PLSI1032E-70LJ

ispLSI and pLSI 1032E ® ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispLSI DEVELOPMENT TOOLS ispVHDL™ Systems — VHDL/Verilog-HDL/Schematic Design Options — Functional/Timing/VHDL Simulation Options ispDS™ Software — Lattice HDL or Boolean Logic Entry — Functional Simulator and Waveform Viewer ispDS+™ HDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation — Static Timing Analyzer ISP Daisy Chain Download Software Functional Block Diagram Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 A0 DQ C7 Output Routing Pool A2 A3 A4 A5 A6 A7 DQ Logic Array C5 DQ GLB C4 C3 DQ C2 C1 Global Routing Pool (GRP) B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 CLK Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins. The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Output Routing Pool 0139A(A1)-isp A1 C6 LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com July 1997 1032E_05 1 Specifications ispLSI and pLSI 1032E Functional Block Diagram Figure 1. ispLSI and pLSI 1032E Functional Block Diagram I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 7 IN 6 RESET Input Bus Generic Logic Blocks (GLBs) D7 D6 Output Routing Pool (ORP) GOE 1/IN 5 GOE 0/IN 4 D5 D4 D3 D2 D1 D0 C7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *SDI/IN 0 *MODE/IN 1 A7 A6 Output Routing Pool (ORP) A5 A4 A3 A2 A1 C6 Output Routing Pool (ORP) C5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 Global Routing Pool (GRP) C4 C3 C2 C1 C0 lnput Bus A0 B0 B1 B2 B3 B4 B5 B6 B7 Clock Distribution Network Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 Megablock *ispEN/NC I/O 16 I/O 17 I/O 18 I/O 19 Input Bus I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 *SDO/IN 2 *SCLK/IN 3 I/O 28 I/O 29 I/O 30 I/O 31 *ISP Control Functions for ispLSI 1032E Only The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI and pLSI 1032E device contains four Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1032E devices are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032E devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. 2 Y0 Y1 Y2 Y3 lnput Bus Specifications ispLSI and pLSI 1032E Absolute Maximum Ratings 1 Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0°C to + 70°C TA = -40°C to + 85°C MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1 UNITS V V V V Table 2-0005/1032E VCC VIL VIH Capacitance (TA=25oC, f=1.0 MHz) SYMBOL PARAMETER Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) Y0 Clock Capacitance TYPICAL 8 15 UNITS pf pf TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V Table 2-0006/1032E C1 C2 Data Retention Specifications PARAMETER Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles MINIMUM 20 10000 100 MAXIMUM – – – UNITS Years Cycles Cycles Table 2-0008/1032E 3 Specifications ispLSI and pLSI 1032E Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 Others 1.5V 1.5V See Figure 2 Table 2-0003/1032E Figure 2. Test Load ≤ 2 ns ≤ 3 ns + 5V R1 Device Output R2 CL * Test Point Output Load Conditions (see Figure 2) TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470Ω ∞ 470Ω ∞ 470Ω R2 390Ω 390Ω 390Ω 390Ω 390Ω CL 35pF 35pF 35pF 5pF 5pF *CL includes Test Fixture and Probe Capacitance. 0213a C Table 2-0004/1032E DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V ≤ VIN ≤ VIL (Max.) 3.5V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VIL 0V ≤ VIN ≤ VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial CONDITION MIN. – 2.4 – – – – – – – TYP. – – – – – – – 190 190 3 MAX. UNITS 0.4 – -10 10 -150 -150 -200 – – V V µA µA µA µA mA mA mA VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4 Table 2-0007/1032E 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25°C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC . 4 Specifications ispLSI and pLSI 1032E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND. 4 # 2 DESCRIPTION 1 -125 – – 125 1 tsu2 + tco1 -100 – – 100 71.0 125 7.0 – 0.0 8.0 – 0.0 – 6.5 – – – – 4.0 4.0 3.5 0.0 10.0 12.5 – – – – 6.0 – – 7.0 – 13.5 – 15.0 15.0 9.0 9.0 – – – – MIN. MAX. MIN. MAX. 7.5 10.0 – – – – 5.0 – – 6.0 – 10.0 – 12.0 12.0 7.0 7.0 – – – – UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 1. 2. 3. 4. A A A – – – A – – – – A – B C B C – – – – 1 2 3 4 5 6 7 8 9 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle 3 Clock Frequency with External Feedback ( ) 91.0 167 5.0 – 0.0 6.0 – 0.0 – 5.0 – – – – 3.0 3.0 3.0 0.0 ( twh 1+ tw1 ) GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low 20 21 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. Table 2-0030A/1032E 5 Specifications ispLSI and pLSI 1032E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND. 4 # 2 DESCRIPTION 1 -90 – – 90.0 1 tsu2 + tco1 -80 – – 80.0 61.0 111 8.5 – 12.0 15.0 – – – – – – -70 15.0 17.5 – – – – 7.0 – – 8.0 – 15.0 – 18.0 18.0 12.0 12.0 – – – – MIN. MAX. MIN. MAX. MIN. MAX. 10.0 12.5 – – – – UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 1. 2. 3. 4. A A A – – – A – – – – A – B C B C – – – – 1 2 3 4 5 6 7 8 9 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback 3 Clock Frequency with External Feedback ( Clock Frequency, Max. Toggle 70.0 56.0 100 9.0 – 0.0 11.0 – 0.0 – 10.0 – – – – 5.0 5.0 4.0 0.0 ( 1 twh + tw1 ) 125 7.5 – 0.0 8.5 – 0.0 – 6.5 – – GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low 20 21 USE – – 4.0 4.0 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 103 NEW 2E-10 DES 0 FOR IGN S 6.0 – – – – 0.0 – – – – – – 4.5 4.5 3.5 0.0 10.0 0.0 8.0 7.0 13.5 15.0 15.0 9.0 9.0 – – – – ) 69.0 6.5 – – – – 7.5 14.0 16.5 16.5 10.0 10.0 – – – – Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section. Table 2-0030B/1032E 6 Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # 2 DESCRIPTION -125 -100 MIN. MAX. MIN. MAX. – – 3.0 0.0 – – – – – – – – – – – – – – 0.1 4.5 – – – – 2.9 – – 0.3 1.9 – – 4.6 4.6 2.3 1.8 2.0 2.3 2.8 3.8 3.9 4.0 3.6 5.0 5.0 0.4 – – 2.3 4.9 3.9 5.4 4.0 1.0 0.0 – – 3.5 0.0 – – – – – – – – – – – – – – 0.5 5.8 – – – – 3.5 – – UNITS Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP 22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 32 GLB Loads 34 4 Prod.Term Bypass Path Delay (Combinatorial) 35 4 Prod. Term Bypass Path Delay (Registered) 36 1 Prod.Term/XOR Path Delay 37 20 Prod. Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Prod.Term Reset to Register Delay 45 GLB Prod. Term Output Enable to I/O Cell Delay 46 GLB Prod. Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay 0.3 2.3 – – 5.0 5.0 2.7 1.9 2.4 2.4 3.0 4.2 5.3 5.3 4.6 5.8 6.3 1.0 – – 2.5 6.2 4.5 7.2 4.7 1.0 0.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tgrp1 tgrp4 tgrp8 tgrp16 tgrp32 GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP torp torpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/1032E 7 Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # 2 DESCRIPTION -90 -80 -70 MIN. MAX. MIN. MAX. MIN. MAX. – – 3.5 0.0 – – – – – – – – – – – – – – 0.3 2.3 – – 5.0 5.0 2.6 2.1 – – 3.5 0.0 – – – – 0.3 2.7 – – 5.4 5.4 2.8 2.2 – – 4.0 0.0 – – – – – – – – – – – – – – 0.5 8.8 – – – – 4.8 – – 0.3 3.3 – – 6.1 6.0 2.8 2.5 2.5 3.2 4.0 5.6 8.8 7.2 8.3 8.7 9.2 1.6 – – 2.9 6.8 5.8 9.0 6.2 1.0 0.0 UNITS Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP 22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 32 GLB Loads 34 4 Prod.Term Bypass Path Delay (Combinatorial) 35 4 Prod. Term Bypass Path Delay (Registered) 36 1 Prod.Term/XOR Path Delay 37 20 Prod. Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Prod.Term Reset to Register Delay 45 GLB Prod. Term Output Enable to I/O Cell Delay 46 GLB Prod. Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GLB t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP USE 0.2 6.8 – – – – 4.1 – – torp torpbp 103 NEW 2E-10 DES 0 FOR IGN S 2.3 2.6 – – 3.2 – 4.4 – 5.7 6.1 5.6 6.8 7.1 0.4 – – 2.9 6.3 5.1 7.1 5.3 1.0 0.0 – – – – – – 0.5 7.9 – – – – 4.5 – – tgrp1 tgrp4 tgrp8 tgrp16 tgrp32 2.5 2.8 3.5 4.8 7.1 6.7 6.6 7.8 8.2 1.3 – – 2.9 6.4 5.5 8.0 5.8 1.0 0.0 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036B/1032E 8 Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # DESCRIPTION -125 -100 UNITS MIN. MAX. MIN. MAX. – – – – – 1.4 1.4 0.8 0.0 0.8 – 1.3 9.9 4.3 4.3 2.7 1.4 1.4 1.8 0.0 1.8 2.8 – – – – – 1.5 1.5 0.8 0.0 0.8 – 2.0 10.0 5.1 5.1 3.9 1.5 1.5 1.8 0.0 1.8 4.3 Outputs tob tsl toen todis tgoe Clocks 49 Output Buffer Delay 50 Output Buffer Delay, Slew Limited Adder 51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line 56 Clk Delay, Clock GLB to Global GLB Clk Line 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line 59 Global Reset to GLB and I/O Registers ns ns ns ns ns ns ns ns ns ns ns tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr Global Reset 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1032E 9 Specifications ispLSI and pLSI 1032E Internal Timing Parameters1 PARAM. # DESCRIPTION -90 -80 -70 UNITS MIN. MAX. MIN. MAX. MIN. MAX. – – – – – 1.7 5.3 5.3 3.7 – 2.1 5.7 5.7 4.3 – – – – – 1.5 1.5 0.8 0.0 0.8 – 2.6 10.0 6.2 6.2 5.8 1.5 1.5 1.8 0.0 1.8 4.6 Outputs 50 Output Buffer Delay, Slew Limited Adder 51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers 103 NEW 2E-10 DES 0 FOR IGN S tob tsl toen todis tgoe Clocks 49 Output Buffer Delay ns ns ns ns ns ns ns ns ns ns ns 10.0 – 10.0 – – – USE tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr 1.4 2.4 0.8 0.0 0.8 – 1.4 2.9 1.8 0.0 1.8 1.5 2.6 1.5 3.1 1.8 0.0 1.8 4.5 0.8 0.0 0.8 – Global Reset 1. Internal Timing Parameters are not tested and are for reference only. 4.5 Table 2-0037B/1032E 10 Specifications ispLSI and pLSI 1032E ispLSI and pLSI 1032E Timing Model I/O Cell GRP Feedback Ded. In #34 GRP4 #30 GRP Loading Delay #29, 31 - 33 Comb 4 PT Bypass GLB Reg Bypass #39 GLB Reg Delay D RST Reset #59 #40 - 43 Q ORP Bypass #48 ORP Delay #47 #49, 50 I/O Pin (Output) GLB ORP I/O Cell #28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27 I/O Pin (Input) Reg 4 PT Bypass #35 20 PT XOR Delays #36 - 38 #51, 52 #59 Clock Distribution Y1,2,3 #55 - 58 Control RE PTs OE #44 - 46 CK 0491 Y0 GOE 0,1 #54 #53 Derivations of tsu, th and tco from the Product Term Clock 1 tsu = = = 2.2 ns = = = = 3.5 ns = = = = 10.9 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) – (#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9) Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3) th tco Derivations of tsu, th and tco from the Clock GLB 1 tsu = = = 2.9 ns = = = = 2.7 ns = = = = 5.5 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) – (#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8) Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) – (#22 + #30 + #37) (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0) Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) th tco 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125. Table 2-0042a/1032E 11 Specifications ispLSI and pLSI 1032E Maximum GRP Delay vs GLB Loads 6.0 ispLSI and pLSI 1032E-70 GRP Delay (ns) 5.0 4.0 ispLSI and pLSI 1032E-80 ispLSI and pLSI 1032E-90/100 ispLSI and pLSI 1032E-125 3.0 2.0 1.0 1 4 8 16 GLB Load 32 GRP/GLB/1032E Power Consumption Power consumption in the ispLSI and pLSI 1032E device depends on two primary factors: the speed at which the device is operating, and the number of product terms Figure 3. Typical Device Power Consumption vs fmax 350 300 ispLSI and pLSI 1032E used. Figure 3 shows the relationship between power and operating speed. ICC (mA) 250 200 150 100 0 20 40 60 80 100 125 150 fmax (MHz) Notes: Configuration of eight 16-bit counters Typical current at 5V, 25°C I CC can be estimated for the ispLSI and pLSI 1032E using the following equation: I CC (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the program in the device, the actual I CC should be verified. 0127/1032E 12 Specifications ispLSI and pLSI 1032E Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0/IN 4 PLCC PIN NUMBERS 26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 67 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18 TQFP PIN NUMBERS 17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 66 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, DESCRIPTION 20, Input/Output Pins - These are the general purpose I/O pins used by the logic 28, array. 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. GOE 1/IN 5 84 87 IN 6, IN 7 ispEN**/NC 2, 23 19 89, 14 10 Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Ground (GND) Vcc 24, 49, 74, 99, 25, No connect. 50, 75, 100 Table 2-0002A/1032E SDI*/IN 0 25 16 MODE*/IN 1 42 37 SDO*/IN 2 44 39 SCLK*/IN 3 61 60 RESET Y0 Y1 24 20 66 15 11 65 Y2 63 62 Y3 62 61 GND VCC NC 1, 22, 43, 64 13, 38, 63, 88 12, 64 1, 26, 51, 76, 2, 27, 52, 77, 21, 65 * ispLSI 1032E only ** ispEN for ispLSI 1032E; NC for pLSI 1032E, must be left floating or tied to V , must not be grounded or tied CC to any other signal. 13 Specifications ispLSI and pLSI 1032E Pin Configurations ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram **GOE 1/IN 5 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 11 10 9 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND *ispEN/NC RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 **GOE 0/IN 4 Y1 VCC GND Y2 Y3 *SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 ispLSI 1032E pLSI 1032E Top View 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 *MODE/IN 1 *SDO/IN 2 I/O 24 I/O 7 I/O 8 I/O 9 GND * Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only). ** Pins have dual function capability which is software selectable. 0123-32-isp 14 I/O 39 GND IN 6 Specifications ispLSI and pLSI 1032E Pin Configurations ispLSI 1032E 100-Pin TQFP Pinout Diagram NC NC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND **GOE 1/IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND ispEN RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ispLSI 1032E Top View NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 **GOE 0/IN 4 Y1 VCC GND Y2 Y3 *SCLK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC * Pins have dual function capability. ** Pins have dual function capability which is software selectable. 0766A-32E-isp NC NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *MODE/IN1 GND *SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 15 Specifications ispLSI and pLSI 1032E Part Number Description (is)pLSI Device Family 1032E – XXX X X X Grade Blank = Commercial I = Industrial Package J = PLCC T = TQFP Power L = Low 0212/1032E Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 70 = 70 MHz fmax ispLSI and pLSI 1032E Ordering Information COMMERCIAL FAMILY fmax (MHz) 125 125 100 ispLSI 100 90 90 80 80 70 70 125 100 pLSI 90 80 70 tpd (ns) 7.5 7.5 10 10 10 10 12 12 15 15 7.5 10 10 12 15 ORDERING NUMBER ispLSI 1032E-125LJ ispLSI 1032E-125LT ispLSI 1032E-100LJ ispLSI 1032E-100LT ispLSI 1032E-90LJ* ispLSI 1032E-90LT* ispLSI 1032E-80LJ* ispLSI 1032E-80LT* gn si de ne w al l ispLSI 1032E-70LJ pLSI 1032E-125LJ pLSI 1032E-100LJ pLSI 1032E-90LJ* pLSI 1032E-80LJ* pLSI 1032E-70LJ ispLSI 1032E-70LT SI fo r pL s. PACKAGE 84-Pin PLCC 84-Pin PLCC 100-Pin TQFP 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 84-Pin PLCC 84-Pin PLCC 84-Pin PLCC 84-Pin PLCC Table 2-0041A/1032E is *ispLSI 1032E-100 recommended for new designs. FAMILY ispLSI fmax (MHz) 70 70 se INDUSTRIAL ORDERING NUMBER ispLSI 1032E-70LJI ispLSI 1032E-70LTI PACKAGE 84-Pin PLCC 100-Pin TQFP Table 2-0041B/1032E tpd (ns) 15 15 N ot e: U 16 Copyright © 1997 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter, ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com July 1997