Dynamic Block Reed-Solomon Encoder User’s Guide
August 2010
IPUG40_03.6
Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 8
Chapter 2. Functional Description ...................................................................................................... 10
General Description ............................................................................................................................................ 10
Field Polynomial......................................................................................................................................... 11
Generator Polynomial ................................................................................................................................ 11
Shortened Codes ....................................................................................................................................... 11
Output Latency........................................................................................................................................... 11
Functional Description......................................................................................................................................... 11
Multiplier Array ........................................................................................................................................... 11
Adder Array ................................................................................................................................................ 11
Remainder Array ........................................................................................................................................ 12
Control........................................................................................................................................................ 12
Basis Conversion Modules......................................................................................................................... 12
Signal Descriptions ............................................................................................................................................. 12
Timing Specifications .......................................................................................................................................... 13
Chapter 3. Parameter Settings ............................................................................................................ 17
Reed-Solomon Encoder Configuration GUI ........................................................................................................ 18
Core Configuration ..................................................................................................................................... 18
RS Parameters........................................................................................................................................... 18
Check Symbols .......................................................................................................................................... 19
Block Size Type ......................................................................................................................................... 19
Implementation Parameters ....................................................................................................................... 19
Optional Output Ports................................................................................................................................. 19
Summary............................................................................................................................................................. 20
Chapter 4. IP Core Generation............................................................................................................. 21
Licensing the IP Core.......................................................................................................................................... 21
Getting Started .................................................................................................................................................... 21
IPexpress-Created Files and Top Level Directory Structure............................................................................... 23
Instantiating the Core .......................................................................................................................................... 25
Running Functional Simulation ........................................................................................................................... 25
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 25
Hardware Evaluation........................................................................................................................................... 26
Enabling Hardware Evaluation in Diamond:............................................................................................... 26
Enabling Hardware Evaluation in ispLEVER:............................................................................................. 26
Updating/Regenerating the IP Core .................................................................................................................... 26
Regenerating an IP Core in Diamond ........................................................................................................ 26
Regenerating an IP Core in ispLEVER ...................................................................................................... 27
Chapter 5. Support Resources ............................................................................................................ 28
Lattice Technical Support.................................................................................................................................... 28
Online Forums............................................................................................................................................ 28
Telephone Support Hotline ........................................................................................................................ 28
E-mail Support ........................................................................................................................................... 28
Local Support ............................................................................................................................................. 28
Internet ....................................................................................................................................................... 28
References.......................................................................................................................................................... 28
LatticeECP ........................................................................................................................................... /EC28
LatticeECP2M ............................................................................................................................................ 28
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Table of Contents
LatticeECP3 ............................................................................................................................................... 29
LatticeSC/M................................................................................................................................................ 29
LatticeXP.................................................................................................................................................... 29
LatticeXP2.................................................................................................................................................. 29
Related Information............................................................................................................................................. 29
Revision History .................................................................................................................................................. 29
Appendix A. Resource Utilization ....................................................................................................... 30
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 30
Ordering Part Number................................................................................................................................ 30
LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 31
Ordering Part Number................................................................................................................................ 31
LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 32
Ordering Part Number................................................................................................................................ 32
LatticeECP3 FPGAs............................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
LatticeXP FPGAs ................................................................................................................................................ 33
Ordering Part Number................................................................................................................................ 33
LatticeXP2 FPGAs .............................................................................................................................................. 33
Ordering Part Number................................................................................................................................ 33
LatticeSC and LatticeSCM FPGAs ..................................................................................................................... 34
Ordering Part Number................................................................................................................................ 34
IPUG40_03.6, August 2010
3
Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 1:
Introduction
Lattice's Dynamic Block Reed-Solomon Encoder IP core can be used for forward error correction in many terrestrial communication, space communication, data storage, and data retrieval systems. The encoder is compliant
with several industrial standards including the more recent IEEE 802.16-2004. The Reed-Solomon Encoder IP core
provides a customizable solution allowing forward error correction in other non-standard applications as well.
The encoder supports both a fixed, as well as a variable number of total symbols (block) and check symbols. In the
variable configurations, either the block size or both the block size and check symbols can be dynamically varied
through ports. The core allows dynamic output check symbols puncturing in the fixed check symbols configurations.
This user's guide describes the functionality and implementation of the Reed-Solomon Encoder. Lattice also offers
a Reed-Solomon Decoder core that can serve as a complementary pair for decoding. For more information on Lattice products, refer to the Lattice web site at www.latticesemi.com.
Quick Facts
Table 1-1 through Table 1-9 give quick facts about the Dynamic Block Reed-Solomon Encoder IP core for LatticeEC™, LatticeECP™, LatticeECP2™, LattceECP2M™, LattticeSC™, LatticeSCM™, LatticeXP™,
LatticeXP2™, and LatticeECP3™ devices.
Table 1-1. Dynamic Block Reed-Solomon Encoder IP core for LatticeEC Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFEC1E
LFEC1E
Synthesis
LFEC1E
LFEC1E
LFEC3E
300
500
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
600
®
®
Diamond 1.0 or ispLEVER 8.1
Synopsys® Synplify™ Pro for Lattice D-2009.12L-1
Aldec® Active-HDL™ 8.2 Lattice Edition
Simulation
IPUG40_03.6, August 2010
LFEC1E
LFEC20E-5F672C
Lattice Implementation
Design Tool
Support
ATSC
IEEE
802.162004 SC
Lattice EC
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Mentor Graphics® ModelSim™ SE 6.3F
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-2. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFECP6E
LFECP20E-5F672C
300
500
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
600
Lattice Implementation
Design Tool
Support
ATSC
IEEE
802.162004 SC
Lattice ECP
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Diamond 1.0 or ispLEVER 8.1
Synthesis
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
Mentor Graphics ModelSim SE 6.3F
Table 1-3. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP2 Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFE2-6E
LFE2-50E-7F484C
300
400
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
Synthesis
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
IPUG40_03.6, August 2010
ATSC
IEEE
802.162004 SC
Lattice ECP2
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Mentor Graphics ModelSim SE 6.3F
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-4. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP2M Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFE2M20E
LFE2M35E-7F484C
300
400
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
ATSC
IEEE
802.162004 SC
Lattice ECP2M
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Diamond 1.0 or ispLEVER 8.1
Synthesis
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
Mentor Graphics ModelSim SE 6.3F
Table 1-5. Dynamic Block Reed-Solomon Encoder IP core for LatticeSC Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFSC3GA15E
LFSC3GA25E-7F900C
300
500
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
Synthesis
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
IPUG40_03.6, August 2010
ATSC
IEEE
802.162004 SC
Lattice SC
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Mentor Graphics ModelSim SE 6.3F
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-6. Dynamic Block Reed-Solomon Encoder IP core for LatticeSCM Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFSCM3GA15EP1
LFSCM3GA25EP1-7F900C
300
500
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
ATSC
IEEE
802.162004 SC
Lattice SCM
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Diamond 1.0 or ispLEVER 8.1
Synthesis
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
Mentor Graphics ModelSim SE 6.3F
Table 1-7. Dynamic Block Reed-Solomon Encoder IP core for LatticeXP Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFXP3E
LFXP20E-5F256C
300
500
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
600
Lattice Implementation
Design Tool
Support
Synthesis
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
IPUG40_03.6, August 2010
ATSC
IEEE
802.162004 SC
Lattice XP
Targeted Device
Resource
Utilization
DVB
IEEE
802.162004 SCa
Mentor Graphics ModelSim SE 6.3F
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-8. Dynamic Block Reed-Solomon Encoder IP core for LatticeXP2 Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
DVB
FPGA Families Supported
Lattice XP2
Minimal Device Needed
LFXP2-5E
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
IEEE
802.162004 SC
LFXP2-17E-7FT256C
300
400
300
400
400
2700
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
ATSC
IEEE
802.162004 SCa
Diamond 1.0 or ispLEVER 8.1
Synthesis
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
Mentor Graphics ModelSim SE 6.3F
Table 1-9. Dynamic Block Reed-Solomon Encoder IP core for LatticeECP3 Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
OC-192
Core
Requirements
CCSDS
DVB
FPGA Families Supported
Minimal Device Needed
LUTs
sysMEM EBRs
Registers
LFE3-35EA
LFE3-95E-8FN484CES
300
500
300
400
400
2800
0
0
0
0
0
0
300
400
300
300
300
500
Lattice Implementation
Design Tool
Support
Synthesis
IEEE
802.162004 SC
Lattice ECP3
Targeted Device
Resource
Utilization
ATSC
IEEE
802.162004 SCa
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Simulation
Mentor Graphics ModelSim SE 6.3F
Features
• 3- to 12-bit symbol width
• Configurable field polynomial
• Configurable generator polynomial: starting root and root spacing
• User-defined codewords
– Maximum of 4095 symbols
– Maximum of 256 check symbols
– Shortened codes
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Introduction
• Selectable Reed-Solomon standards
– OC-192
– DVB
– CCSDS
– ATSC
– IEEE 802.16-2004 WirelessMAN-SCa/OFDM
– IEEE 802.16-2004 WirelessMAN-SC
• Fully synchronous
• Registered input selection
• Systematic encoder
• Full handshaking capability
• Dynamically variable block size
• Dynamically variable check symbols
• Dynamically variable check symbols puncturing
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Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 2:
Functional Description
Figure 2-1 illustrates the operation of a systematic encoder.
Figure 2-1. Reed-Solomon Encoder Block Diagram
Multiplier
Array
Control Bus
din
rstn
enable
byp
ibstart
clk
blocksize
Adder
Array
Remainder
Array
Control
dout
status
outvalid
rfi
obstart
obend
rfib
ibend
numchks
General Description
Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy
in the data before it is transmitted to allow error correction at the receiver. The redundant data (check symbols) are
transmitted with the original data to the receiver. A Reed-Solomon Decoder is used in the receiver to correct any
transmission errors. This type of error correction is widely used in data communications applications such as Digital
Video Broadcast (DVB) and Optical Carriers (i.e. OC-192).
Reed-Solomon codes are written in the format RS(n,k) where k is the number of information symbols and n is the
total number of symbols in a codeword or block. Each symbol in the codeword is wsymb bits wide. The first k symbols in the Reed-Solomon Encoder output are information symbols and the last n-k symbols are check symbols.
This type of encoder, where the information symbols are unchanged and are followed by check symbols in the output, is called a systematic encoder. Figure 2-1 illustrates the operation of a systematic encoder.
Reed-Solomon codes are defined on a finite field known as a Galois field. The size of the field is determined by the
symbol width, wsymb, and is equal to 2wsymb. When n is less than its maximum value of 2wsymb - 1, it is referred to as
a shortened code.
Reed-Solomon codes are characterized by two polynomials: the generator polynomial and the field polynomial.
The field polynomial defines the Galois field where the information and check symbols belong. The generator polynomial determines the check symbol generation and it is a prime polynomial for all codewords (i.e. all codewords
are exactly divisible by the generator polynomial). Both the field and generator polynomials are user configurable.
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Functional Description
Field Polynomial
The field polynomial is defined by its decimal value (f). The decimal value of a field polynomial is obtained by setting x=2 in the polynomial. For example, the polynomial x2 + x + 1 in decimal value is 22 + 2 + 1 = 7. The field polynomial can be specified as any prime polynomial with decimal value up to 2wsymb+1 - 1.
Generator Polynomial
The generator polynomial determines the value of the check symbols. The generator polynomial can be defined by
the parameters starting root (gstart) and root spacing (rootspace). The general form of the generator polynomial is given by:
(x - rootspace (gstart + i))
n-k-1
g(x) =
(1)
i=0
where a (alpha) is called the primitive element of the field polynomial. For a binary Galois field GF(2), a (alpha) is
equal to 2.
Shortened Codes
When the size of the Reed-Solomon codewords, n, is less than the maximum possible size, 2wsymb - 1, they are
called shortened codes. For example, RS (204,188) when wsymb = 8 is a shortened code. Only the non-zero data
is transmitted to the encoder (i.e., 188 in the above example). The encoder then generates the required check symbols from the non-zero data.
Output Latency
Output Latency for the Reed-Solomon Encoder core is defined as the number of clock cycles between the sampling of the first input data and the availability of the first data at the output port. It is three clock cycles when the
inputs are registered and two clock cycles otherwise.
Functional Description
The Reed-Solomon Encoder utilizes Multiplier, Adder and Remainder arrays to perform finite field arithmetic. A
block diagram of the Reed-Solomon Encoder is shown in Figure 2-2. The following section explains the operation
of the arrays and the Control block.
Figure 2-2. Systematic Reed-Solomon Encoder
Codeword
n-k Check Symbols
DATA k-1
DATA 1
DATA 0
Reed-Solomon
Encoder
CHECKn-k-1
k Information Symbols
CHECK 1 CHECK 0 DATA k-1
DATA 1
DATA 0
wsymb bits wide
Multiplier Array
The Multiplier array performs the Galois field multiplication between the generator coefficients and the modulo-2
sum of input data and feedback data. This multiplication is optimized during the processing of the core.
Adder Array
The Adder array performs modulo-2 addition on the data from the previous element of the Remainder array and the
result of the corresponding Galois field multiplication from the Multiplier array. The outputs from the Adder array are
latched into the Remainder array on each clock cycle.
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Functional Description
Remainder Array
The Remainder array is a shift register array. It stores the remainder polynomial after the polynomial division. The
remainder polynomial becomes the check symbols once all information symbols have been processed. The
Remainder array shifts-in the data from the Adder array while the information symbols are processed. When all the
information symbols have been processed, the polynomial multiplication stops and the contents of the Remainder
array are output to dout.
Control
The Control block generates all control signals and determines the state of the Reed-Solomon Encoder. The
rstn, enable, byp, ibstart, and clk inputs control the state of the encoder. The Control block uses these
inputs to control the state of the Multiplier, Adder and Remainder arrays as well as to generate the rfi, status,
outvalid, ibend, obstart and obend outputs.
Basis Conversion Modules
When core type is selected as CCSDS, then two additional Basis Conversion modules are added to the Reed-Solomon Encoder. These modules comply to the CCSDS specification. Dual-basis to normal polynomial-basis conversion module is added after the din input port and normal polynomial-basis to dual-basis conversion module is
added before the dout output port.
Table 2-1. Default Field Polynomials
Symbol Width
Default Field Polynomial
Decimal Value
3
x3 + x + 1
11
4
4
x +x+1
19
5
x5 + x2 +1
37
6
6
x +x+1
67
7
x 7 + x3 + 1
137
8
x8 + x4 + x3 + x2 + 1
285
9
x9 + x4 + 1
529
10
3
10
x +x +1
1033
11
x11 + x2 + 1
2053
12
12
6
4
x +x +x +x+1
4179
Signal Descriptions
Table 2-2 shows the definitions of the interface signals available with the Reed-Solomon encoder IP Core
Table 2-2. Interface Signal Descriptions
Port
Bits
I/O
Description
All Configurations
clk
1
I
System clock. This is the reference clock for input and output data.
rstn
1
I
System wide asynchronous active-low reset signal.
enable
1
I
Enables the encoder to process data on din. When low, the input data is ignored and dout
holds its state.
byp
1
I
When asserted, the data at the input din is passed directly to the output dout after the pipeline latency of the core.
ibstart
1
I
Indicates that the data on din is the first information symbol of a new codeword. This signal is
ignored if byp is high or enable is low.
din
3-12
I
Input data port. The wsymb parameter defines the port width of this signal.
dout
3-12
O
Output data port. The wsymb parameter defines the port width of this signal.
1
O
Indicates the information symbols are present on dout or byp is asserted.
status
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Functional Description
Table 2-2. Interface Signal Descriptions (Continued)
Port
Bits
I/O
Description
For Variable Check Symbols or Punctured Check Symbols
This signal is used for two functions.
1) When the parameter Variable check symbols is “Yes”, this port is used to provide the
number of check symbols value. The width of this port is equal to ceil(log2(Max. number of
check symbols))
2-9
numchks
I
2) When the parameter Puncture check symbols is “Yes”, this port is used to indicate the
number of transmitted check symbols out of total of Number of check symbols. Only the
first numchks number of check symbols are given out at the dout port. The width of this port is
equal to ceil(log2(Number of check symbols)).
In both cases, the value at this port is read only when ibstart is high.
For Variable Block Size Type Only (When the Parameter Variable Block Size is “Yes”)
3-12
I
Variable block size value. The value at this port is read only when ibstart is high. The wsymb
parameter defines the port width of this signal.
outvalid
1
O
Output data valid. This indicates valid data is present on dout.
rfi
1
O
Ready for input. This indicates the encoder is ready to receive input data. Typically, this signal
is high when the core is ready to read information symbols and turns low when check symbols
are being calculated.
rfib
1
O
Ready for input block. This indicates that the encoder is ready to receive the first information
symbol in the block.
ibend
1
O
Input block end. This indicates that the encoder is sampling the last information symbol on the
data input port din.
obstart
1
O
Output block start. This indicates first output data of the codeword on the dout port.
obend
1
O
Output block end. This indicates last output data of the codeword on the dout port.
blocksize
Optional I/Os
Timing Specifications
Figure 2-3 illustrates the timing of an RS (7,3) double pipelined encoder during normal operation. The diagram
shows a typical behavior for the handshake signals status, rfi and outvalid.
Figure 2-3. Timing of an RS (7,3) Double Pipelined Encoder
clk
rstn
ibstart
enable
byp
din
dout
D00
D01
D02
X
D00
X
X
D01
D02
X
D10
C00
C01
D11
C02
D12
C03
status
rfi
outvalid
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Functional Description
Figure 2-4 shows the timing of an RS (7,3) double pipelined encoder with byp asserted during the operation of the
encoder. The handshake signals are identical to normal operation, but the output is shifted due to the extra bypass
data.
Figure 2-4. Timing of an RS (7,3) Double Pipelined Encoder with byp Asserted
clk
rstn
ibstart
enable
byp
din
D00
D01
D02
dout
DBP
X
X
X
X
D00
D01
D02
DBP
C00
D10
C01
D11
C02
status
rfi
outvalid
Figure 2-5 shows the timing of an RS (7,3) double pipelined encoder with enable de-asserted during the operation of the encoder. The de-assertion of enable results in corresponding invalid outputs happening after a few
cycles determined by the output latency and indicated by outvalid going low. When outvalid is low, the output
handshake signals maintain their last state.
Figure 2-5. Timing of an RS (7,3) Double Pipelined Encoder with enable De-asserted
clk
rstn
ibstart
enable
byp
din
dout
D00
D01
D02
X
D00
X
X
X
X
D01
D02
D02
C00
D10
C01
D11
C02
status
rfi
outvalid
Figure 2-6 shows the timing of an RS (7,3) double pipelined encoder with ibstart re-asserted during the operation of the encoder. The handshake signal rfi goes high to indicate the encoder is ready to receive a new set of
data when ibstart is re-asserted during encoding.
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Functional Description
Figure 2-6. Timing of an RS (7,3) Double Pipelined Encoder with ibstart Re-asserted
clk
rstn
ibstart
enable
byp
din
dout
D00
D01
D02
D10
X
D00
D01
D11
D02
D12
C00
X
X
X
D10
D11
D12
status
rfi
outvalid
Figure 2-7 explains the timing of an RS (7,3) double pipelined encoder with variable block size and variable check
symbols. The figure also shows the timing of the optional output ports outvalid, obstart, obend, rfi, rfib
and ibend.
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Functional Description
Figure 2-7. Timing of an RS (7,3) Encoder with Variable Block Size and Variable Check Symbols
clk
rstn
enable
byp
ibstart
blocksize
7
7
7
numchks
4
4
4
din
D00
D01
dout
D02
D00
D01
D02
C00
D10
D11
D12
C01
C02
C03
D10
D11
D12
C10
D20
D21
C11
C12
status
outvalid
obstart
obend
rfi
rfib
ibend
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Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 3:
Parameter Settings
The IPexpress™ tool is used to create IP and architectural modules in the Diamond and ispLEVER software. Refer
to “IP Core Generation” on page 24 for a description on how to generate the IP.
The Dynamic Block Reed-Solomon Encoder IP core GUI allows the user to create a custom configuration or to
select one of the standard configurations: OC-192, CCSDS, DVB, ATSC, IEEE 802.16-2004 WirelessMANSCa/OFDM and IEEE 802.16-2004 WirelessMAN-SC. Table 3-1 provides the list of user configurable parameters
for the Reed-Solomon Encoder IP core.
Table 3-1. User Configurable Parameters
Parameter
Range
Default
Custom, OC-192, CCSDS, DVB, ATSC, IEEE 802.162004 SCa, IEEE 802.16-2004 SC
OC-192
Yes,/No
Yes
3 - 12 bits
8 bits
5 - 8191
285
gstart
0 - 65535
0
rootspace
1 - 65535
1
{Constant, Variable} if “Variable check symbols” is not
checked. {Variable} if “Variable check symbols” is
checked.
Constant
Core Type
Core type
Connect reset port to GSR
RS Parameters
wsymb
fpoly
Block Size Type
Block size type
n
3 - 4095
255
k
1 - 4093
239
Variable check symbols
Yes,/No
No
Max. number of
check symbols
3 - 128
Even number of
check symbols
Yes,/No
Number of
check symbols
2 - 256
Puncture
check symbols
Yes,/No
Check Symbols
32
No
16
No
Implementation Parameters
Registered
input
Yes,/No
Use mult.
opt. algorithm
Yes,/No
Yes
Yes
Optional Output Ports
rfi
Yes,/No
No
outvalid
Yes,/No
No
rfib
Yes,/No
No
ibend
Yes,/No
No
obstart
Yes,/No
No
obend
Yes,/No
No
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Parameter Settings
Reed-Solomon Encoder Configuration GUI
Figure 3-1 shows the contents of the Reed-Solomon Encoder IP core Configuration GUI.
Figure 3-1. Reed-Solomon Encoder IP core Configuration GUI
Core Configuration
This parameter selects between custom and pre-defined standard configurations. The Parameter Settings of the
Standard Configurations table in the Dynamic Block Reed-Solomon Encoder User’s Guide defines the fixed parameter values for different standard configurations.
RS Parameters
wsymb
This parameter specifies the symbol width.
fpoly
This parameter specifies the decimal value of the field polynomial. Table 2-1 on page 12 defines the default field
polynomial parameter values for different symbol widths.
gstart
This parameter specifies the offset value of the generator polynomial. The starting value for the first root of the generator polynomial is calculated as rootspace * gstart.
rootspace
This parameter specifies root spacing of the generator polynomial. The value of rootspace must satisfy the following equation: GCD(rootspace, 2wsymb-1) = 1. GCD is Greatest Common Divisor.
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Parameter Settings
Check Symbols
Variable Check Symbols
Specifies whether the number of check symbols is variable through the input port.
Number of Check Symbols
This parameter specifies the maximum value for number of check symbols provided through the input port
numchks. This parameter selection is available when Variable check symbols is checked.
Even Number of Check Symbols
If this is checked, only even values should be provided on the input port numchks. If an odd value is given, it is
internally set to the next lower even value. If this parameter is checked the core area is smaller and performance is
better. This parameter selection is available when Variable check symbols is checked.
Pucture Check Symbols
This paramete enables the puncturing of check symbols, whereby only the first few check symbols are transmitted.
The number of transmitted check symbols value is provided through the input port numchks. This parameter selection is available when Block size type is selected as “Variable” and Variable check symbols is not checked.
Block Size Type
Specifies whether block size is provided as a constant value or varied through the input port. If Block size type is
selected as “Variable”, the block size is read from the input port blocksize.
Block Size(n)
This parameter specifies the total number of symbols in the codeword. This parameter can be defined only when
block size is constant.
Information Symbols(k)
This parameter specifies the number of information symbols in the codeword. This parameter can be defined only
when block size is constant
Implementation Parameters
Registered Input
This parameter specifies whether the inputs are registered. Having registered inputs improves the performance of
the core, but the latency will increase by one.
Use Mult. Opt. Algorithm
This parameter enables Galois field multiplication optimization algorithm to be used before synthesis. If this option
is not checked, the optimization is left to the synthesis tool. In most cases, using an optimization algorithm results
in improved performance and reduced area.
Optional Output Ports
rfi
Determines whether the output port rfi (ready for input) is present.
outvalid
Determines whether the output port outvalid (output valid) is present.
rfib
Determines whether the output port rfib (ready for input block or first data in the codeword) is present.
ibend
Determines whether the output port ibend (input block end or last information symbol in the codeword) is present.
obstart
Determines whether the output port obstart (output block start) is present.
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Parameter Settings
obend
Determines whether the output port obend (output block end) is present.
Summary
The Summary entry in Figure 3-1 shows the output latency of the IP core based on the specified parameters. Output Latency for the Reed-Solomon Encoder IP core is defined as the number of clock cycles between the sampling
of the first input data and the availability of the first data at the output port. It is three clock cycles when the inputs
are registered and two clock cycles otherwise.
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Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 4:
IP Core Generation
This chapter provides information on licensing the Dynamic Block Reed-Solomon Encoder IP core, generating the
core using the Diamond or ispLEVER software IPexpress tool, running functional simulation, and including the core
in a top-level design. The Lattice Dynamic Block Reed-Solomon Encoder IP core can be used in LatticeECP3,
LatticeECP2/M, LatticeECP, LatticeSC/M, LatticeXP, and LatticeXP2 device families.
Licensing the IP Core
An IP license is required to enable full, unrestricted use of the Dynamic Block Reed-Solomon Encoder IP core in a
complete, top-level design. An IP license that specifies the IP core and device family is required to enable full use
of the core in Lattice devices. Instructions on how to obtain licenses for Lattice IP cores are given at:
http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm
Users may download and generate the IP core and fully evaluate the core through functional simulation and implementation (synthesis, map, place and route) without an IP license. The Dynamic Block Reed-Solomon Encoder IP
core also supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP
core that operate in hardware for a limited time (approximately four hours) without requiring an IP license (see
“Instantiating the Core” on page 25 for further details). However, a license is required to enable timing simulation, to
open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout limitation.
Getting Started
The Dynamic Block Reed-Solomon Encoder IP core is available for download from the Lattice IP Server using the
IPexpress tool. The IP files are automatically installed using ispUPDATE technology in any customer-specified
directory. After the IP core has been installed, the IP core will be available in the IPexpress GUI dialog box shown in
Figure 4-1.
The IPexpress tool GUI dialog box for the Dynamic Block Reed-Solomon Encoder IP is shown in Figure 4-1. To
generate a specific IP core configuration the user specifies:
• Project Path – Path to the directory where the generated IP files will be loaded.
• File Name – “username” designation given to the generated IP core and corresponding folders and files.
• (Diamond) Module Output – Verilog or VHDL.
• (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
• Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3,
etc.). Only families that support the particular IP core are listed.
• Part Name – Specific targeted part within the selected device family.
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IP Core Generation
Figure 4-1. IPexpress Dialog Box (Diamond Version)
Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in
ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool
online help for further information.
To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display
the Dynamic Block Reed-Solomon Encoder IP core Configuration GUI, as shown in Figure 4-2. From this dialog
box, the user can select the IP parameter options specific to their application. Refer to “Parameter Settings” on
page 17 for more information on the parameter settings.
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IP Core Generation
Figure 4-2. Configuration Dialog Box (Diamond Version)
IPexpress-Created Files and Top Level Directory Structure
When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are
generated in the specified “Project Path” directory. The directory structure of the generated files is shown in
Figure 4-3.
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IP Core Generation
Figure 4-3. Lattice Dynamic Block Reed-Solomon Encoder IP core Directory Structure
Table 4-1 provides a list of key files created by the IPexpress tool and how they are used. The IPexpress tool creates several files that are used throughout the design cycle. The names of most of the created files are customized
to the user’s module name specified in the IPexpress tool.
Table 4-1. File List
File
Description
_inst.v
This file provides an instance template for the IP.
_bb.v
This file provides the synthesis black box for the user’s synthesis.
.ngo
The ngo files provide the synthesized IP core used by Diamond or ispLEVER. This file needs to
be pointed to by the Build step by using the search path property.
.lpc
This file contains the IPexpress tool options used to recreate or modify the core in the IPexpress
tool.
.ipx
The IPX file holds references to all of the elements of an IP or Module after it is generated from
the IPexpress tool (Diamond version only). The file is used to bring in the appropriate files during the design implementation and analysis. It is also used to re-load parameter settings into the
IP/Module generation GUI when an IP/Module is being re-generated.
_top.[v,vhd]
This file provides a module which instantiates the RS Encoder core. This file can be easily modified for the user's instance of the RS Encoder core. This file is located in the
rsenc_eval//src/rtl/top/ directory.
_generate.tcl
This file is created when GUI “Generate” button is pushed and generation is invoked. This file
may be run from command line.
_generate.log
This is the IPexpress scripts log file.
_gen.log
This is the IPexpress IP generation log file.
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IP Core Generation
Instantiating the Core
The \ and subtending directories provide files supporting Dynamic Block Reed-Solomon Encoder
IP core evaluation. The \ directory shown in Figure 4-3 contains files and folders with content that
is constant for all con-figurations of the Dynamic Block Reed-Solomon Encoder. The \ subfolder
(\resnc_core0 in this example) contains files and folders with content specific to the username configuration.
The \rsenc_eval directory is created by IPexpress the first time the core is generated and updated each time the
core is regenerated. A \ directory is created by IPexpress each time the core is generated and regenerated each time the core with the same file name is regenerated. A separate \ directory is generated for cores with different names, e.g. rsenc_core0, rsenc_core1, etc.
Running Functional Simulation
Simulation support for the Dynamic Block Reed-Solomon Encoder IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator, Mentor Graphics ModelSim simulator. The functional simulation includes a configurationspecific behavioral model of the Dynamic Block Reed-Solomon Encoder IP core. The test bench sources stimulus
to the core, and monitors output from the core. The generated IP core package includes the configuration-specific
behavior model (_beh.v) for func-tional simulation in the “Project Path” root directory. The simulation
scripts supporting ModelSim evaluation simulation is provided in
\\rsenc_eval\\sim\modelsim\scripts. The simulation script supporting
Aldec evaluation simulation is provided in
\\rsenc_eval\\sim\aldec\scripts. Both Modelsim and Aldec simulation is
supported via test bench files provided in \\rsenc_eval\testbench. Models required for
simulation are provided in the corresponding \models folder. Users may run the Aldec evaluation simulation by
doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro.
3. Browse to folder \\rsenc_eval\\sim\aldec\scripts and execute one of
the "do" scripts shown.
Users may run the Modelsim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder
\rsenc_eval\\sim\modelsim\scripts.
3. 3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation completes, a pop-up window will appear asking “Are you sure you want to finish?”
Answer No to analyze the results (answering Yes closes ModelSim).
Synthesizing and Implementing the Core in a Top-Level Design
Synthesis support for the Dynamic Block Reed-Solomon Encoder IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The Dynamic Block Reed-Solomon Encoder IP core itself is synthesized and is provided
in NGO format when the core is generated in IPexpress. Users may synthesize the core in their own top-level
design by instantiating the core in their top-level as described previously and then synthesizing the entire design
with either Synplify or Precision RTL Synthesis. The following text describes the evaluation implementation flow for
Windows platforms. The flow for Linux and UNIX platforms is described in the Readme file included with the IP
core. The top-level files _top.v are provided in
\\rsenc_eval\\src\rtl\top. Push-button implementation of the reference
design is supported via Diamond or ispLEVER project files, .syn, located in the following directory:
\\rsenc_eval\\impl\(synplify or precision).
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IP Core Generation
To use this project file in Diamond:
1. Choose File > Open > Project.
2. Browse to
\\rsenc_eval\\impl\synplify (or precision) in the Open Project
dialog box.
3. Select and open .ldf. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project.
4. Select the Process tab in the left-hand GUI window.
5. Implement the complete design via the standard Diamond GUI flow.
To use this project file in ispLEVER:
1. Choose File > Open Project.
2. Browse to
\\rsenc_eval\\impl\synplify (or precision) in the Open Project
dialog box.
3. Select and open .syn. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project.
4. Select the device top-level entry in the left-hand GUI window.
5. Implement the complete design via the standard ispLEVER GUI flow.
Hardware Evaluation
The Dynamic Block Reed-Solomon Encoder IP core supports Lattice’s IP hardware evaluation capability, which
makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in user-defined designs.
Enabling Hardware Evaluation in Diamond:
Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be
enabled/disabled in the Strategy dialog box. It is enabled by default.
Enabling Hardware Evaluation in ispLEVER:
In the Processes for Current Source pane, right-click the Build Database process and choose Properties from the
dropdown menu. The hardware evaluation capability may be enabled/disabled in the Properties dialog box. It is
enabled by default.
Updating/Regenerating the IP Core
By regenerating an IP core with the IPexpress tool, you can modify any of its settings including device type, design
entry method, and any of the options specific to the IP core. Regenerating can be done to modify an existing IP
core or to create a new but similar one.
Regenerating an IP Core in Diamond
To regenerate an IP core in Diamond:
1. In IPexpress, click the Regenerate button.
2. In the Regenerate view of IPexpress, choose the IPX source file of the module or IP you wish to regenerate.
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IP Core Generation
3. IPexpress shows the current settings for the module or IP in the Source box. Make your new settings in the Target box.
4. If you want to generate a new set of files in a new location, set the new location in the IPX Target File box. The
base of the file name will be the base of all the new file names. The IPX Target File must end with an .ipx extension.
5. Click Regenerate. The module’s dialog box opens showing the current option settings.
6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the
About tab in IPexpress for links to technical notes and user guides. IP may come with additional information. As
the options change, the schematic diagram of the module changes to show the I/O and the device resources
the module will need.
7. To import the module into your project, if it’s not already there, select Import IPX to Diamond Project (not
available in stand-alone mode).
8. Click Generate.
9. Check the Generate Log tab to check for warnings and error messages.
10.Click Close.
The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP
core required to support simulation, synthesis and implementation. The IP core may be included in a user's design
by importing the .ipx file to the associated Diamond project. To change the option settings of a module or IP that is
already in a design project, double-click the module’s .ipx file in the File List view. This opens IPexpress and the
module’s dialog box showing the current option settings. Then go to step 6 above.
Regenerating an IP Core in ispLEVER
To regenerate an IP core in ispLEVER:
1. In the IPexpress tool, choose Tools > Regenerate IP/Module.
2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core
you wish to regenerate, and click Open.
3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core
in the Source Value box. Make your new settings in the Target Value box.
4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base
of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension.
5. Click Next. The IP core’s dialog box opens showing the current option settings.
6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the
About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and
the device resources the IP core will need.
7. Click Generate.
8. Click the Generate Log tab to check for warnings and error messages.
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Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 5:
Support Resources
This chapter contains information about Lattice Technical Support, additional references, and document revision
history.
Lattice Technical Support
There are a number of ways to receive technical support.
Online Forums
The first place to look is Lattice Forums (http://www.latticesemi.com/support/forums.cfm). Lattice Forums contain a
wealth of knowledge and are actively monitored by Lattice Applications Engineers.
Telephone Support Hotline
Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m.
Pacific Time.
• For USA & Canada: 1-800-LATTICE (528-8423)
• For other locations: +1 503 268 8001
In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English
language only.
• For Asia: +86 21 52989090
E-mail Support
• techsupport@latticesemi.com
• techsupport-asia@latticesemi.com
Local Support
Contact your nearest Lattice Sales Office.
Internet
www.latticesemi.com
References
• Neal Glover and Trent Dudley, “Practical error correction design for engineers”, Cirrus Logic, Colorado, 1991
• IEEE Standard for Local and metropolitan area networks, Part 16: Air Interface for Fixed Broadband Wireless
Access Systems, October 2004 (IEEE Std 802.16-2004)[
• Advanced Television Systems Committee, Inc., www.atsc.org
• Digital Video Broadcasting Project, www.dvb.org
• The Consultative Committee for Space Data Systems (CCSDS), www.ccsds.org
LatticeECP/EC
• HB1000, LatticeECP/EC Family Handbook
LatticeECP2M
• HB1003, LatticeECP2M Family Handbook
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Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Support Resources
LatticeECP3
• HB1009, LatticeECP3 Family Handbook
LatticeSC/M
• DS1004, LatticeSC/M Family Data Sheet
LatticeXP
• HB1001, LatticeXP Family Handbook
LatticeXP2
• DS1009, Lattice XP2 Datasheet
Related Information
For more information regarding core usage and design verification, refer to the Reed-Solomon Decoder IP Core
User’s Guide.
Revision History
Date
—
Version
Change Summary
—
3.0
Previous Lattice releases.
03.1
4.0
Core version 4.0: Full support of IPexpress flow, including
LatticeECP/EC, LatticeECP2, LatticeSC, and LatticeXP
December 2006
03.2
4.1
Updated appendices and added support for the LatticeECP2M family.
May 2007
03.3
4.2
Added support for LatticeXP2 FPGA family.
August 2006
Updated LatticeECP/EC appendix.
Updated LatticeSC appendix.
May 2009
03.4
4.3
Added support for LatticeECP3 FPGA family.
Updated Global Reset.
Updated all appendices.
July 2010
03.5
4.3
Divided document into chapters. Added table of contents.
Added Quick Facts tables in Chapter 1, “Introduction.”
Added new content in Chapter 4, “IP Core Generation.”
August, 2010
03.6
IPUG40_03.6, August 2010
4.4
Added support for Diamond software throughout.
29
Dynamic Block Reed-Solomon Encoder User’s Guide
Appendix A:
Resource Utilization
This appendix gives resource utilization information for Lattice FPGAs using the Dynamic Block Reed-Solomon
Encoder IP core.
IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER
design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER
help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at:
www.latticesemi.com/software.
LatticeECP and LatticeEC FPGAs
The utilization data shown in Table A-1 is derived from the parameter settings listed in Table A-2.
Table A-1. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM™
EBRs
I/Os
fMAX (MHz)
OC-192
132
260
207
0
24
179
CCSDS
214
426
338
0
24
178
DVB
140
273
210
0
24
174
IPexpress User-Configurable Mode
ATSC
161
320
245
0
24
169
IEEE 802.16-2004 WirelessMAN SCa
168
324
255
0
37
176
IEEE 802.16-2004 WirelessMAN SC
1222
2438
450
0
38
71
1. Performance and utilization data are generated using an LFEC/P20E-5F672C device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP/EC family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeEC/ECP devices is RSENC-DBLK-E2-U4.
Table A-2. Parameter Settings of the Evaluation Packages
Configuration
Description
1 (default)
OC-192
2
3
CCSDS
DVB
4
ATSC
5
6
IEEE 802.16- IEEE 802.162004 SCa
2004 SC
Rs Parameters
Wsymb
8
8
8
8
8
8
285
391
285
285
285
285
Gstart
0
112
0
0
0
0
Rootspace
1
11
1
1
1
1
N/A
N/A
N/A
N/A
N/A
Yes
Fpoly
Check Symbols
Variable check symbols
Number of check symbols
N/A
N/A
N/A
N/A
16
N/A
Max. number of check symbols
N/A
N/A
N/A
N/A
N/A
32
Even number of check symbols
N/A
N/A
N/A
N/A
N/A
Yes
Puncture check symbols
N/A
N/A
N/A
N/A
Yes
N/A
Constant
Constant
Constant
Constant
Variable
Variable
255
255
204
207
255
255
Block Size Type
Block size type
Block size (n)
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Resource Utilization
Table A-2. Parameter Settings of the Evaluation Packages (Continued)
Configuration
1 (default)
2
3
4
5
6
239
223
188
187
N/A
N/A
Registered input
Yes
Yes
Yes
Yes
Yes
Yes
Use mult.opt.algorithm
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Information symbols (k)
Implementation Parameters
Optional Output Ports
rfi
outvalid
No
No
No
No
No
No
rfib
Yes
Yes
Yes
Yes
Yes
Yes
Ibend
No
No
No
No
No
No
obstart
No
No
No
No
No
No
obend
No
No
No
No
No
No
Summary
Latency
3 clock cycles 3 clock cycles 3 clock cycles 3 clock cycles 3 clock cycles 3 clock cycles
LatticeECP2 and LatticeECP2S FPGAs
The utilization data shown in Table A-3 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-3. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
133
262
201
0
24
320
CCSDS
204
404
330
0
24
250
DVB
137
269
201
0
24
276
ATSC
159
315
233
0
24
282
IEEE 802.16-2004 WirelessMAN SCa
173
336
246
0
37
280
IEEE 802.16-2004 WirelessMAN SC
1287
2565
442
0
38
112
IPexpress User-Configurable Mode
1. Performance and utilization data are generated using an LFE2-50E/SE-7F484C device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP2S family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeECP2/S devices is RSENC-DBLK-P2-U4.
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Resource Utilization
LatticeECP2M and LatticeECP2MS FPGAs
The utilization data shown in Table A-4 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-4. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
133
262
201
0
24
257
CCSDS
204
404
330
0
24
247
IPexpress User-Configurable Mode
DVB
137
269
201
0
24
286
ATSC
159
315
233
0
24
266
IEEE 802.16-2004 WirelessMAN SCa
173
336
246
0
37
295
IEEE 802.16-2004 WirelessMAN SC
1287
2565
442
0
38
128
1. Performance and utilization data are generated using an LFE2M35E/SE-7F484C device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP2M and LatticeECP2MS families.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeECP2M/S devices is RSENC-DBLK-PM-U4.
LatticeECP3 FPGAs
The utilization data shown in Table A-5 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-5. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
129
251
201
0
24
400
CCSDS
203
398
330
0
24
400
IPexpress User-Configurable Mode
DVB
129
254
201
0
24
400
ATSC
150
293
233
0
24
400
IEEE 802.16-2004 WirelessMAN SCa
172
332
246
0
37
400
IEEE 802.16-2004 WirelessMAN SC
1276
2533
506
0
38
202
1. Performance and utilization data are generated using an LFE3-95E-8FN484CES device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP3 family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeECP3 devices is RSENC-DBLK-P3-U4.
IPUG40_03.6, August 2010
32
Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Resource Utilization
LatticeXP FPGAs
The utilization data shown in Table A-6 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-6. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
132
260
207
0
24
185
CCSDS
214
426
338
0
24
175
IPexpress User-Configurable Mode
DVB
140
273
210
0
24
183
ATSC
161
320
245
0
24
164
IEEE 802.16-2004 WirelessMAN SCa
168
324
255
0
37
178
IEEE 802.16-2004 WirelessMAN SC
1222
2438
450
0
38
68
1. Performance and utilization data are generated using an LFXP20E-5F256C device with Lattice Diamond 1.0 and Synplify Pro D-2009.12L1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the
LatticeXP family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeXP devices is RSENC-DBLK-XP-U4.
LatticeXP2 FPGAs
The utilization data shown in Table A-7 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-7. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
133
262
201
0
24
291
CCSDS
204
404
330
0
24
264
IPexpress User-Configurable Mode
DVB
137
269
201
0
24
282
ATSC
159
315
233
0
24
278
IEEE 802.16-2004 WirelessMAN SCa
173
336
246
0
37
262
IEEE 802.16-2004 WirelessMAN SC
1287
2565
442
0
38
92
1. Performance and utilization data are generated using an LFXP2-17E-7FT256C device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeXP2 family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeXP2 devices is RSENC-DBLK-X2-U4.
IPUG40_03.6, August 2010
33
Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Resource Utilization
LatticeSC and LatticeSCM FPGAs
The utilization data shown in Table A-8 is derived from the parameter settings listed in Table A-2 on page 30.
Table A-8. Performance and Resource Utilization1
Slices
LUTs
Registers
sysMEM
EBRs
I/Os
fMAX (MHz)
OC-192
129
251
201
0
24
400
CCSDS
203
398
330
0
24
400
IPexpress User-Configurable Mode
DVB
129
254
201
0
24
400
ATSC
150
293
233
0
24
400
IEEE 802.16-2004 WirelessMAN SCa
172
332
246
0
37
400
IEEE 802.16-2004 WirelessMAN SC
1276
2533
506
0
38
202
1. Performance and utilization data are generated using an LFSC/M3GA25E-7F900C device with Lattice Diamond 1.0 and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeSCM family.
Ordering Part Number
The Ordering Part Number (OPN) for all configurations of the Dynamic Block Reed-Solomon Encoder core targeting LatticeSC/M devices is RSENC-DBLK-SC-U4.
IPUG40_03.6, August 2010
34
Dynamic Block Reed-Solomon Encoder User’s Guide
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