2D Scaler IP Core User’s Guide
August 2013
IPUG88_01.2
Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Release Information .............................................................................................................................................. 5
Chapter 2. Functional Description ........................................................................................................ 6
Key Concepts........................................................................................................................................................ 6
Block Diagram....................................................................................................................................................... 6
Algorithm and Supported Filter Kernels ................................................................................................................ 7
Dynamic Parameter Updating ............................................................................................................................... 7
Rounding............................................................................................................................................................... 8
Primary I/O ............................................................................................................................................................ 9
Interface Descriptions ........................................................................................................................................... 9
Video Input/Output ....................................................................................................................................... 9
Parameter Register Read/Write Interface .................................................................................................. 10
Control Signals and Timing ........................................................................................................................ 10
Chapter 3. Parameter Settings ............................................................................................................ 14
Architecture ......................................................................................................................................................... 15
Frame Dimensions ..................................................................................................................................... 15
Filter Physical Characteristics .................................................................................................................... 15
I/O Specification .................................................................................................................................................. 16
Implementation.................................................................................................................................................... 17
Chapter 4. IP Core Generation............................................................................................................. 18
Licensing the IP Core.......................................................................................................................................... 18
Getting Started .................................................................................................................................................... 18
Configuring the 2D Scaler IP Core in IPexpress ................................................................................................. 18
IPexpress-Created Files and Top-Level Directory Structure...................................................................... 20
Instantiating the Core ................................................................................................................................. 21
Running Functional Simulation .................................................................................................................. 21
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 21
Hardware Evaluation........................................................................................................................................... 22
Enabling Hardware Evaluation in Diamond................................................................................................ 22
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 22
Updating/Regenerating the IP Core .................................................................................................................... 22
Regenerating an IP Core in Diamond ........................................................................................................ 22
Regenerating an IP Core in ispLEVER ...................................................................................................... 23
Chapter 5. Support Resources ............................................................................................................ 24
Lattice Technical Support.................................................................................................................................... 24
Online Forums............................................................................................................................................ 24
Telephone Support Hotline ........................................................................................................................ 24
E-mail Support ........................................................................................................................................... 24
Local Support ............................................................................................................................................. 24
Internet ....................................................................................................................................................... 24
References.......................................................................................................................................................... 24
Revision History .................................................................................................................................................. 24
Appendix A. Resource Utilization ....................................................................................................... 25
LatticeECP3 Devices .......................................................................................................................................... 25
Ordering Part Number................................................................................................................................ 25
LatticeECP2M and LatticeECP2MS Devices ...................................................................................................... 25
Ordering Part Number................................................................................................................................ 25
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Table of Contents
LatticeECP2 and LatticeECP2S Devices ............................................................................................................ 25
Ordering Part Number................................................................................................................................ 26
LatticeXP2 Devices ............................................................................................................................................. 26
Ordering Part Number................................................................................................................................ 26
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Chapter 1:
Introduction
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible
architecture supports a wide variety of scaling algorithms. The highly configurable design takes advantage of the
embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either
streaming video or bursty input video data. In-system input and output frame sizes updating is possible on a frame
basis.
Quick Facts
Table 1-1 gives quick facts about the 2D Scaler IP core.
Table 1-1. 2D Scaler IP Core Quick Facts
2D Scaler IP Core Configuration
480P to 720P
(YCbCr4:2:2, serial)
FPGA Families
Supported
Core
Requirements Minimum Device
Required
Targeted Device
LFE2-6E
LFE3-17EA
LFE2-6E
LFE3-17EA
LFE2-12E
LFE3-17EA
LFE2-20E7F484C
LFE3-17EA8FN484C
LFE2-20E7F484C
LFE3-17EA8FN484C
LFE2-20E7F484C
LFE3-17EA8FN484C
4x4
4x4
4x4
Pixel width
8
8
8
Coefficient width
9
9
9
Registers
953
955
1116
1113
1515
1522
LUTs
1278
1343
1267
1338
1715
1829
EBRs
4
4
7
7
9
9
MULT9x9
8
8
16
16
24
24
Lattice
Implementation
Design Tool
Support
720P to 1080P
(RGB, parallel, dynamic)
LatticeECP3™, LatticeECP2M™, LatticeECP2MS,
LatticeECP2™, LatticeECP2S, LatticeXP2™
Taps
Resource
Utilization
720P to 480P
(YCbCr4:2:2, parallel)
Lattice Diamond® 1.3 or ispLEVER® 8.1
Synthesis
Synopsys® Synplify™ Pro for Lattice E-2011.03L
Simulation
Aldec® Active-HDL™ 8.2 Lattice Edition
Mentor Graphics® ModelSim™ SE 6.3F
Features
• Supports single-color, YCbCr 4:2:2, YCbCr 4:4:4 and RGB video formats
• Supports serial and parallel processing
• Dynamic parameter updating
• Supports multi-scaling algorithms
• Configurable number of filter taps for Lanczos coefficient set
• Configurable number of phases for Bicubic, Mitchell and Lanczos coefficient sets
• Configurable pixel data width
• Configurable coefficient width
• Configurable parameter bus width and separate parameter bus clock
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Introduction
• Selectable memory type for line buffer and coefficient memories
• Option for sharing vertical and horizontal filter coefficient memories
Release Information
• 2D Scaler IP Core version 2.0; last updated September 2, 2011
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2D Scaler IP Core User’s Guide
Chapter 2:
Functional Description
Key Concepts
Video scaling is the process of calculating values for the pixels in an output frame of dimensions Xout-by-Yout from
the values of pixels in an input frame of dimensions Xin-by-Yin. Scaling up by an integer multiple involves inserting
new pixels between the original pixels in the input frame and calculating each new pixel value as a weighted sum of
nearby original pixel values. The number of original pixel values and their weights depends on the scaling algorithm
employed. In general, including more original pixels in the calculation results in a higher quality result (but requires
more FPGA resources).
Conversely, down-scaling by an integer multiple involves dropping unneeded input pixels. Typically, the drop operation is preceded by a two-dimensional low-pass filter to avoid a jagged appearance in the output frame. The lowpass filtering operation is itself a weighted sum of nearby input pixels. The set of weights is referred to as the “filter
kernel” or “coefficient set”.
Block Diagram
The high-level architecture of the 2D Scaler IP core is shown in Figure 2-1.
Figure 2-1. 2D Scaler IP Core Block Diagram
Pixels In
Line
Buffer
Vertical
Filter
Horizontal
Filter
Pixels Out
The 2D Scaler IP core allows different scaling factors for the horizontal and vertical dimensions. It uses a separable
filter architecture which, as depicted by the block diagram, performs the vertical and horizontal scaling in two steps.
The input pixel data is first stored in the line buffer. The size of the line buffer is dictated by the number of the vertical filter taps and the maximum input frame width. Pixel data are read out of the line buffer and passed to the vertical filter column by column. Likewise, the vertical filter coefficients are read out of the coefficient memories and
passed to the vertical filter for processing along with the pixel data. The row outputs from the vertical filter are then
passed to the horizontal filter to generate the output pixels. Output precision control is then performed on the final
output pixel value.
The 2D Scaler IP core supports in-system re-programming of the input and output frame sizes via a parameter bus.
If the IP core is configured for dynamic parameter updating then the maximum input and output frame resolutions
need to be specified so that line buffer and various counters can be configured appropriately. Also the parameter
bus can be configured to run on a separate clock. By default, the parameter bus runs on the input pixel sample
clock.
When processing YCbCr 4:2:2 video format, the core averages neighboring pixels’ Cb and Cr vectors to construct
YCbCr 4:4:4 format for scaling.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Functional Description
Algorithm and Supported Filter Kernels
Video scaling is a process of generating pixels that do not exist in the original image. In order to compute an output
pixel from a set of fixed input pixels, it is necessary to map the output pixel to the input pixel grid and estimate the
location of the output pixel relative to the input pixels. The algorithm approximates the output pixel value by using a
filter with coefficients weighted accordingly.
A 4-tap Bicubic filter uses four adjacent input pixels to interpolate an output pixel, for example. The spaces between
the adjacent pixels are divided into a configurable number of positions called phases so that the output pixel is
mapped into one of these positions. The weights of the coefficients are determined by the positions or phases and
how close they are to the output pixel. The higher the number of phases, the more accurate is the interpolated output pixel.
Figure 2-2. Scaling Process with 4-Tap Bicubic Filter
1+v
2-v
v
Pn-1
Pn
1-v
Dst
Pn+1
Pn+2
Dst = Pn-1 * coeff(1+v) + Pn * coeff(v) + Pn+1 * coeff(1-v) + Pn+2 * coeff(2-v)
= Source Pixel
= Destination Pixel
The 2D Scaler IP core supports five adaptive scaling kernels: 1-tap nearest neighbor, 2-tap bilinear, 4-tap bicubic,
4-tap Mitchell and configurable multi-tap Lanczos filters. The range for the size of the Lanczos filters is from 4 taps
to 12 taps. Filter coefficients are generated at compile time when the kernel is configured.
Dynamic Parameter Updating
The 2D Scaler IP core supports in-system input and output frame sizes updating via a register read/write interface
called parameter ports. The parameter registers are listed below.
Address
Registers
Size
R/W
Description
0x0000
FRMWIDTH
32
R/W
Input frame width register – The FRMWIDTH value must be
the input frame width minus 1. The minimum value is 31, and
the maximum value is the maximum input frame width specified
on the IP GUI minus 1. The default value is the maximum value.
Input frame width must be an even number for YCbCr4:2:2 format (i.e. FRMWIDTH must be odd).
0x0004
FRMHEIGHT
32
R/W
Input frame height register – The FRMHEIGHT must be the
input frame height minus 1. The minimum value is 31, and the
maximum value is the maximum input frame height specified on
the IP GUI minus 1. The default value is the maximum value.
0x0008
OUTWIDTH
32
R/W
Output frame width register – The OUTWIDTH must be the
output frame width minus 1. The minimum value is 31, and the
maximum value is the maximum output frame width specified
on the IP GUI minus 1. The default value is the maximum value.
Output frame width must be an even number for YCbCr4:2:2
format (i.e. OUTWIDTH must be odd).
0x000C
OUTHEIGHT
32
R/W
Output frame height register – The OUTHEIGHT must be the
output frame height minus 1. The minimum value is 31, and the
maximum value is the maximum output frame height specified
on the IP GUI minus 1. The default value is the maximum value.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Functional Description
Address
Registers
Size
R/W
Description
0x0010
VSFACTOR
32
R/W
Vertical scaling factor register –
VSFACTOR = ((FRMHEIGHT+1)*(1 Open Project.
2. Browse to \\scaler_eval\\impl\(synplify or precision) in the Open Project dialog box.
3. Select and open .syn. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project.
4. Select the device top-level entry in the left-hand GUI window.
5. Implement the complete design via the standard ispLEVER GUI flow.
Hardware Evaluation
The 2D Scaler IP core supports the Lattice IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring
the purchase of an IP license. It may also be used to evaluate the core in hardware in user-defined designs.
Enabling Hardware Evaluation in Diamond
Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be
enabled/disabled in the Strategy dialog box. It is enabled by default.
Enabling Hardware Evaluation in ispLEVER
In the Processes for Current Source pane, right-click the Build Database process and choose Properties from
the drop-down menu. The hardware evaluation capability may be enabled/disabled in the Properties dialog box. It
is enabled by default.
Updating/Regenerating the IP Core
By regenerating an IP core with IPexpress, you can modify any of its settings including device type, design entry
method, and any of the options specific to the IP core. Regenerating can be done to modify an existing IP core or to
create a new but similar one.
Regenerating an IP Core in Diamond
To regenerate an IP core in Diamond:
1. In IPexpress, click the Regenerate button.
2. In the Regenerate view of IPexpress, choose the IPX source file of the module or IP you wish to regenerate.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
IP Core Generation
3. IPexpress shows the current settings for the module or IP in the Source box. Make your new settings in the
Target box.
4. If you want to generate a new set of files in a new location, set the new location in the IPX Target File box. The
base of the file name will be the base of all the new file names. The IPX Target File must end with an .ipx extension.
5. Click Regenerate. The module’s dialog box opens showing the current option settings.
6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the
About tab in IPexpress for links to technical notes and user’s guides. IP may come with additional information.
As the options change, the schematic diagram of the module changes to show the I/O and the device
resources the module will need.
7. To import the module into your project if it is not already there, select Import IPX to Diamond Project (not
available in stand-alone mode).
8. Click Generate.
9. Check the Generate Log tab to check for warnings and error messages.
10. Click Close.
The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP
core required to support simulation, synthesis and implementation. The IP core may be included in a user’s design
by importing the .ipx file to the associated Diamond project. To change the option settings of a module or IP that is
already in a design project, double-click the module’s .ipx file in the File List view. This opens IPexpress and the
module’s dialog box showing the current option settings. Then go to step 6 above.
Regenerating an IP Core in ispLEVER
To regenerate an IP core in ispLEVER:
1. In the IPexpress tool, choose Tools > Regenerate IP/Module.
2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core
you wish to regenerate, and click Open.
3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP
core in the Source Value box. Make your new settings in the Target Value box.
4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The
base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc
extension.
5. Click Next. The IP core’s dialog box opens showing the current option settings.
6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the
About tab in the IPexpress tool for links to technical notes and user’s guides. The IP core may come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and
the device resources the IP core will need.
7. Click Generate.
8. Click the Generate Log tab to check for warnings and error messages.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Chapter 5:
Support Resources
Lattice Technical Support
There are a number of ways to receive technical support as listed below.
E-mail Support
techsupport@latticesemi.com
Local Support
Contact your nearest Lattice sales office.
Internet
www.latticesemi.com
References
• HB1009, LatticeECP3 Family Handbook
• HB1003, LatticeECP2/M Family Handbook
• HB1002, LatticeXP2 Family Handbook
Revision History
Date
Document
Version
IP Core
Version
February 2011
01.0
1.0
Initial release.
October 2011
01.1
2.0
Updated to support 2D Scaler IP version 2.0.
August 2013
01.2
02.1
Modified the title for the Resource Utilization tables
Change Summary
Updated corporate logo.
Updated Lattice Technical Support information.
Updated References format.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Appendix A:
Resource Utilization
This appendix gives resource utilization information for Lattice FPGAs using the 2D Scaler IP core. IPexpress is the
Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools.
Details regarding the use of IPexpress can be found in the IPexpress, Diamond and ispLEVER online help systems. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at:
www.latticesemi.com/software.
LatticeECP3 Devices
Table A-1. Performance and Resource Utilization Examples1
Video
Format
Max. Input
Frame Size
Max. Output
Frame Size
YCbCr422
720x480
1280x720
Parallel
Pixels Coefficient
Processing Dynamic Taps Width
Width
Registers LUT4s Slices EBRs MULT9X9s fMAX
No
No
4x4
8
9
955
1343
948
4
8
271
YCbCr422
1280x720
720x480
Yes
No
4x4
8
9
1113
1338
996
7
16
246
RGB
1280x720
1920x1080
Yes
Yes
4x4
8
9
1522
1829
1356
9
24
275
1. Performance and utilization data are generated targeting a LFE3-35EA-8FN484C device using Lattice Diamond 1.3 and Synplify Pro E2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP3 family.
Ordering Part Number
The Ordering Part Number (OPN) for the 2D Scaler IP core targeting LatticeECP3 devices is SCALER-E3-U1.
LatticeECP2M and LatticeECP2MS Devices
Table A-2. Performance and Resource Utilization Examples1
Video
Format
Max. Input
Frame Size
Max. Output
Frame Size
YCbCr422
720x480
1280x720
Parallel
Pixels Coefficient
Processing Dynamic Taps Width
Width
Registers LUT4s Slices EBRs MULT9X9s fMAX
No
No
4x4
8
9
953
1278
936
4
8
249
YCbCr422
1280x720
720x480
Yes
No
4x4
8
9
1116
1267
991
7
16
262
RGB
1280x720
1920x1080
Yes
Yes
4x4
8
9
1515
1715
1362
9
24
268
1. Performance and utilization data are generated targeting a LFE2M20E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP2M and LatticeECP2MS family.
Ordering Part Number
The Ordering Part Number (OPN) for the 2D Scaler IP core targeting LatticeECP2M/S devices is SCALER-PM-U1.
LatticeECP2 and LatticeECP2S Devices
Table A-3. PPerformance and Resource Utilization Examples1
Video
Format
Max. Input
Frame Size
Max. Output
Frame Size
Parallel
Pixels Coefficient
Processing Dynamic Taps Width
Width
Registers LUT4s Slices EBRs MULT9X9s fMAX
YCbCr422
720x480
1280x720
No
No
4x4
8
9
955
1278
936
4
8
248
YCbCr422
1280x720
720x480
Yes
No
4x4
8
9
1116
1267
991
7
16
263
RGB
1280x720
1920x1080
Yes
Yes
4x4
8
9
1515
1715
1362
9
24
269
1. Performance and utilization data are generated targeting a LFE2-20E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP2 and LatticeECP2S family.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013
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2D Scaler IP Core User’s Guide
Resource Utilization
Ordering Part Number
The Ordering Part Number (OPN) for the 2D Scaler IP core targeting LatticeECP2 and LatticeECP2S devices is
SCALER-P2-U1.
LatticeXP2 Devices
Table A-4. Performance and Resource Utilization Examples1
Video
Format
Max. Input
Frame Size
Max. Output
Frame Size
Parallel
Pixels Coefficient
Processing Dynamic Taps Width
Width
Registers LUT4s Slices EBRs MULT9X9s fMAX
YCbCr422
720x480
1280x720
No
No
4x4
8
9
953
1278
936
4
8
YCbCr422
1280x720
720x480
Yes
No
4x4
8
9
1116
1267
991
7
16
233
RGB
1280x720
1920x1080
Yes
Yes
4x4
8
9
1515
1715
1362
9
24
238
220
1. Performance and utilization data are generated targeting a LFXP2-30E-7F484C device using Lattice Diamond 1.3 and Synplify Pro E2011.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeXP2 family.
Ordering Part Number
The Ordering Part Number (OPN) for the 2D Scaler IP core targeting LatticeXP2 devices is SCALER-X2-U1.
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2D Scaler IP Core User’s Guide
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