Data Sheet
SiI9134 HDMI Deep Color Transmitter
Data Sheet
Document # SiI-DS-0193-F
This document was watermarked on 06-08-2010 at 15:08:06 local time.
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
July 2010
Copyright Notice
Copyright © 2009-2010 , Inc. All rights reserved. These materials contain proprietary and inmation (including trade
secrets, copyright and other interests) of , Inc. You may not these materials except your bona fide non-commercial
evaluation of your potential purchase of products and/services from or its affiliates, and/or in connection with your
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You have no right to copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these
materials, or otherwise make these materials available, in whole or in part, to any third party.
Patents
The subject matter described herein contains one or more inventions claimed in patents and/or patents pending owned by , Inc., including but not
limited to the inventions claimed in US patents #6, 914, 637, #6, 151, 334, #6, 026, 124, #5, 974, 464 and #5, 825, 824.
Trademark Acknowledgment
™, VastLane™, SteelVine™, PinnaClear™, Simplay™, Simplay HD™, LiquiHD, Satalink™, InstaPort™, and TMDS™ are trademarks or registered trademarks of , Inc. in the United States and other countries. HDMI™, the HDMI logo and High-Definition Multimedia Interface™ are trademarks or registered
This document contains inmation subject to the Export Administration Regulations (EAR) andhasaclassification of EAR99
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0
Revision History
Revision
A
B
Date
11/2006
12/2006
Comment
Tables of AC and DC specification were updated.
Updated DC specifications and overall matting.
B01
C
2/2007
4/2007
UpdatedI CCT and ISTBY specifications.
Added Audio Down-sampler inmation and HDMI design considerations
D
E
E01
F
10/2007
8/2009
5/2010
7/2010
Corrected DC and Digital I/O specifications, hot plug inmation, and other content
Updated to include 3D provided in the HDMI 1.4 Standard.
Updated page 1 and layout to prepare Data Brief; minor editing throughout.
Updated Table 22; clarified 3D inmation.
© 2009-2010 . Inc. All rights reserved.
ii
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Table of Contents
General Description ..............................................................................................................................................................1
HDMI Output ...................................................................................................................................................................1
Digital Video Interface .....................................................................................................................................................1
Digital Audio Interface .....................................................................................................................................................1
Control Capability ............................................................................................................................................................1
Package .............................................................................................................................................................................1
SiI9134 Transmitter Compared with SiI9030 and SiI9034 Devices .....................................................................................2
Pin Diagram ..........................................................................................................................................................................3
Description ...........................................................................................................................................................................4
Video Data Input and Conversion ....................................................................................................................................5
Video Processing Pipeline ............................................................................................................................................5
Input Clock Multiplier/Divider ............. .......................................................................................................................5
Video Data Capture Logic ............................................................................................................................................5
Configuration to Support Deep-color ...........................................................................................................................5
Common Video Input mats
6
Embedded Sync Decoding ............................................................................................................................................6
Data Enable Generator ..................................................................................................................................................6
Re-sampling ..................................................................................................................................................................6
Color Space Converters (CSC) ................................................................................. ...................................................7
14-to-8/10/12-Dither .....................................................................................................................................................7
Color Range Scaling ....................................................................................................................................................7
Clipping ........................................................................................................................................................................8
HDCP Encryption Engine/XOR Mask .........................................................................................................................8
TMDS Digital Core ......................................... ............................................................................................................8
3D Video mats ..............................................................................................................................................................8
3D Video Limitations ................................................................... ...............................................................................9
Audio Data Capture Logic ................................................................................................................................................9
S/PDIF ..........................................................................................................................................................................9
I2S .................................................................................................................................................................................9
One-Bit Audio Input (DSD/SACD) ............................................................................................................................10
High-Bit Rate Audio on HDMI .................................................................................................................................10
Audio Downsampler Limitations... ................................................................................................................................11
HDCP Key ROM ............................................................................................................................................................12
Interrupt Out ...................................................................................................................................................................12
Control and Configuration ..............................................................................................................................................12
Registers/Configuration Logic ....................................................................................................................................12
Microcontroller Slave I2C Interface ...........................................................................................................................12
DDC Master I2C Interface ..........................................................................................................................................12
Electrical Specifications .....................................................................................................................................................14
Absolute Maximum Conditions ......................................................................................................................................14
Normal Operating Conditions .........................................................................................................................................14
DC Specifications ...........................................................................................................................................................15
Digital I/O Specifications ...........................................................................................................................................15
TMDS I/O Specifications ...........................................................................................................................................16
DC Power Supply Pin Specifications .........................................................................................................................17
AC Specifications ...........................................................................................................................................................18
TMDS AC Timing Specifications ..............................................................................................................................18
Audio AC Timing Specifications ...............................................................................................................................18
Video AC Timing Specifications ................................................................................................................................19
Control Timing Specifications ....................................................................................................................................20
Timing Diagrams ............................................................................................................................................................21
Input Timing Diagrams...............................................................................................................................................21
Audio Timing Diagrams .............................................................................................................................................23
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Power Supply Sequencing ......................................................................................................................................... 24
Output Timing Diagrams ........................................................................................................................................... 24
Pin Descriptions ................................................................................................................................................................. 25
Video Input Pins ............................................................................................................................................................ 25
Audio Input Pins ............................................................................................................................................................ 26
Configuration/Programming Pins .................................................................................................................................. 26
Control Pins ................................................................................................................................................................... 26
Differential Signal Data Pins ......................................................................................................................................... 27
Power and Ground Pins ................................................................................................................................................. 27
Data Bus Mappings............................................................................................................................................................ 28
RGB and YCbCr 4:4:4 mats with Separate Syncs ..................................................................................................... 29
YC 4:2:2 mats with Separate Syncs ........................................................................................................................... 32
YC 4:2:2 mats with Embedded Sync ......................................................................................................................... 33
YC Mux 4:2:2 mats with Separate Syncs .................................................................................................................. 35
YC Mux 4:2:2 Embedded Sync mats ........... ............................................................................................................. 37
12/15/18-Bit DMO RGB and YCbCr mats ................................................................................................................ 39
6Design Guidelines ................................................................................................ .. ........................................... 40
Power Supplies ........................................................
....................................................................................... 40
Voltage Ripple Regulation ......................................................................................................................................... 40
Decoupling ................................................................................................................................................................. 40
High-Speed TMDS Signals ........................................................................................................................................... 41
ESD Protection ................................................................................................................ ......................................... 41
Transmitter Layout Guidelines .................................................................................................................................. 41
Protection I2C
Port................................................................................................................................................... 41
Hot Plug Signal Conditioning ........................................................................................................................................ 42
HDMI Design Considerations........................................................................................................................................ 42
HDMI CTS Test ID 7-4: TMDS Differential Rise and Fall Time ............................................................................ 42
Recommendation to pass Test ID 7-4 ........................................................................................................................ 42
EMI Considerations ................................................................................. ..................................................................... 42
Typical Circuit ............................................................................................................................................................... 43
Power Supply Decoupling ......................................................................................................................................... 43
HDMI Port TMDS Connections ................................................................................................................................ 44
Control Signal Connections ....................................................................................................................................... 45
Packaging........................................................................................................................................................................... 46
100-pin TQFP Package Dimensions and Marking Specification .................................................................................. 46
Ordering Inmation ............................................................................................................................................................. 46
References ......................................................................................................................................................................... 47
Standards Documents .................................................................................................................................................... 47
Documents ................................................................................................................................................................... 47
iv
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
List of Figures
Figure 1. SiI9134 System Diagram................................................................................................................................. 1
Figure 2. Pin Diagram .................................................................................................................................................... 3
Figure 3 Functional Block Diagram ............................................................................................................................... 4
Figure 4. Transmitter Video Data Processing Path ......................................................................................................... 5
Figure 5. High Speed Data Transmission ..................................................................................................................... 10
Figure 6. High Bitrate Stream Bee and after Reassembly and Splitting ....................................................................... 10
Figure 7. High Bit Rate Stream After Splitting ............................................................................................................ 10
Figure 8. Simplified I2C Ports ...................................................................................................................................... 12
Figure 8. Master I2C Supported Transactions............................................................................................................... 13
Figure 9. IDCK Clock Cycle/HIGH/LOW Times ........................................................................................................ 21
Figure 10. Control and Data Single-Edge Setup/Hold Times to IDCK ........................................................................ 21
Figure 11. Dual-Edge Setup/Hold Times to IDCK ....................................................................................................... 21
Figure 12. VSYNC and HSYNC Delay Times from/to DE ........................................................................................ 22
Figure 13. DE HIGH/LOW Times ............................................................................................................................... 22
Figure 14. RESET# Minimum Timings ....................................................................................................................... 22
Figure 15. S/PDIF Input Timings
23
Figure 16. I2S Input Timings ........................................................................................................................................ 23
Figure 17. DSD Input Timings ..................................................................................................................................... 23
Figure 18. MCLK Timings ........................................................................................................................................... 23
Figure 19. Power Supply Sequencing ............................................................................... ........................................... 24
Figure 20. Differential Transition Times ...................................................................................................................... 24
Figure 21. I2C Data Valid Delay (Driving Read Cycle Data) ...................................................................................... 24
Figure 22. INT Output Pin Response to HPD Input Change ........................................................................................ 24
Figure 23. 4:4:4 RGB 36-Bit Timing Diagram ............................................................................................................. 30
Figure 24. 4:4:4 YCbCr 36-Bit Timing Diagram .... .................................................................................................... 30
Figure 25. 4:4:4 RGB 30-Bit Timing Diagram ............................................................................................................. 30
Figure 26. 4:4:4 YCbCr 30-Bit Timing Diagram ................................. ....................................................................... 31
Figure 27. 4:4:4 RGB 24-Bit Timing Diagram ............................................................................................................. 31
Figure 28. Figure 24. 4:4:4 YCbCr 24-Bit Timing Diagram ........................................................................................ 31
Figure 29. YC 4:2:2 12-Bit per Pixel Timing Diagram ................................................................................................ 34
Figure 30. YC 4:2:2 10-Bit per Pixel Timing Diagram ................................................................................................ 34
Figure 31. YC 4:2:2 8-Bit per Pixel Timing Diagram ................................................................................................. 34
Figure 32. YC Mux 4:2:2 Timing Diagram ................................................................................................................. 36
Figure 33. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram ....................................................................... 38
Figure 34. 12-Bit Input DMO Timing Diagram ........................................................................................................... 39
Figure 35. Decoupling and Bypass Schematic ............................................................................................................. 40
Figure 36. Decoupling and Bypass Capacitor Placement ............................................................................................. 40
Figure 37. Transmitter to HDMI Connector Routing–Top View ................................................................................. 41
Figure 38. Power Supply Decoupling and PLL Filtering Schematic ............................................................................ 43
Figure 39. HDMI Port TMDS Connections Schematic ................................................................................................ 44
Figure 40. HDMI Port ESD Protection Schematic ....................................................................................................... 44
Figure 41. Controller Connections Schematic .............................................................................................................. 45
Figure 42. Package Diagram......................................................................................................................................... 46
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
List of Tables
Table 1. Summary of New Features ............................................................................................................................... 2
Table 2. Video Input mats Example ............................................................................................................................... 6
Table 3. Color Space versus Video mat .......................................................................................................................... 7
Table 4. YCbCr-to-RGB Color Space Conversion mula ................................................................................................ 7
Table 5. Supported 3D Video mats ................................................................................................................................. 8
Table 5. Supported MCLK Frequencies ......................................................................................................................... 9
Table 6. Channel Status Bits d Word Length............................................................................................................... 11
Table 7. Control of I2C Address with CI2CA Pin ........................................................................................................ 12
Table 9. Absolute Maximum Conditions ...................................................................................................................... 14
Table 10. Normal Operating Conditions ....................................................................................................................... 14
Table 11. Digital I/O Specifications ............................................................................................................................. 15
Table 12. TMDS DC Specifications— Source Termination On ................................................................................... 16
Table 13. TMDS DC Specifications— Source Termination Off ................................................................................. 16
Table 14. Power-Down Modes ..................................................................................................................................... 17
Table 15. Total Power Mode ........................................................................................................................................ 17
Table 16. Power Operating Modes
17
Table 17. TMDS AC Specifications ............................................................................................................................. 18
Table 18. S/PDIF Input Port Timings ........................................................................................................................... 18
Table 19. I2S Input Port Timings .................................................................................................................................. 18
Table 20. DSD Input Port Timings .......................................................................................... .................................... 19
Table 21. Video Input AC Specifications ..................................................................................................................... 19
Table 22. Control Signal Timing Specifications .......................................................................................................... 20
Table 23. Input Video mats........................................................................................................................................... 28
Table 24. 4:4:4 Mappings ............................................................................................................................................. 29
Table 25. YC 4:2:2 Separate Sync Pin Mappings ........... ............................................................................................. 32
Table 26. YC 4:2:2 Embedded Sync Pin Mappings ..................................................................................................... 33
Table 27. YC Mux 4:2:2 Mappings ............................................................. ................................................................ 35
Table 28. YC Mux 4:2:2 Embedded Sync Pin Mapping .............................................................................................. 37
Table 29. 12/15/18-Bit Input 4:4:4 Mappings .............................................................................................................. 39
Table 30. Referenced Documents ................................................................................................................................. 47
Table 31. Standards Groups Contact Inmation ............................................................................................................. 47
Table 32. Publications ......................................................................................................................................................... 47
vi
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
General Description
Digital Video Interface
The SiI9134 HDMI Deep Color Transmitter is a thirdgeneration High Definition Multimedia Interface
(HDMI®) transmitter that provides a simple method of
sending protected digital audio and video that
provides end rs with a truly all-digital experience.
A/V receivers, along with Blu-ray Disc™ and HD
DVD players and recorders, can provide high quality
digital audio and video over a simple, low cost cable.
The SiI9134 transmitter extends the
family of HDMI transmitters by supporting 30-bit
and 36-bit Deep Color video, and incorporates a
flexible audio and video interface. It is software and
pin-compatible with the SiI9034 transmitter.
Supports DVD and HD MPEG decoders
24-bit, 30-bit, and 36-bit RGB/YCbCr 4:4:4 (Deep Color)
16-bit, 20-bit, and 24-bit YCbCr 4:2:2
8-bit, 10-bit, and 12-bit YCbCr 4:2:2 (ITU.601 and
ITU.656)
12-bit, 15-bit and 18-bit dual-edge clocking input modes
YCbCr-to-RGB color space conversion
BTA-T1004 video input mat
Input clock divider or multiplier (input clock frequencies
of 0.5x, 2x, 4x).
Programmable Data Enable generator and sync
extraction.
The transmitter perms the 10- or12-bit to 8-bit
conversion of the 10/12-bit Deep Color video input
data by increasing the TMDS™ clock frequency and
packing the extra bits into the next byte. An
225 MHz to support Deep Color and 1080p
integrated color-space converter allows direct
connection to all major MPEG decoders, including
those that provide an ITU.656 output.
Pre-programmed High Bandwidth Content Protection
(HDCP) keys provide the highest level of key
security; which simplifies manufacturing and lowers
Digital Audio Interface
DTS HD and Dolby True HD high bit rate audio support
A dedicated 4-pin Direct Stream Digital (DSD) 8-channel
input provides Super Audio CD (SACD) and decoded
Dolby Digital applications
Four I2S inputs with flexible channel mapping support
High Bit-Rate audio and accept Dolby Digital and DVD-
cost.
Audio input (2-channel 192 kHz, 8-channel 192 kHz)
HDMI Output
S/PDIF input supports PCM, Dolby Digital, and DTS
Supports Deep Color and High-Bitrate Audio
digital audio transmission (32–192 kHz sample rate)
IEC60958 or IEC61937 compatible
Supports all the mandatory and several optional
3D mats described in the HDMI 1.4
Specification
s the latest generation of TMDS core
, which operates from 25 MHz to
2:1 and 4:1 down-sampling handles 96 kHz and 192 kHz
audio streams
Control Capability
resolution
Backward compatibility with the DVI
Specification allows HDMI systems to connect
to DVI displays.
Monitor Detection supported through Hot Plug and
Receiver Detection
Master I2C interface DDC connection simplifies board
layout and lowers cost.
HDCP encryption engine transmitting
protected audio and video content
Flexible power management.
Package
100-pin14 mm by 14 mm TQFP package
Figure 1. SiI9134 System Diagram
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
SiI9134 Transmitter Compared with SiI9030 and
SiI9034 Devices
Table 1 summarizes the differences among the SiI9030, the SiI9034, and the SiI9134 HDMI transmitters.
Table 1. Summary of New Features
Transmitter
Video Input
SiI9030
SiI9034
SiI9134
Digital Video Input Ports
I/O Voltage
Input Pixel Clock Multiply/Divide
Maximum Pixel Input Clock Rate
Maximum TMDS Output Clock
BTA-T1004 mat Support
Video mat Conversion
1
3.3 V
0.5x, 2x, 4x
150 MHz
150 MHz
Yes
1
3.3 V
0.5x, 2x, 4x
165 MHz
165 MHz
Yes
1
3.3 V
0.5x, 2x, 4x
165 MHz
225 MHz
Yes
36-Bit and 30-Bit Deep Color
YCbCr → RGB CSC
No
Yes
No
Yes
Yes
Yes
RGB → YCbCr CSC
4:2:2 → 4:4:4 Upsampling
4:4:4 → 4:2:2 Decimation
16-235 → 0-255 Expansion
0-255 → 16-235 Compression
16-235/240 Clipping
Audio Input
No
Yes
No
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
One-bit Audio (DSD/SACD)
No
S/PDIF Input Ports
I2S Input Bits
High Bit Rate Audio Support
Compressed DTS-HD and Dolby True-HD
2-Channel Maximum Sample Rate
8-Channel Maximum Sample Rate
Down Sampling
Yes
Yes
192 kHz to 48 kHz
192 kHz to 48 kHz
192 kHz to 48 kHz
1
4 (8-channel)
No
1
4 (8-channel)
No
1
4 (8-channel)
Yes
2
2
2
192 kHz on I S
96 kHz on S/PDIF
96 kHz
96 kHz to 48 kHz
192 kHz on I S
192 kHz on S/PDIF
192 kHz
96 kHz to 48 kHz
192 kHz on I S
192 kHz on S/PDIF
192 kHz
96 kHz to 48 kHz
CI2CA Pin
Yes
—
No
Software Register
80-pin TQFP ePad
CI2CA Pin
Yes
—
No
Software Register
100-pin TQFP
CI2CA Pin
Yes
—
Yes
Software Register
100-pin TQFP
2
I C Address Bus
Device Address Select
Master DDC Bus
Other
3D Support
HDCP Reset
Package
2
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Pin Diagram
Figure 2 shows the pin connections the SiI9134 transmitter in the 100-pin TQFP package. Individual pin functions
are described in the Pin Descriptions section beginning on page 25.
Figure 2. Pin Diagram
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Description
The SiI9134 transmitter provides a complete solution transmitting HDMI digital audio or video. Specialized audio and
video processing available within the transmitter adds HDMI capability to consumer electronics devices easily and cost
effectively. Figure 3 shows the functional blocks of the device. Pin descriptions begin on page 25.
Figure 3 Functional Block Diagram
4
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Video Data Input and Conversion
Video Processing Pipeline
Figure 4 shows the video data processing stages. Each of the processing blocks can be bypassed by setting the
appropriate register bits. The HSYNC and VSYNC input signals are required except in embedded sync modes. The DE
input signal is optional; the DE generator can create this signal using the HSYNC and VSYNC pulses.
Figure 4. Transmitter Video Data Processing Path
Input Clock Multiplier/Divider
The input pixel clock can be multiplied by 0.5, 1, 2, or 4. Video input mats that a 2x clock (such as YC Mux mode)
can then be transmitted across the HDMI link with a 1x clock; similarly with 1x to 2x, 1x to 4x and 2x to 4x.
Video Data Capture Logic
The video data capture logic receives uncompressed digital video through an 8-bit to-24 bit wide interface. The three
8/10/12-bit data channels of the interface can be configured 17 different video mats (see Table 2 on page 6 ). It
provides a direct connection to major A/V processors. Register settings configure the interface bus width, mat
(8/10/12/16/20/24-bit), and rising or falling edge latching. The appropriate registers must be configured to describe
which mat of video is being sent to the SiI9134 transmitter. This inmation travels over the HDMI link in CEA-861D
Active Video Inmation (AVI) packets. The transmitter also supports dual-edge clocking using 12 data pins.
Configuration to Support Deep-color
The SiI9134 transmitter provides support Deep Color video data up to the maximum specified link speed of
2.25 Gbps (225 MHz clock rate the Deep Color packetized data). It supports both 30-bit (10 -bits per pixel
component) and 36-bit (12-bits per pixel component) video input mats, and converts the data to 8-bit packets
encryption and TMDS encoding transferring across the TMDS link.
When the input data width is wider than desired, the device can be programmed to dither or truncate the video data to
the desired size. instance, if the input data width is 12 bits per pixel component, but the sink device supports 10 bits,
the transmitter can be programmed either to dither or to truncate the 12-bit input data to the desired 10-bit output data.
Dither processing is the final block in the video processing path and occurs after all other video processing has been
permed.
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
5
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Common Video Input mats
Table 2 lists the video input mats that the SiI9134 transmitter supports.
Table 2. Video Input mats Example
Data Enable Generator
Color
Space
Video
mat
RGB
4:4:4
YCbCr
4:4:4
Input
Bus
Channels Width1, 2
Input Pixel Clock (MHz)
HSYNC/
VSYNC4
480i5
3
3
3
1.5
36
30
24
12
Separate
Separate
Separate
Separate
27
27
27
27
VGA/4
80p
25/27
25/27
25/27
25/27
1.5
1.5
3
15
18
36
Separate
Separate
Separate
27
27
27
25/27
25/27
27
3
3
30
24
Separate
Separate
27
27
27
27
Separate
2754
XGA
720p
1080i
SXGA 1080p UXGA
—
—
65
65
74.25
74.25
74.25
74.25
74.25
74.25
74.25
74.25
108
108
108
—
148.5
148.5
148.5
—
—
—
162
—
—
—
—
3
65
65
—
74.25
74.25
74.25
74.25
74.25
74.25
—
—
—
—
—
148.5
—
—
—
3
3
—
—
—
—
148.5
74.25
74.25
Notes
148.5
—
—
—
—
74.25
74.25
—
—
148.5
148.5
—
—
—
—
1.5
1.5
1.5
4:2:2
12
15
18
16/20/24
Separate
Separate
Separate
Separate
27
27
27
27
27
25/27
25/27
27
—
65
65
—
74.25
74.25
74.25
74.25
74.25
74.25
74.25
74.25
—
—
—
—
—
—
—
148.5
—
—
—
—
3
3
3
—
8/10/12
Embedded
BTAT1004
27
—
27
54
—
—
74.25
—
74.25
—
—
—
148.5
—
—
—
4
4,6
2
Embedded
1
27
54
—
148.5
148.5
—
—
—
Notes:
1. Bus widths of 8, 10, or 12 bits one channel. Bus widths of 16, 20, or 24 bits with 4:2:2 data sequences two
data channels.
2. Latching edge is programmable.
3. These mats dual-edge clocking.
4. If embedded syncs are provided, then DE is generated ly from SAV/EAV sequences. Embedded syncs
656 SAV/EAV sequences of FF, 00, 00, XY.
The transmitter includes logic toconstruct a DE signal from the incoming HSYNC, VSYNC, and clock. Registers are
5. 480i must be input at 27 MHz using pixel replication to be transmitted across the HDMI link.
6. BTA-T1004 mat is defined a single-channel (8/10/12-bit) bus with encoded syncs.
Embedded Sync Decoding
The SiI9134 transmitter can create DE, HSYNC, and VSYNC signals from the Start of Active Video (SAV) and End
of Active Video (EAV) codes within the 656 video stream. HDCP is not supported in this mode.
programmed to enable the DE signal to define the size of the active display region. This feature is ful when
interfacing to MPEG decoders that do not provide a specific DE output signal.
Re-sampling
Re-sampling (up-sampling/decimation) blocks allow conversion of 4:4:4 data to 4:2:2 and of 4:2:2 data to 4:4:4
transmission over the HDMI link.
6
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SiI-DS-0193-F
4
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Color Space Converters (CSC)
Two color space converters (CSCs) (YCbCr to RGB and RGB to YCbCr) are available to interface to the many video
mats supplied by A/V processors and to provide full DVI backward compatibility. The CSC can be adjusted to perm
standard-definition conversions (ITU.601) or high-definition conversions (ITU.709) by setting the appropriate
registers.
RGB to YCbCr The RGB→YCbCr color space converter can convert from video data RGB to standard definition or to
high definition YCbCr mats. The HDMI AVI packet defines the color space of the incoming video.
Table 3. Color Space versus Video mat
Video mat
Conversion
640 x 480
480i
ITU-R BT.601
ITU-R BT.601
576i
480p
576p
240p
288p
720p
1080i
1080p
ITU-R BT.601
ITU-R BT.601
ITU-R BT.601
ITU-R BT.601
ITU-R BT.601
ITU-R BT.709
ITU-R BT.709
ITU-R BT.709
mulas
CE Mode 16-235 RGB
Y = 0.299R′ + 0.587G′ + 0.114B′
Cb = –0.172R′ – 0.339G′ + 0.511B′ + 128
Cr = 0.511R′ – 0.428G′ – 0.083B′ + 128
G′ = Y – 0.459(Cr – 128) – 0.18 3(Cb – 128)
Y = 0.213R′ + 0.715G′ + 0.072B′
Cb = –0.117R′ – 0.394G′ + 0.511B′ + 128
Cr = 0.511R′ – 0.464G′ – 0.047B′ + 128
YCbCr to RGB The YCbCr→RGB color space converter allows MPEG decoders to interface with RGB- inputs.
The CSC can convert from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB. Refer to the
detailed mulas in Table 4. Note the difference between RGB range CE modes and PC modes.
Table 4. YCbCr-to-RGB Color Space Conversion mula
mat change
Conversion
YCbCr 16-235 Input2,
3to
6011
RGB 16-235 Output2, 3
7091
YCbCr Input Color Range 2, 3
R′ = Y + 1.371(Cr – 128)
G′ = Y– 0.698(Cr – 128) – 0.336(Cb – 128)
B′ = Y + 1.732(Cb – 128)
R′ = Y + 1.540(Cr – 128)
Notes:
YCbCr 16-235 Input2, 3
to
RGB 0-255 Output2, 3
601
709
1.
2.
3.
B′ = Y + 1.816(Cb – 128)
R′ = 1.164((Y-16) + 1.371(Cr – 128))
G′ = 1.164((Y-16) – 0.698(Cr – 128) – 0.336(Cb – 128))
B′ = 1.164((Y-16) + 1.732(Cb – 128))
R′ = 1.164((Y-16) + 1.540(Cr – 128))
G′ = 1.164((Y-16) – 0.459(Cr – 128) – 0.183(Cb – 128))
B′ = 1.164((Y-16) + 1.816(Cb – 128))
No clipping can be
10-bit deepby 4.
12-bit deepby 16.done.color,alloccurrencesofthevalues16,128,235,and255shouldbemultipliedcolor,alloccurrencesofthevalues16,128,235,and255shouldbemultiplied
14-to-8/10/12-Dither
The 14-to-8/10/12-dither block dithers ly processed, 14-bit data to 8, 10, or 12 bits output on the HDMI link. It can be
bypassed to output 10/12-bit modes when supplied by the A/V processor or converted in the decimator and CSC.
Color Range Scaling
The SiI9134 transmitter can scale the input color range from limited-range into full-range or vice versa through the
range expansion and compression blocks. When enabled by itself, the range expansion block expands 16–235 (64–943
to 256–3775 30/36-bit color depth) limited-range data into 0–255 (0–1023 to 0–4095 30/36-bit color depth) full-
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
7
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
range data each video channel. When range expansion and the YCbCr to RGB converter are both enabled, the input
conversion range Cb and Cr channels is 16–240 (64–963 to 256–3855 30/36-bit color depth). Similarly, the range
compression block compresses 0–255/0–1023/0–4095 full-range data into 16–235/64–943/256–3775 limited-range data
each video channel when enabled by itself. When enabled with the RGB to YCbCr converter, this block compresses to
16–240/64–963/256–3855 the Cb and Cr channels. The color range scaling is linear.
Clipping
The clipping block, when enabled, clips the values of the output video to 16–235 RGB video or the Y channel, and
to 16–240 the Cb and Cr channels.
HDCP Encryption Engine/XOR Mask
The HDCP encryption engine contains the logic necessary to encrypt the incoming audio and video data and includes support HDCP
authentication and repeater checks. The system microcontroller or microprocessor controls the encryption process by using a set sequence of
register reads and writes. An algorithm s HDCP keys and a Key Selector Value (KSV) stored in the on-board ROM to calculate a number that is
then applied to an XOR mask. This process encrypts the audio and video data on a pixel-by-pixel basis during each clock cycle.
3D Video mats
TMDS Digital Core
The TMDS digital core perms 8-to- 10-bit TMDS encoding on the data received from the HDCP XOR mask. This data is
sent to three TMDS differential data lines, along with a TMDS differential clock line. A resistor tied to the
EXT_SWING pin controls the TMDS swing amplitude.
The SiI9134 transmitter supports the 3D video modes described in the HDMI Specification. All modes support RGB
prevented as it may resultin visible artifacts.
4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color mats and 8-, 10-, and 12-bit data-width per color component. External
separate HSYNC, VSYNC, and DE signals can be supplied, or these signals can be supplied as embedded EAV/SAV
Furthermore, a frame rate of 24 Hz also means that a framerateof 23.98 Hz is supported and a frame rate of 60 Hz also
means a frame rate of 59.94 Hz is supported. Input pixel clock changes accordingly.
sequences in the video stream. Table 5 shows the maximum possible resolution with a given frame rate; example, Side- bySide (Half) mode is defined 1080p60, which implies that 720p60 and 480p60 are also supported.
When using Side-by-Side mat, the of 4:2:2 to 4:4:4: up - sampling and 4:4:4 to 4:2:2 down-sampling should be
Video processing should be bypassed in the case of L + depth mat.
Transmission of the HDMI Vendor Specific InfoFrame, which carries 3D inmation to the receiver, is supported by the
SiI9134 device.
Table 5. Supported 3D Video mats
3D mat
Extended
Definition
Resolution
Frame
Rate (Hz)
—
1080p
24
Input Pixel Clock
(MHz)
Frame Packing
interlaced
L + depth
—
full
Side-by-Side
half
Top-and-Bottom
8
—
720p
50/60
1080i
1080p
50/60
24
720p
50/60
1080p
24
720p
50/60
1080p
50/60
1080i
50/60
1080p
24
720p
50/60
© 2009-2010 , Inc. All rights reserved.
148.5
74.25
74.25
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
3D Video Limitations
Frame Packing mat: Frame packing mat requires Vact_space, which must have constant video data. Dithering
should be disabled when transmitting the frame packing mat.
In the case of 1080p 24 Hz mat, this video mat has a total of 2295 lines. However, the VRES counter
(0x72. 0x3C,0x3D) of the SiI9134 device has 11 bits, which means a maximum of 2047 lines. In this case, the
VRES counter overflows and shows a value of 0.
The DE generator is supported except the 1080p 24 Hz mat. The DE_LIN register (0x72.0x38,0x39) has 11 bits
(maximum 2047), but the 1080p 24 Hz mat requires 2205 lines.
Side-by-Side mat: L frame and R frame are concatenated without a border. Since 4:4:4 to 4:2:2 down-sampling and
4:2:2 dithering and upsampling to 4:4:4 has a decimation filter which looks at adjacent pixels, those features should not
be d to avoid visible artifacts.
L + Depth mat: Any video processing should be bypassed.
Top-and-Bottom mat: There are no limitations.
Audio Data Capture Logic
The SiI9134 transmitter accepts digital audio over an S/PDIF interface, four I 2S inputs, or eight one-bit audio inputs.
S/PDIF
The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream multiS/PDIF have been created from the same clock source. This step usually s the original MCLK to strobe out the
channel (IEC 61937) mats. The audio data capture logic ms the audio data into packets described in the HDMI Specification. The S/PDIF input supports audio sampling (Fs) rates from 32 to 192 kHz. A separate master clock input (MCLK), coherent with the S/PDIF input, is required time-stamping purposes. Coherent means that the MCLK and
S/PDIF from the sourcing chip. There is no setup or hold timing requirement on an input with respect to MCLK.
I2 S
Four I2S inputs allow transmission of DVD-Audio or decoded Dolby Digital to A/V receivers and high-end displays.
The interface supports up to 8-channels at 192 kHz. The I2S pins must also be coherent with MCLK.
Register control allows the audio data to be downsampled by one-half or one-fourth. This control allows the transmitter
to share the audio bus with a high-sample-rate audio DAC, while downsampling audio an attached display that
supports lower rates. Conversions from 192 to 48 kHz, from 176.4 to 44.1 kHz, from 96 to 48 kHz, and from 88.2
to 44.1 kHz are supported. Audio data can be downsampled on 2-channel audio.
The appropriate registers must be configured to describe the audio mat provided to the SiI9134 transmitter. This
inmation is passed over the HDMI link in the CEA-861D Audio Info (AI) packets.
Table 5 shows the MCLK frequencies that support the seven audio sample rates.
128
4.096 MHz
5.645 MHz6.144 MHz11.290 MHz
12.288 MHz
22.579 MHz
24.576 MHz
176.4 kHz
192 kHz
33.868 MHz
45.158 MHz
67.737 MHz
—
—
—
—
36.864 MHz
49.152 MHz
73.728 MHz
—
—
—
—
Table 5. Supported MCLK Frequencies
Multiple of Fs
192
256
384
512
768
1024
1152
32 kHz
44.1 kHz
6.144 MHz
8.192 MHz
12.288 MHz
16.384 MHz
24.576 MHz
32.768 MHz
36.864 MHz
8. 467 MHz
11.290 MHz
16.934 MHz
22.579 MHz
33.869 MHz
45.158 MHz
50.803 MHz
I2S and S/PDIF Supported MCLK Rates
Audio Sample Rate, Fs
48 kHz
88.2 kHz
96 kHz
9.216 MHz
12.288 MHz
18.432 MHz
24.576 MHz
36.864 MHz
49.152 MHz
55.296 MHz
16.934 MHz
22.579 MHz
33.864 MHz
45.158 MHz
67.738 MHz
—
—
18.432 MHz
24.576 MHz
36.864 MHz
49.152 MHz
73.728 MHz
—
—
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
9
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
One-Bit Audio Input (DSD/SACD)
Direct Stream Digital (DSD) is an audio data mat defined Super Audio CD (SACD) applications. A clock and four data
inputs, each left and right channels, provide support up to 8 channels. One-bit audio sources provide MCLK and support
64 Fs, with Fs being either 44.1 kHz or 88.2 kHz.
The one-bit audio inputs are sampled on the positive edge of the DSD clock, assembled into 56-bit packets, and mapped
to the appropriate FIFO. The Audio InfoFrame, instead of the Channel Status bits, carries the sampling inmation onebit audio.
High-Bit Rate Audio on HDMI
The new high-bit-rate compression standards, such as MLP and DTS-HD, transmit data at bit rates as high as 18 or
24 Mbps. Beca these bit rates are so high, DVD decoders and HDMI transmitters (as source devices), and DSP and
HDMI receivers (as sink devices) must carry the data using four I 2S lines rather than using a single very-high-speed
S/PDIF interface or I2S bus (see Figure 5 on the next page).
MPEG
Tx
Rx
DSP
Figure 5. HighSpeed Data Transmission
The high-bit-rate audio stream is originally encoded as a single stream. To send the stream over four I2S lines, the DVD
decoder splits it into four streams. Figure 6 shows the high-bit-rate stream bee it has been split into four I2S lines.
Figure 7 shows the same audio stream after being split. Each sample requires 16 cycles of the I2S clock (SCK).
Figure 6. High Bitrate Stream Bee and after Reassembly and Splitting
Figure 7. High Bit Rate Stream After Splitting
10
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Audio Downsampler Limitations
The SiI9134 transmitter has an audio downsampler function that can down sample the incoming two-channel audio data
and output the result over the HDMI link. The audio data can be downsampled by one-half or one-fourth with register
control. Conversions from 192 to 48 kHz, 176.4 to 44.1 kHz, 96 to 48 kHz, and 88.2 to 44.1 kHz are supported. Some
limitations in the audio sample word length when using this feature may need special consideration in a real application.
When enabling the audio downsampler, the Channel Status registers the audio sample word lengths sent over the
HDMI link always indicate the maximum possible length. example, if the input S/PDIF stream was in 20-bit mode
with 16 bits valid, after enabling the downsampler the Channel Status indicates 20-bit mode with 20 bits valid.
Audio sample word length is carried in bits 33 through 35 of the Channel Status register over the HDMI link, as shown
in Table 6. These bits are always set to 0b101 when enabling the down-sampler feature. Audio data is not affected beca
0s are placed into the LSBs of the data, and the wider word length is sent across the HDMI link.
Table 6. Channel Status Bits d Word Length
Bit
1
0
1
Audio sample word
length
1. M aximum audio s ample
34
0
0
1
0
33
0
1
0
0
32
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
1
1
0
0
1
1
1
Notes:
Sample word
length, bits
Note
length (MAXLEN) is 20its if MAXLEN = 0, 24 bits if MAXLEN = 1.
word
35
0
0
0
1
202, 4
0
Max.
word
length1
Not indicated
16
18
19
17
Not indicated
20
22
23
24
21
—
2
2
2
2
3
3
3
3
3, 4
3
2. Maximum audio sample word length is 20.
3. Maximum audio sample word length is 24.
4. Bits [35:33] are always 0b101 when the down-sampler is enabled
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
11
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
HDCP Key ROM
The SiI9134 transmitter comes pre-programmed with a set of production HDCP keys stored in an ROM. System
manufacturers do not need to purchase key sets from the Digital-Content Protection LLC. handles all purchasing,
programming, and security the HDCP keys. The pre- programmed HDCP keys provide the highest level of security
beca there is no way to read the keys once the devices are programmed. Customers must sign the HDCP license
agreement (www.digital-cp.com) or be under a specific NDA with bee receiving samples of the transmitter.
Interrupt Out
The INT pin provides an interrupt signal to the system microcontroller when any of the following occur:
Monitor Detect (HPD input) changes
VSYNC (ful synchronizing a microcontroller to the vertical timing interval)
0xFF on each page in the I2C protocol. Beca thereare more than 255 bytes of registers in the transmitter, it is
Error in the audio mat
DDC FIFO status change
The Register/Configuration Logicblock incorporates all the registers required configuring and managing the SiI9134
HDCP authentication error
Control and Configuration
All functions of the transmitter are monitored and controlled with I 2C registers. Register addresses range from 0x00 to
transmitter. These registers are d to perm HDCP authentication, audio/video mat processing, CEA-861D info-packet
matting, and power-down control.
accessed using one of two I2C device addresses, which can be altered with the CI2CA pin. The level on the CI2CA pin is
2
not latched ly and theree must not be changed during any active I C operations.
Table 7. Control of I2C Address with CI2CA Pin
Device Address
First Device Address
Second Device Address
CI2CA = HIGH
0x76
0x7E
Registers/Configuration Logic
CI2CA = LOW
0x72
0x7A
Microcontroller Slave I2C Interface
The controller slave I2C interface on the transmitter (pins CSCL and CSDA) is capable of running up to 400 kHz. This
bus is d to configure the transmitter by reading and writing to various registers and is 5 V tolerant. Figure 8 shows the
host I2C ports.
Figure 8. Simplified I2C Ports
DDC Master I2C Interface
The transmitter includes two I2C ports: a master port to connect directly to the HDMI cable and a port to connect to the
system microcontroller or processor. Both are shown in Figure 8. DDC reads and writes are executed by reading and
writing registers in the SiI9134 transmitter.
12
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
, Inc.
SiI9134 HDMI Deep Color Transmitter
Data Sheet
The master DDC block supports I2C transactions specified by VESA Enhanced Display Data Channel Standard (Section
3.1.2), and it supports an I2C write transaction needed HDCP. The Master DDC block complies with the Standard
Mode timing of the I2C specification (100 kHz) and supports slave clock stretching as required by E-DDC. Section 8.4.1
of the HDMI Specification limits the speed allowed on the DDC bus to 100 kHz.
Figure 8 provides inmation about the transactions supported by the master I2C interface.
Figure 8. Master I2C Supported Transactions
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
13
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Electrical Specifications
The following tables provide electrical specifications the SiI9134 transmitter.
Absolute Maximum Conditions
Table 9. Absolute Maximum Conditions
Symbol
IOVCC33
Parameter
I/O pin supply voltage 3.3 V
Min
–0.3
Typ
—
Max
4.0
Units
V
Note
3
PVCC1
PVCC2
AVCC18
AVCC33
CVCC18
TMDS PLL supply voltage
TMDS PLL supply voltage
TMDS analog supply voltage
TMDS analog supply voltage 3.3 V
Digital Core supply voltage
2
DDC I C I/O reference voltage
–0.3
–0.3
–0.3
–0.3
–0.3
—
—
—
—
—
2.5
2.5
2.5
4.0
2.5
V
V
V
V
V
—
—
—
3
3
–0.3
—
5.5
V
—
Input voltage
Output voltage
–0.3
–0.3
—
—
5.5
IOVCC33 + 0.3
V
V
—
—
TA
Ambient temperature (with power applied)
–25
—
105
C
—
TJ
Junction temperature (with power applied)
—
—
125
C
—
Storage temperature
–65
—
150
C
—
DDCPWR5V
VI
VO
TSTG
Notes:
1. Permanent device damage can occur if absolute maximum conditions are exceeded.
2.973.33.63V1
IOVCC33I/O pin supply voltage 3.3 V
2. Restrict functional operation to the conditions described in the Normal Operating Conditions section below.
3. Voltage undershoot or overshoot cannot exceed absolute maximum conditions.
4.
Refer to the SiI9134 HDMI Deep Color Transmitter Qualification Report inmation on ESD permance.
Normal Operating Conditions
Table 10. Normal Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
Note
Θjc
PVCC1
PVCC2
AVCC18
AVCC33
CVCC18
Junction thermal resistance(Theta JC)
TMDS PLL supply voltage
TMDS PLL supply voltage
TMDS analog supply voltage 1.8 V
TMDS analog supply voltage 3.3 V
Digital core supply voltage
2
DDC I C I/O reference voltage
—
1.62
1.62
1.62
2.97
1.62
—
1.8
1.8
1.8
3.3
1.8
17.5
1.98
1.98
1.98
3.63
1.98
C/W
V
V
V
V
V
—
2
2
—
5
—
4.50
5.0
5.50
V
4
DDCPWR5V
DIFF3318
Θja
A
T
–1.0
(VCC33–VCC18)
Ambient temperatu re (with p ower applied )
Ambient thermal resistance (Theta JA)
—
2.0
V
3, 4
0
25
70
C
—
—
—
55
C/W
6
Notes:
1.
2.
3.
4.
5.
6.
7.
14
Power to IOVCC33 and AVCC33 pins should be controlled from one source.
Power to PVCC1 and PVCC2 pins should be regulated.
Applies to all 3.3 V and 1.8 V power supplies. Power supply sequencing must guarantee that power pins stay within
these limits of each other. See Figure 19.
No power sequencing is required on other supply voltages.
The HDMI Specification requires termination voltage to be controlled to 3.3 V ±5%. The SiI9134 HDMI Deep
Color Transmitter tolerates a wider range of ±300 mV.
Airflow at 0 m/s.
See page 42 schematics showing decoupling and power supply regulation.
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
DC Specifications
Digital I/O Specifications
Under normal operating conditions, unless otherwise specified.
Table 11. Digital I/O Specifications
Symbol
VIH
VIL
VOH
VOL
LVTTL
LVTTL
LVTTL
LVTTL
Min
2.0
—
2.4
—
Typ
—
—
—
—
Max
—
0.825
—
0.4
Units
V
V
V
V
Notes
1
1
1
1
LVTTL
VOUT = 2.4 V
6.2
12.4
19
mA
2, 7, 8
Output minimum sink current
LOW to HIGH threshold, local
2
I C bus
HIGH to LOW threshold, local
2
I C bus
LOW to HIGH threshold, DDC
2
I C Bus
HIGH to LOW threshold, DDC
LVTTL
VOUT = 0.4 V
4.5
6.6
7.6
mA
2, 7, 8
Schmitt
—
1.9
—
—
V
1, 4
Schmitt
—
—
—
0.7
V
1, 4
Schmitt
—
2.3
—
—
V
1
VTH-I2D
I C bus
Schmitt
—
—
—
1.5
V
1
VCINL
VCIPL
Input clamp voltage
Input clamp voltage
All
All
ICL = –18 mA
ICL = 18 mA
—
—
—
—
GND – 0.8
VCC + 0.8
V
V
1, 5
1, 5
Input leakage Current
All
High impedance
–10
—
10
μA
1, 6
IOL
VTH+I2L
VTH-I2L
VTH+I2D
2
IIL
Notes:
1.
2.
3.
4.
Pin Type3
Conditions
—
—
—
—
IOH
Parameter
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Output minimum source DC
current
Guaranteed by characterization.
Guaranteed by design.
LVTTL inputs except CI2CA have no pull-up or pull-down resistors. All und input pins should be tied
LOW.
When no VCC is applied to the chip, the CSCL and CSDA pins can continue to draw a small current and prevent
2
2
the I C masterfrom communicating2with other deviceson the I C bus. Theree, do not remove VCC from the
transmitter unless the attached I
5.
C bus is completely idle.
Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions a pulse of
greater than 3 ns or more than one third of the clock cycle, whichever is less. Exceeding the Clamp Current I CL
listed can result in permanent damage to the chip.
6. Limits defined by HDMI Specification.
7. Output drive specification applies to INT, DSCL, DSDA, and CSDA pins.
8. Minimum output drive specified at ambient = 70 °C and IOVCC = 3.0 V. Typical drive specified at ambient = 25 °C
and IOVCC = 3.3 V. Maximum output drive specified at ambient = 0 °C and IOVCC = 3.6 V.
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
15
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
TMDS I/O Specifications
Table 12. TMDS DC Specifications— Source Termination On
source termination and leakage bias (STERM and LVBIAS in TMDS Control Register #1 bits 0 and 2 respectively)
are turned on in the chip. External source termination components must be removed. LVBIAS should be set to 1 after
reset.
Symbol Parameter
VDOH
VDOL
VOD
VODD
IDOS
Notes:
1.
2.
3.
Differential HIGH level output
voltage
Differential LOW level output
voltage
Differential Outputs single
ended swing amplitude
Differential Outputs differential
swing amplitude
Differential output short circuit
Pin
Type
Conditions
TMDS
—
TMDS
—
TMDS
Min
Typ
Max
Units
Notes
AVCC33
– 150
AVCC33
– 600
AVCC33
– 130
AVCC33
–110
AVCC33
– 400
mV
1
mV
1
REXT_SWING
= 698 Ω 1%
REXT SWING
400
450
600
mV
1, 3
TMDS
= 698 Ω 1%
800
900
1200
mV
1, 3
TMDS
VOUT = 0 V
—
—
5
μA
2
AVCC33
– 600– 500– 400
voltage
current
Guaranteed by characterization.
Guaranteed by design.
Minimum output drive specified at ambient = 70 °C and IOVCC = 3.0 V. Typical drive specified at ambient = 25 °C
Pin
and IOVCC = 3.3 V. Maximum output drive specified at ambient = 0 °C and IOVCC = 3.6 V.
Table 13. TMDS DC Specifications— Source Termination Off
source termination and leakage bias (STERM and LVBIAS in TMDS Control Register #1 bits 0 and 2 respectively)
are turned off in the chip. External source termination components are required and the chip must be set
accordingly upon power up.
Symbol
Parameter
VDOH
Differential HIGH level output
voltage
Differential LOW level output
VDOL
3.
Type
TMDS
TMDS
Conditions
—
—
Min
Typ
Max
Units
AVCC33
– 10
AVCC33
AVCC33
AVCC33
+ 10
AVCC33
mV
1
mV
1
AVCC33
Notes
Minimum output drive specifiedat ambient = 70 °C and IOVCC = 3.0 V. Typical drive specified at ambient = 25 °C
VOD
VODD
IDOS
Notes:
Differential Outputs single
ended swing amplitude
Differential Outputs differential
swing amplitude
Differential output short circuit
current
TMDS
TMDS
TMDS
= 850 Ω 1%
REXT SWING
= 850 Ω 1%
VOUT = 0 V
400
800
500
1000
600
1200
mV
mV
1, 3
1, 3
—
—
5
μA
2
1.
2.
Guaranteed by characterization.
and IOVCC = 3.3 V. Maximum output drive specified at ambient = 0 °C and IOVCC = 3.6 V.
Guaranteed by design.
16
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
DC Power Supply Pin Specifications
Table 14. Power-Down Modes
Symbol
Parameter
IPDQ3
IPDQ
IPD
Notes:
Mode
Frequency
Complete power-down current
A
Quiet power-down current
Power-down current @ 225 MHz
B
C
Maximum3
Units
Notes
1.8 V
3.3 V
No input
1
5
mA
1, 2
clock
Clocking
8
30
5
5
mA
mA
1
1
1. Power is not related to input pixel clock (IDCK) frequency.
2. Most registers are accessible with no input pixel clock. Exceptions include Packet Control and ROM test. Stopping
the input pixel clock (IDCK) is equivalent to setting PDIDCK# = 0 to minimize power.
3. Maximum power limits measured with all supplies at maximum normal operating conditions, minimum normal
operating ambient temperature, and a single pixel checkerboard pattern.
Table 15. Total Power Mode
Typical1
valuesare specified full functional mode,not power-down modes.
3. Typical
Symbol
Parameter
ISTBY
Notes:
Mode
Standby current
D
Frequency
27 MHz
74.25 MHz
1.8 V
—
—
3.3 V
—
—
1.8 V
20
44
3.3 V
5
5
Units
mA
mA
E
150 MHz
225 MHz
27 MHz
150 MHz
—
—
87
221
—
—
5
5
77
94
102
230
5
5
5
5
mA
mA
mA
mA
—
—
225 MHz
251
5
276
5
mA
—
Trans mitter s upp ly
ICCT
1.
2.
Maximum2
74.25 M Hz
current
146
5
168
5
mA
Notes
3
—
Typical power specifications measured with supplies at typical normal operating conditions and an SMPTE133
video pattern.
Maximum power limits measured with all supplies at maximum normal operating conditions, minimum normal
operating ambient temperature, and a single pixel checkerboard pattern.
Table 16. Power Operating Modes
clock trees
Bit States
Mode
PDTOT#
1
1
PD#
0
0
Input
Switchin
PDIDCK# PDOSC
g
0
1
No
0
0
No
A
B
Complete Power Down
Quiet Power Down
C
Power Down
1
0
0
D
Standby
1
0
1
0
0
Yes
Yes
Description
Comment
Minimum power.
Master DDC available.
Upstream chip still
Lowest power mode.
Access DDC bus
while minimizing
active.
transmit power.
active.
Power-reset mode.
E
Full Power
SiI-DS-0193-F
1
1
1
0
Yes
© 2009-2010 , Inc. All rights reserved.
Full-function.
Functional mode.
17
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
AC Specifications
TMDS AC Timing Specifications
Under normal operating conditions, unless otherwise specified.
Table 17. TMDS AC Specifications
Symbol
TDDF
TDDR
THDE
TLDE
SLHT
Parameter
VSYNC and HSYNC Delay from DE falling
edge
VSYNC and HSYNC Delay to DE rising edge
DE HIGH Time
DE LOW Time
Min
Typ
Max
Units
Figure
—
1
—
—
TCIP
Figure 12
—
1
—
138
—
—
—
—
8191
—
TCIP
TCIP
TCIP
Figure 12
Figure 13
Figure 13
75
—
144
ps
Figure 20
75
—
144
ps
Figure 20
—
3
Differential Swing LOW-to-HIGH Transition
4
Time
SHLT
3
Conditions
3
Differential Swing HIGH-to-LOW Transition
4
REXT_SWING = 698 Ω
Source
Termination On
Time
3
Notes:
1. Guaranteed by design.
2. Guaranteed by characterization.
3. TLDE (DE LOW Time) minimum is defined HDMI mode carrying 480p video with 192 kHz audio, which
requires at least 138 pixel clocks of blanking to carry the audio packets. If HDCP is running, minimum DE
LOW time is 58 clocks (according to the HDCP Specification). If both HDCP and audio are not running, minimum
DE LOW time is 12 clocks TMDS. moredetails, refer to Figure 13 on page 22. Minimum vertical blanking
time is 3 horizontal line times.
4. Limits are defined by the HDMI Specification.
Audio AC Timing Specifications
Table 18. S/PDIF Input Port Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
FS_SPDIF
TSPCYC
Sample Rate
1
SPDIF Cycle Time
2 Channel
CL = 10 pF
32
—
—
—
192
1.0
kHz
UI
—
Figure 15
TSPDUTY
1
SPDIF Duty Cycle
CL = 10 pF
90%
—
110%
UI
Figure 15
TMCLKCYC
FMCLK
TMCLKDUTY
TAUDDLY
3
MCLK Cycle Time
3
MCLK Frequency
3
MCLK Duty Cycle
Audio Pipeline Delay
4
CL = 10 pF
CL = 10 pF
CL = 10 pF
13.3
—
—
—
—
75
ns
MHz
Figure 15
Figure 15
40%
—
60%
TMCLKCYC
Figure 15
—
—
30
70
μs
—
Conditions
—
Min
32
Typ
—
Max
192
Units
kHz
Figure
—
CL = 10 pF
—
—
1.0
UI
Figure 16
—
—
—
110%
—
—
UI
ns
ns
Figure 16
Figure 16
Figure 16
Table 19. I2S Input Port Timings
Symbol
FS_I2S
Parameter
Sample Rate
TSCKCYC
I S Cycle Time
TSCKDUTY
TI2SSU
TI2SHD
I S Duty Cycle
1
2
3
1
2
CL = 10 pF
3
2
I S Setup Time
2
3
2
I S Hold Time
3
2
CL = 10 pF
CL = 10 pF
90%
15
0
SiI-DS-0193-F
18
© 2009-2010 , Inc. All rights reserved.
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Table 20. DSD Input Port Timings
Symbol
Parameter
FS_DSD
Sample Rate
TDCKCYC
TDCKDUTY
TDSDSU
TDSDHD
Notes:
Conditions
Min
Typ
Max
Units
Figure
—
—
44.1
88.2
kHz
—
CL = 10 pF
—
—
1.0
UI
Figure 17
CL = 10 pF
90%
20
20
—
—
—
110%
—
—
UI
ns
ns
Figure 17
Figure 17
Figure 17
1
DSD Cycle Time
DSD Duty Cycle
DSD Setup Time
DSD Hold Time
1
3
CL = 10 pF
CL = 10 pF
1. Proportional to unit time (UI) according to sample rate. Refer to the I 2S or S/PDIF Specifications.
2. Setup and hold minima are based on 13.388 MHz sampling, which is adapted from Fig. 3 of Philips I2S
Specification.
3. A separate master clock input (MCLK) is required; refer to the S/PDIF section on page 9.
4. Audio pipeline delay is measured from the transmitter input pins to TMDS output. The video path delay is
insignificant.
Single-edge
THIDF
0.8——nsFigure 10
Video AC Timing Specifications
Under normal operating conditions, unless otherwise specified.
Table 21. Video Input AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Note
TCIP
—
6.1
—
40
ns
Figure 9
1
—
25
—
165
MHz
Figure 9
2
TCIP12
FCIP12
IDCK period, one pixel per clock
IDCK frequency, one pixel per
clock
IDCK period, dual-edge clock
IDCK frequency, dual-edge clock
—
—
12.3
25
—
—
40
82.5
ns
MHz
Figure 11
Figure 11
2
2
TDUTY
TIJIT
IDCK duty cycle
Worst case IDCK clock jitter
—
—
40%
—
—
—
60%
1.0
TCIP
ns
Figure 9
Figure 9
—
3, 4
1.0
—
—
ns
Figure 10
1.0
—
—
ns
Figure 10
0.5
—
—
ns
Figure 10
1.0
—
—
ns
Figure 11
1.0
—
—
ns
Figure 11
FCIP
TSIDF
2. TCIP12
TSIDR
THIDR
TSIDD
THIDD
Setup time to IDCK falling edge
(EDGE = 0)
Hold time to IDCK falling edge
(EDGE = 0)
and FCIP12 apply in dual-edgemode. TCIP12 is not a controlling specification.
Setup time to IDCK rising edge
(EDGE = 1)
Hold time to IDCK rising edge
(EDGE = 1)
Setup time to IDCK rising or
falling edge
Hold time to IDCK rising or falling
edge
clocking mode
12-bit dual-edge
clocking mode
5
6
Notes:
1. TCIP and FCIP apply in single-edge clocking modes. TCIP is the inverse of FCIP and is not a controlling specification.
3. Input clock jitter is estimated by triggering a digital scope at the rising edge of input clock and measuring the peakto-peak time spread of the rising edge of the input clock one microsecond after the trigger.
4. Actual jitter tolerance can be higher depending on the frequency of the jitter.
5. Setup and hold time specifications apply to Data, DE, VSYNC, and HSYNC input pins, relative to IDCK input
clock.
6. Setup and hold limits are not affected by EDGE bit setting 12/15/18-bit, dual-edge clocking mode.
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
19
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Control Timing Specifications
Under normal operating conditions, unless otherwise specified.
Table 22. Control Signal Timing Specifications
Symbol
TRESET
TI2CDVD
THDDAT
THDSTA
TINT
FSCL
Parameter
RESET# signal LOW time required
reset
SDA Data Valid Delay from SCL falling
edge on READ command
2
I C data hold time
2
I C Hold time (repeated) START
condition
Response time INT output pin from
change in input condition (HPD,
Conditions
Min
Typ
—
50
—
CL = 400pF
—
—
0–400 kHz
7.0
0–400 kHz
Max
Units
Figure
Note
µs
Figure 14
1, 5
700
ns
Figure 21
2
—
—
ns
—
3
–7.0
—
—
ns
—
—
—
—
100
µs
Figure 22
40
70
100
kHz
—
RESET# =
Receiver Sense, VSYNC change, etc.).
HIGH
Frequency on master DDC SCL signal
—
2
Notes:
1. Reset on RESET# pin can be LOW as the supply becomes stable, or pulled LOW at least TRESET.
2. All standard-mode (100 kHz) I2C timing requirements are guaranteed by design. These timings apply to the slave
I2C port (pins CSDA and CSCL) and to the master I2C port (pins DSDA and DSCL).
3. This minimum hold time is required by CSCL and CSDA pins as an I2C slave. The device does not include the
300 ns delay required by the I2C Specification (Version 2.1, Table 5, note 2).
4. The master DDC block provides an SCL signal the E-DDC bus. The HDMI Specification limits this to I C
Standard Mode or 100 kHz. of the Master DDC block does not require an active IDCK.
5. Not a Schmitt trigger.
—
—
20
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Timing Diagrams
Input Timing Diagrams
T
CIP
50%
50%
T
50%
DUTY
Figure 9. IDCK Clock Cycle/HIGH/LOW Times
T
EDGE=1
IDCK
T
D[35:0], DE,
HSYNC,VSYNC
50 %
T
HIDR
SIDR
50 %
50 %
no change allowed
IDCK
EDGE=0
CIP
50 %
50 %
T
SIDF
50 %
T
HIDF
D[35:0], DE,
HSYNC,VSYNC
50 %
no change allowed
Signals may change in the unshaded portion of the wavem, to meet both the
minimum setup and minimum hold time specifications.
50 %
Figure 10. Control and Data Single-Edge Setup/Hold Times to IDCK
Figure 11. Dual-Edge Setup/Hold Times to IDCK
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
21
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Figure 12. VSYNC and HSYNC Delay Times from/to DE
T
DE
2.0 V
HDE
2.0 V
0.8 V
T
0.8 V
LDE
Figure 13. DE HIGH/LOW Times
VCCmax
VCC
min
VCC
RESET#
RESET#
TRESET
Note: VCC must be stable between its limits Normal Operating Conditions TRESET bee RESET# is HIGH.
RESET# must be pulled LOW TRESET bee accessing registers. This can be done by holding RESET# LOW until TRESET after
stable power (as shown to the left above) or by pulling RESET# LOW from a HIGH state (as shown to the right) at
least TRESET.
Figure 14. RESET# Minimum Timings
22
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Audio Timing Diagrams
Figure 15. S/PDIF Input Timings
Figure 16. I2S Input Timings
Figure 17. DSD Input Timings
Figure 18. MCLK Timings
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
23
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Power Supply Sequencing
Figure 19. Power Supply Sequencing
Output Timing Diagrams
Figure 20. Differential Transition Times
2
Figure 21. I C Data Valid Delay (Driving Read Cycle Data)
Figure 22. INT Output Pin Response to HPD Input Change
24
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Pin Descriptions
The following tables provide pin descriptions the SiI9134 transmitter
Video Input Pins
Pin Name
D0
D1
Pin
98
97
Type
LVTTL
LVTTL
Dir
Input
Input
D2
D3
D4
D5
D6
D7
D8
96
95
94
93
92
91
90
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Input
Input
Input
Input
Input
Input
Input
D23
71
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
86
85
84
83
82
81
80
79
78
77
75
74
73
72
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
D24
D25
D26
D27
D28
D29
D30
D31
D33
D34
70
69
68
67
63
62
61
60
58
57
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
D32
59
LVT TL
LVT TL
Input
Description
These are the lower 12 bits of the 36-bit pixel bus. These pins are highly
configurable, and support multiple RGB and YCbCr mats. Refer to Data Bus
Mappings on page 27 complete inmation.
These are the middle 12 bits of the 36-bit pixel bus.
These are the upper 12 bits of the 36-bit pixel bus.
D35
IDCK
DE
HSYNC
VSYNC
SiI-DS-0193-F
56
88
1
2
3
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Input
Input
Input
Input
Input
Input data clock
Data enable
Horizontal sync input control signal
Vertical sync input control signal
© 2009-2010 , Inc. All rights reserved.
25
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Audio Input Pins
Pin Name
SCK
WS
SD0
SD1
SD2
SD3
DL0
DR0
DL1
Pin
11
10
9
8
7
6
17
16
19
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Dir
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
2
I S serial clock
2
I S Word Select
2
I S serial data
2
I S serial data
2
I S serial data
2
I S serial data
One-bit audio data left 0
One-bit audio data right 0
One-bit audio data left 1
DR1
DL2
DR2
18
21
20
LVTTL
LVTTL
LVTTL
Input
Input
Input
One-bit audio data right 1
One-bit audio data left 2
One-bit audio data right 2
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Input
Input
Input
Input
Input
One-bit audio data left 3
One-bit audio data right 3
One-bit audio clock input
Audio input master clock
S/PDIF audio input
Control Pins
DL3
DR3
DCLK
MCLK
SPDIF
23
22
15
5
4
Configuration/Programming Pins
Pin Name
HPD
RSVDL
INT
Pin
51
52
24
Type
LVTTL
LVTTL
LVTTL
Dir
Input
Input
Output
Pin Name
Pin
Open drain
Type
Output
Dir
CI2CA
RESET#
50
25
LVTTL
LVTTL
Schmidt
Input
Input
CSCL
48
Schmitt
Input
CSDA
49
Schmitt
Open drain
Schmitt
Schmitt
Input
Output
Input
Input
DSCL
46
Open drain
DSDA
47
Description
Hot Plug Detect input
Reserved by and must be tied LOW.
Interrupt output
Description
2
I C device address select (see page 12)
Reset pin (active LOW)
5 V tolerant
2
I C Clock
2
I C Data (open drain output.)
DDC Clock (open drain output)
Output
DDC Data (open drain output.)
The DSCL pin is bi-directional. The transmitter monitors the state of DSCL so that it can accommodate I 2C clock
stretching by the slave device. The level on the CI2CA pin is not latched ly and must not be changed during any active
I2C operations.
26
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Differential Signal Data Pins
Pin Name
TX0+
TX0TX1+
TX1TX2+
TX2-
Pin
34
33
37
36
40
39
Type
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Dir
Output
Output
Output
Output
Output
Output
Description
TMDS output data pairs.
—
—
—
—
—
TXC+
TXC-
31
30
TMDS
TMDS
Output
Output
TMDS output clock pair.
—
Voltage Swing Adjust. A resistor is tied from this pin to AVCC18. This resistor
EXT_SWING
27
Analog
Input
determines the amplitude of the voltage swing. recommends a
value of 698 Ω 1%.
Power and Ground Pins
Pin Name
CVCC18
Pin
12, 55, 64, 76, 99
Type
Power
Description
Digital Core VCC.
IOVCC33
AVCC33
AVCC18
14, 53, 66, 89
44
32, 38,
Power
Power
Power
IO Pin VCC.
Analog VCC.
Analog VCC.
3.3 V
3.3 V
1.8 V
AGND
26, 29, 35, 41,43
Ground
Analog GND.
Ground
PVCC1
PVCC2
28
42
Power
Power
DDCPWR5V
GND
45
13, 54, 65, 87,100
Power
Ground
TMDS Core PLL Power.
Filter PLL Power.
Power reference signal. Supplies power to the DDC
2
I C pads when chip is powered off.
Digital ground
Supply
1.8 V
1.8 V
1.8 V
5V
Ground
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
27
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Data Bus Mappings
The SiI9134 transmitter supports multiple input data mappings. Some have explicit control signals, and some have
embedded control signals. The selection of data mapping mode should be consistent at the pins and in the corresponding
register settings.
Table 23. Input Video mats
Input Mode
Data
Widths
Clock Mode
Syncs
Page
Notes
RGB 4:4:4
24, 30, 36
1x
Explicit
28
3, 6
YCbCr 4:4:4
24, 30, 36
1x
Explicit
28
1, 3, 6
YC 4:2:2
16, 20, 24
1x
Explicit
—
2, 1
YC 4:2:2
16, 20, 24
1x
Embedded
31
2, 1
YC Mux 4:2:2
16, 20, 24
1x
Explicit
—
—
YC Mux 4:2:2
16, 20, 24
1x
Embedded
—
—
RGB 4:4:4
12, 15, 18
dual-edge
Explicit
38
8
every HDMI source to transmitan accurate AVI InfoFrame. Even in therare cases where an AVI is not absolutely
transmitting audio.In addition, the HDMI Specification andthe EIA/CEA-861D Specification require virtually
YCbCr 4:4:4
12, 15, 18
dual-edge
Explicit
38
1, 8
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
4:4:4 data contains one Cr, one Cb, and one Y value every pixel.
4:2:2 data contains one Cr and one Cb value every two pixels, and one Y value every pixel.
these mats can be carried across the HDMI link. Refer to the HDMI Specification, Section 6.2.3. The link
clock must be within the specified range of the HDMI receiver.
In YC MUX mode data is input on one 8/10/12-bit channel. A 2x clock is required.
extracted sync timings to CEA-861D compliant timings.
Embedded sync decoding extracts the syncs. A 2x clock is required. The DE generator may be needed to convert
A 2x clock can also be sent with 4:4:4 data. This is necessary the receiver to remat such a stream into 4:2:2
data or into a multiplexed YC MUX output mat.
When sending a 2x clock the HDMI source must also send AVI InfoFrames with an accurate pixel replication field.
Refer to the HDMI Specification, Section 6.4.
Dual-edge clocking is allowed these video mappings.
The HDMI Specification requires that every HDMI source transmit an accurate Audio InfoFrame whenever it is
required, strongly recommends transmitting an AVI during every vertical blanking interval.
28
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
RGB and YCbCr 4:4:4 mats with Separate Syncs
The pixel clock runs at the pixel rate and a complete definition of each pixel is input on each clock. The same timing
mat is d YCbCr 4:4:4.
Table 24. 4:4:4 Mappings
Pin
Name
D0
D1
D2
D3
D4
D5
24-bit
RGB
GND
GND
GND
GND
B0
B1
24-bit
YCbCr
GND
GND
GND
GND
Cb0
Cb1
30-bit
RGB
GND
GND
B0
B1
B2
B3
30-bit
YCbCr
GND
GND
Cb0
Cb1
Cb2
Cb3
36-bit
RGB
B0
B1
B2
B3
B4
B5
36-bit
YCbCr
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
D6
D7
B2
B3
Cb2
Cb3
B4
B5
Cb4
Cb5
B6
B7
Cb6
Cb7
D23
G7
D8
D9
D10
D11
D12
D13
B4
B5
B6
B7
GND
GND
Cb4
Cb5
Cb6
Cb7
GND
GND
B6
B7
B8
B9
GND
GND
Cb6
Cb7
Cb8
Cb9
GND
GND
B8
B9
B10
B11
G0
G1
Cb8
Cb9
Cb10
Cb11
Y0
Y1
D14
D15
D16
D17
D18
D19
GND
GND
G0
G1
G2
G3
GND
GND
Y0
Y1
Y2
Y3
G0
G1
G2
G3
G4
G5
Y0
Y1
Y2
Y3
Y4
Y5
G2
G3
G4
G5
G6
G7
Y2
Y3
Y4
Y5
Y6
Y7
D21
D22
G5
G6
Y5
Y6
G7
G8
Y7
Y8
G9
G10
Y9
Y10
D33
D24
D25
D26
D27
D28
D29
D30
D32
R5
GND
GND
GND
GND
R0
R1
R2
R4
Cr5
GND
GND
GND
GND
Cr0
Cr1
Cr2
Cr4
GND
GND
R0
R1
R2
R3
R4
R6
R9
R0
R1
R2
R3
R4
R5
R6
R8
Cr9
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr8
D34
R6
Cr6
R8
Cr8
R10
Cr10
D35
HSYNC
VSYNC
DE
R7
HSYNC
VSYNC
DE
Cr7
HSYNC
VSYNC
DE
Cr9
HSYNC
VSYNC
DE
R11
HSYNC
VSYNC
DE
Cr11
HSYNC
VSYNC
DE
D20
D31
G4
R3
Y7
Y4
Cr3
G9Y9
G6
R5
R9
HSYNC
VSYNC
DE
Y6
R7Cr7
GND
GND
Cr0
Cr1
Cr2
Cr3
Cr4
Cr6
Cr5
G11Y11
G8
R7
Y8
Cr7
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
29
SiI9134 HDMI Deep Color Transmitter
Data Sheet
Figure 23. 4:4:4 RGB 36-Bit Timing Diagram
Figure 24. 4:4:4 YCbCr 36 -Bit Timing Diagram
Figure 25. 4:4:4 RGB 30-Bit Timing Diagram
, Inc.
30
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Figure 26. 4:4:4 YCbCr 30-Bit Timing Diagram
Figure 27. 4:4:4 RGB 24-Bit Timing Diagram
Figure 28. Figure 24. 4:4:4 YCbCr 24-Bit Timing Diagram
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
31
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
YC 4:2:2 mats with Separate Syncs
The YC 4:2:2 mats input one pixel every pixel clock period. A luma (Y) value is input every pixel, but the chroma
values (Cb and Cr) change every second pixel. Pixel data can be 16-bit, 20-bit or 24- bit. HSYNC and VSYNC are
input explicitly on their own pins. The DE high time must contain an even number of pixel clocks.
Table 25. YC 4:2:2 Separate Sync Pin Mappings
Pin Name
D0
D1
D2
D3
D4
16-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y0
Y1
GND
GND
GND
D22
Y6
D8
D9
D10
D17
D11
D12
GND
GND
GND
Y1
GND
GND
GND
GND
GND
Y1
GND
GND
GND
GND
Cb0
Y3
Cb1
GND
GND
GND
Cr0
Y3
Cr1
GND
Cb0
Cb1
Cb2
Y5
Cb3
GND
Cr0
Cr1
Cr2
Y5
Cr3
GND
Y1
Y2
Y3
D13
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D16
Y0
Y0
Y2
Y2
Y4
Y4
D18
D19
D20
D21
Y2
Y3
Y4
Y5
Y2
Y3
Y4
Y5
Y4
Y5
Y6
Y7
Y4
Y5
Y6
Y7
Y6
Y7
Y8
Y9
Y6
Y7
Y8
Y9
D23
D24
D25
Y7
GND
GND
Y7
GND
GND
Y9
GND
GND
Y9
GND
GND
Y11
GND
GND
Y11
GND
GND
ConY6fidentialY8Y8Y10
Silico n
GND
GND
Y0
Y1
24-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
Y0
Y0
D5
D6
D7
D14
GND
GND
GND
20-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y1
Y2
Y3
Y10
GND
GND
GND
D26
D27
D28
D29
D31
D32
D33
D34
GND
GND
Cb0
Cb1
Cb3
Cb4
Cb5
Cb6
GND
GND
Cr0
Cr1
Cr3
Cr4
Cr5
Cr6
GND
GND
Cb2
Cb3
Cb5
Cb6
Cb7
Cb8
GND
GND
Cr2
Cr3
Cr5
Cr6
Cr7
Cr8
GND
GND
Cb4
Cb5
Cb7
Cb8
Cb9
Cb10
GND
GND
Cr4
Cr5
Cr7
Cr8
Cr9
Cr10
D35
HSYNC
VSYNC
DE
Cb7
HSYNC
VSYNC
DE
Cr7
HSYNC
VSYNC
DE
Cb9
HSYNC
VSYNC
DE
Cr9
HSYNC
VSYNC
DE
Cb11
HSYNC
VSYNC
DE
Cr11
HSYNC
VSYNC
DE
D30
32
Cb2
Cr2
Cb4
Cr4
Cb6
© 2009-2010 , Inc. All rights reserved.
Cr6
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
YC 4:2:2 mats with Embedded Sync
Table 26. YC 4:2:2 Embedded Sync Pin Mappings
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
16-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D8
D9
GND
GND
D25
GND
GND
GND
20-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y0
Y0
Y1
Y1
GND
GND
GND
GND
24-bit YC
Pixel #0
Pixel #1
GND
GND
GND
GND
GND
GND
GND
GND
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Cb0
Cb1
Cr0
Cr1
GNDGNDGND
GNDGND
D10
D11
D12
D13
D14
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Cb0
Cb1
GND
GND
GND
GND
Cr0
Cr1
GND
GND
GND
GND
Cb2
Cb3
GND
GND
GND
GND
D16
D17
D18
D19
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
Y2
Y3
Y4
Y5
Y2
Y3
Y4
Y5
Y4
Y5
Y6
Y7
Y4
Y5
Y6
Y7
D21
Y5
Y5
Y7
Y7
Y9
Y9
D23
D24
Y7
GND
Y7
GND
Y9
GND
Y9
GND
Y11
GND
Y11
GND
D35
D26
D27
D28
D29
D30
D31
D32
D34
Cb7
GND
GND
Cb0
Cb1
Cb2
Cb3
Cb4
Cb6
Cr7
GND
GND
Cr0
Cr1
Cr2
Cr3
Cr4
Cr6
GND
GND
Cb2
Cb3
Cb4
Cb5
Cb6
Cb8
Cb9Cr9
GND
GND
Cr2
Cr3
Cr4
Cr5
Cr6
Cr8
Cb11
GND
GND
Cb4
Cb5
Cb6
Cb7
Cb8
Cb10
Cr11
GND
GND
Cr4
Cr5
Cr6
Cr7
Cr8
Cr10
HSYNC
VSYNC
DE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D20
D22
D33
Y4
Y6
Cb5
Y4
Y6
Cr5
Y6
Y8
Cb7
Y6
Cr7
Y8
Y8
Y10
Cb9
Cr2
Cr3
GND
GND
GND
GND
Y8
Y10
Cr9
GND
GND
GND
SiI-DS-0193-F
© 2009-2010 , Inc. All rights reserved.
33
SiI9134 HDMI Deep Color Transmitter
Data Sheet
Figure 29. YC 4:2:2 12-Bit per Pixel Timing Diagram
Figure 30. YC 4:2:2 10-Bit per Pixel Timing Diagram
Figure 31. YC 4:2:2 8-Bit per Pixel Timing Diagram
Note: The val data is defined in various specifications to specific values.
, Inc.
34
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
YC Mux 4:2:2 mats with Separate Syncs
The video data is multiplexed onto fewer pins than the mapping in Table 25, but a luma (Y) is provided each pixel, and
either a Cb or a Cr value each pixel, since the clock rate is doubled. Figure 32 shows the 12-bit mode. The 10-and 8bit mappings fewer input pins the pixel data. Note the explicit syncs.
Table 27. YC Mux 4:2:2 Mappings
Pin Name
D0
D1
D2
D3
D4
1st Clk
GND
GND
GND
GND
GND
D5
D6
D7
GND
GND
GND
8-bit
2nd Clk
GND
GND
GND
GND
GND
GND
GND
GND
1st Clk
GND
GND
GND
GND
GND
GND
C0
C1
10-bit
2nd Clk
GND
GND
GND
GND
GND
GND
Y0
Y1
12-bit
1st Clk
GND
GND
GND
GND
C0
2nd Clk
GND
GND
GND
GND
Y0
C1
C2
C3
Y1
Y2
Y3
ntialY8C10
ConfideY6C8
D22
C6
D8
D9
D10
D17
D11
D12
GND
GND
GND
C1
GND
GND
GND
GND
GND
Y1
GND
GND
GND
GND
GND
C3
GND
GND
GND
GND
GND
Y3
GND
GND
GND
GND
GND
C5
GND
GND
GND
GND
GND
Y5
GND
GND
D13
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D16
C0
Y0
C2
Y2
C4
Y4
D18
D19
D20
D21
C2
C3
C4
C5
Y2
Y3
Y4
Y5
C4
C5
C6
C7
Y4
Y5
Y6
Y7
C6
C7
C8
C9
Y6
Y7
Y8
Y9
D23
D24
D25
C7
GND
GND
Y7
GND
GND
C9
GND
GND
Y9
GND
GND
C11
GND
GND
D14
Silico n
GND
GND
Y10
GND
GND
GND
GND
Y11
GND
GND
D26
D27
D28
D29
D31
D32
D33
D34
GND
GND
GND
GND
GND
GND
GND
GND
D35
HSYNC
VSYNC
DE
GND
D30
SiI-DS-0193-F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HSYNC
VSYNC
DE
GND
HSYNC
VSYNC
DE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HSYNC
VSYNC
DE
© 2009-2010 , Inc. All rights reserved.
35
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Figure 32. YC Mux 4:2:2 Timing Diagram
Note: The val data is defined in various specifications to specific values.
36
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
YC Mux 4:2:2 Embedded Sync mats
This mode is similar to the one on page 34, but with embedded syncs. It is similar to SMTPE 293 in embedding the
syncs, but also multiplexes the luma (Y) and chroma (Cb and Cr) onto the same pins on alternating pixel clock cycles.
Normally this mode is d 480i, 480p, 576i, and 576p modes. Input clock rate is twice the pixel clock rate. SAV code is
shown bee rise of DE. EAV follows fall of DE. 480p 54 MHz input can be achieved if the input clock is 54 MHz.
Table 28. YC Mux 4:2:2 Embedded Sync Pin Mapping
Pin Name
8-bit
D0
D1
D2
1st Clk
GND
GND
GND
2nd Clk
GND
GND
GND
1st Clk
GND
GND
GND
D3
D4
D5
GND
GND
GND
GND
GND
GND
GND
GND
GND
10-bit
2nd Clk
GND
GND
GND
1st Clk
GND
GND
GND
12-bit
2nd Clk
GND
GND
GND
GND
GND
GND
GND
C0
C1
GND
Y0
Y1
ntial
Te chnology
Silico n
D6
D7
D8
D9
GND
GND
GND
GND
GND
GND
GND
GND
C0
C1
GND
GND
Y0
Y1
GND
GND
C2
C3
GND
GND
Y2
Y3
GND
GND
D10
D11
D13
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D14
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D16
D17
D18
D19
D20
C0
C1
C2
C3
C4
Y0
Y1
Y2
Y3
Y4
C2
C3
C4
C5
C6
C4
C5
C6
C7
C8
Y4
Y5
Y6
Y7
Y8
D21
D22
D23
D24
D25
D26
D27
D28
C5
C6
C7
GND
GND
GND
GND
GND
Y5
Y6
Y7
GND
GND
GND
GND
GND
C7
C8
C9
GND
GND
GND
GND
GND
Y7
Y8
Y9
GND
GND
GND
GND
GND
C9
C10
C11
GND
GND
GND
GND
GND
Y9
Y10
Y11
GND
GND
GND
GND
GND
D30
D31
D32
D33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D12
D29
GND
GND
GND
GNDGND
GND
GND
Y2
Y3
Y4
Y5
Y6
GND
GND
GND
GND
GND
D34
GND
D35
HSYNC
VSYNC
DE
GND
SiI-DS-0193-F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
© 2009-2010 , Inc. All rights reserved.
GND
GND
GND
GND
GND
37
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Figure 33. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram
Note: The val data is defined in various specifications to specific values. The DE generator may be needed to convert extracted sync timings to CEA-861D timings. See
the ITU-R BT656 Specification.
38
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
12/15/18-Bit DMO RGB and YCbCr mats
The pixel clock runs at the pixel rate and a complete definition of each pixel is input on each clock. One clock edge
latches in half the pixel data on 12, 15, or 18 pins (depending on the input data width). The opposite clock edge latches
in the remaining half of the pixel data on the same 12, 15, or 18 pins. Figure 34 shows RGB data. The same timing mat
is d YCbCr 4:4:4, as listed in Table 24. Control signals (DE, HSYNC, and VSYNC) must change state to meet the
setup and hold times with respect to the first edge of IDCK. Figure 34 shows IDCK latching input data when the EDGE
bit is set to 1. DE, VSYNC, and HSYNC must change state while meeting the setup and hold times specified 12-bit,
dual-edge mode. Refer to page 18 more details.
Table 29. 12/15/18-Bit Input 4:4:4 Mappings
D0
24-bit
RGB
YCbCr
First
Second
First
Second
Edge
Edge
Edge
Edge
GND
GND
GND
GND
30-bit
RGB
YCbCr
First
Second
First
Second
Edge
Edge
Edge
Edge
GND
GND
GND
GND
D1
D2
GND
GND
Pin
Name
D17
G1
D3
D4
D5
D6
GND
B0
B1
B2
D7
D8
D9
D10
B3
B4
B5
B6
GND
GND
R5Y1
GND
G4
G5
G6
G7
R0
R1
R2
GND
GND
GND
GND
GND
B0
GND
Cb0
Cb1
Cb2
Cr5
GND
Y4
Y5
Y6
G3
B1
B2
B3
B4
Cb3
Cb4
Cb5
Cb6
Y7
Cr0
Cr1
Cr2
B5
B6
B7
B8
GND
G5
TecR8
GND
Cb0
GND
Y5
36-bit
RGB
YCbCr
First
Second
First
Second
Edge
Edge
Edge
Edge
B0
G6
Cb0
Y6
B1
B2
G7
G8
Cb1
Cb2
Y7
Y8
hnologyY3Cr8G5
R11
Y5
Cr11
G6
G7
G8
G9
Cb1
Cb2
Cb3
Cb4
Y6
Y7
Y8
Y9
B3
B4
B5
B6
G9
G10
G11
R0
Cb3
Cb4
Cb5
Cb6
Y9
Y10
Y11
Cr0
R0
R1
R2
R3
Cb5
Cb6
Cb7
Cb8
Cr0
Cr1
Cr2
Cr3
B7
B8
B9
B10
R1
R2
R3
R4
Cb7
Cb8
Cb9
Cb10
Cr1
Cr2
Cr3
Cr4
f or
D11
D12
B7
GND
R3
GND
Cb7
GND
Cr3
GND
B9
GND
R4
GND
Cb9
GND
Cr4
GND
B11
G0
R5
R6
Cb11
Y0
Cr5
Cr6
D13
D14
D15
D16
GND
GND
GND
G0
GND
GND
GND
R4
GND
GND
GND
Y0
GND
GND
GND
Cr4
GND
G0
G1
G2
GND
R5
R6
R7
GND
Y0
Y1
Y2
GND
Cr5
Cr6
Cr7
G1
G2
G3
G4
R7
R8
R9
R10
Y1
Y2
Y3
Y4
Cr7
Cr8
Cr9
Cr10
D18
D19
G2
G3
R6
R7
Y2
Y3
Cr6
Cr7
G4
GND
R9
GND
Y4
GND
Cr9
GND
GND
GND
GND
GND
GND
GND
GND
GND
HSYNC HSYNC HSYNC HSYNC HSYNC
VSYNC VSYNC VSYNC VSYNC VSYNC
DE
DE
DE
DE
DE
HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC
VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
Figure 34. 12-Bit Input DMO Timing Diagram
SiI-DS-0193-F
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Design Guidelines
Power Supplies
Voltage Ripple Regulation
Excessive noise on PVCC1 or PVCC2 can ca improper PLL operation as it tries to stay locked on the incoming video
clock. Make sure to keep PVCC1 and PVCC2 noise below the maximum allowable value of 100 mV. If the ripple on
PVCC1 or PVCC21 is higher than 100 mV, recommends that a separate power source be d to supply these pins. A
voltage regulator that can supply 50 mA is sufficient PVCC1 and PVCC2. Refer to the schematic on page 42.
Decoupling
Designers should include decoupling and bypass capacitors at each power pin in the layout. These capacitors are shown
schematically in Figure 35. Place them as close as possible to the SiI9134 device pins, and avoid routing through vias if
possible, as shown in Figure 36, which represents the various types of power pins on the transmitter.
Note: Figure 36 shows the decoupling and bypass capacitor placement the TQFP package.
Figure 35. Decoupling and Bypass Schematic
VCC
C1
C2
L1
VCC
GND
Ferrite
C3
Via to GND
Figure 36. Decoupling and Bypass Capacitor Placement
Pins in each of the groups AVCC33, AVCC18, CVCC18, and IOVCC33 can share C2, C3, and L1, with each pin
having a separate C1 placed as close to the pin as possible.
40
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
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High-Speed TMDS Signals
ESD Protection
The transmitter chip can withstand electrostatic discharge to 2kV HBM. In applications where higher protection levels
are required, ESD-limiting components can be placed on the differential lines coming out of the chip. These components
typically have a capacitive effect, reducing the signal quality at higher clock frequencies on the link. the lowest
capacitance devices possible. In no case should the capacitance value exceed 5 pF.
Transmitter Layout Guidelines
The layout guidelines below help to ensure signal integrity, and encourages the board designer to follow them if
possible. An example of routing is shown in Figure 37.
Place the output connector that carries the TMDS signals as close as possible to the chip.
Route the differential lines as directly as possible from the connector to the device.
Route the two traces of each differential pair together.
Minimize the number of vias through which the signal lines are routed.
Lay out the two traces of each differential pair with a controlled differential impedance of 100 Ω.
Beca HDMI transmitters are tolerant of skews between differential pairs, spiral skew compensation
path length differences is not required.
Figure 37. Transmitter to HDMI Connector Routing–Top View
Protection I2C Port
Both the local (CSCL/CSDA) and master DDC (DSCL/DSDA) I2C pins on the transmitter chip are 5 V tolerant, although the
CSCL and CSDA pins are typically tied to 3.3 V. When no VCC is applied to the chip, the CSCL and CSDA pins can
continue to draw a small current and prevent the 1 2C master from communicating with other devices on the I2C bus. Theree,
do not remove VCC unless the local I2C bus is completely idle. The same requirement does not
SiI-DS-0193-F
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
apply to the DSCL and DSDA pins, which have true open- drain connections that enter a high-impedance state when the chip
is powered off, as long as the 5 volt reference voltage signal these I/Os, DDCPWR5V, continues to be supplied.
Hot Plug Signal Conditioning
The HDMI interface provides a hot plug signal back to the host side from the display. This signal is generated by
routing a 5 V source from the host through the cable to the display, and back. The specification defines the minimum
HIGH level the hot plug as 2.0 volts at the connector pin. The HPD pin is 5 V tolerant and can be directly connected to
the SiI9134 transmitter. However, an external pull-down resistor of 47 kΩ is required to guarantee that this CMOS
input is not floating, as shown in Figure 39 on page 43.
HDMI Design Considerations
HDMI CTS Test ID 7-4: TMDS Differential Rise and Fall Time
The HDMI CTS requires that the differential rise and fall time of the TMDS signals be > 75 ps, with all measurements
taken at the highest supported TMDS clock frequency. The HDMI CTS Specification lists three different oscilloscopes
that can be d to measure this parameter.
SiI9134 transmitter passes with rise and fall times greater than 75 ps. However, when using the Agilent DSO80000B
Tektronix TDS7404 (can bedupto148.5MHz.) Tektronix DPO70804 (no frequency limitation)
Agilent DSO80000B (no frequency limitation)
The Tektronix TDS7404scopeisthesamescope listed in the previous HDMI 1.2 CTS. When this scope is d, the adding a discrete capacitor
of approximately 1 pF from the signal to ground can also solve this compliance issue. The
scope, has found the rise and fall time of the transmitter can be faster than 75 ps. The difference is due to the higher
bandwidth of the Agilent DSO80000B, giving a more accurate measurement. has done no testing with Tektronix
DPO70804.
Recommendation to pass Test ID 7-4
Adding common components, such as common-mode filters and ESD suppression devices, increase the capacitance
slightly, slowing down the rise and fall time to well within the specification. If these devices are not in your design,
following external components have been tested on the CP9034/9134 reference design and proven to
comply with the HDMI CTS Specification:
Common Mode Filter: TDK ACM2012H
ESD Suppression Diode: Semtech Rclamp 0514M. Calinia Micro Devices (CMD) also makes a similar device
Components with similar characteristics can also be d.
Electromagnetic interference is a functionofboardlayout,shielding,receiver component operating voltage, frequency of operation, and
other factors. When attempting to control emissions, it is important not to place any passive components on the differential signal
lines other than any essential ESD protection, as described earlier. The differential signaling d in HDMI is inherently low in EMI, as
long as the routing recommendations noted in the Transmitter Layout Guidelines section on page 40 are followed.
which has not tested but from which we expect similar compliance permance.
EMI Considerations
The PCB ground plane should extend unbroken under as much of the transmitter chip and associated circuitry as
possible, with all ground pins of the chip using a common ground.
42
© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
Typical Circuit
Representative circuits applications of the SiI9134 transmitter chip are shown in Figure 38 through Figure 41. a
detailed review of your intended circuit implementation, contact your representative.
Power Supply Decoupling
Figure 38. Power Supply Decoupling and PLL Filtering Schematic
The ferrites shown in Figure 38 should have an impedance of 10 Ω or more in the frequency range 1–2 MHz.
SiI-DS-0193-F
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
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HDMI Port TMDS Connections
Figure 39. HDMI Port TMDS Connections Schematic
The transmitter is on the left in Figure 39. The specific value R EXT SWING is specified on page 16.
Figure 40. HDMI Port ESD Protection Schematic
44
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SiI-DS-0193-F
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
Control Signal Connections
Figure 41. Controller Connections Schematic
SiI-DS-0193-F
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
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Packaging
100-pin TQFP Package Dimensions and Marking Specification
Body thickness
1.00
1.05
Description
typ
—
—
max
1.20
0.15
JEDEC Package Code MS-026-AED
Item
A
A1
Thickness
Stand-off
A2
D1
E1
F1
Body size
14.00
Body size
14.00
Footprint
16.00
—
—
—
G1
L1
Footprint
Lead length
16.00
1.00
—
—
L
Foot length
0.60
0.75
b
Lead width
0.22
0.27
c
Lead thickness
—
0.20
e
Lead pitch
0.50
—
Legend
LLLLLL.LLLL
Package: SiI9134CTU
Description
Lot number
YY
Yearof manufacture
WW
TTTTTT
Week of manufacture
Trace code
M
Maturity code
= 0: engineering samples
= 1: pre-production
> 1: production
Figure 42. Package Diagram
Ordering Inmation
Production Part Numbers:
—
46
Device
Standard
© 2009-2010 , Inc. All rights reserved.
Part Number
SiI9134CTU
SiI-DS-0193-F
SiI9134 HDMI Deep Color Transmitter
Data Sheet
, Inc.
References
Standards Documents
Table 30 lists the abbreviations d in this document. Contact the responsible standards groups listed in Table 31 more
inmation on these specifications.
Table 30. Referenced Documents
Abbreviation
HDMI
HCTS
HDCP
E-EDID
E-DID IG
CEA-861-D
EDDC
Standards Publication, Organization, and Date
High Definition Multimedia Interface, Revision 1.4, HDMI Consortium, June 2009
HDMI Compliance Test Specification, Revision 1.3a, HDMI Consortium, November 2006
High-bandwidth Digital Content Protection, Revision 1.3, Digital Content Protection, LLC, December 2006
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA, Feb. 2000
VESA EDID Implementation Guide, VESA, June 2001
A DTV Profile Uncompressed High Speed Digital Interfaces, EIA/CEA, July 2006
Enhanced Display Data Channel Standard, Version 1.1, VESA, March 2004
Table 31. Standards Groups Contact Inmation
Standards Group
ANSI/EIA/CEA
VESA
HDCP
Web URL
http://global.ihs.com
http://www.vesa.org
http://www.digital-cp.com
e-mail
global@ihs.com
—
info@digital-cp.com
Phone
800-854-7179
408-957-9270
—
DVI
HDMI
http://www.ddwg.org
http://www.hdmi.org
ddwg.if@intel.com
admin@hdmi.org
—
—
Documents
Table 32 lists documents that are available from your sales representative.
Table 32. Publications
Document
SiI-PR-0039
SiI-DS-0193-F
Title
SiI9034/9134 HDMI Transmitter Programmer’s Reference
© 2009-2010 , Inc. All rights reserved.
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SiI9134 HDMI Deep Color Transmitter
Data Sheet
48
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© 2009-2010 , Inc. All rights reserved.
SiI-DS-0193-F
, Inc.
SiI9134 HDMI Deep Color Transmitter
Data Sheet
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from of, the materials are accurate, reliable, complete, up-to-date, or produce specific outcomes. , Inc. and its
affiliates assume no liability or responsibility any errors or omissions in these materials, makes no commitment or
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WITHOUT LIMITATION any loss of profits arising out of your access to, or interpretation of, or actions taken or not
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, Inc. and its affiliates reserve the right, without notice, to periodically modify the inmation in these materials, and
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