TR-SDI-PHY-E3-U1

Tri-Rate Serial Digital Interface Physical Layer IP Core User’s Guide December 2011 IPUG82_01.5 Table of Contents Chapter 1. Introduction .......................................................................................................................... 5 Quick Facts ........................................................................................................................................................... 6 Features ................................................................................................................................................................ 6 Video Interface and Source Format Support......................................................................................................... 6 Chapter 2. Functional Description ........................................................................................................ 8 Receiver ................................................................................................................................................................ 8 Decoder/Descrambler .................................................................................................................................. 9 Word Alignment/TRS Detection ................................................................................................................... 9 Rate Detection and Control.......................................................................................................................... 9 Format Detection........................................................................................................................................ 10 CRC Checker ............................................................................................................................................. 10 XYZ Word Decoder .................................................................................................................................... 10 LN Decoder ................................................................................................................................................ 10 VPID Extraction.......................................................................................................................................... 11 Transmitter .......................................................................................................................................................... 11 LN Encoder ................................................................................................................................................ 11 CRC Computation ...................................................................................................................................... 11 VPID Insertion ............................................................................................................................................ 12 LN/CRC Insertion ....................................................................................................................................... 12 Scrambler/ Encoder ................................................................................................................................... 12 Low-Speed Serializer ................................................................................................................................. 12 Signal Descriptions ............................................................................................................................................. 12 Interfacing with Tri-Rate SDI PHY IP Core ......................................................................................................... 17 SERDES/Board Tx Interface...................................................................................................................... 17 SD 10-bit Mode for Tx ................................................................................................................................ 18 SD LDR Mode ............................................................................................................................................ 18 VPID Extraction.......................................................................................................................................... 19 FPGA Tx Interface ..................................................................................................................................... 19 Custom Format .......................................................................................................................................... 19 Advanced Settings ..................................................................................................................................... 19 SERDES/Board Rx Interface ..................................................................................................................... 19 FPGA Rx Interface ..................................................................................................................................... 20 SD 10-Bit Mode for Rx ............................................................................................................................... 20 Video Payload Identification and Extraction............................................................................................... 20 Integer Frame-Rate Applications ............................................................................................................... 21 Fractional Frame-Rate Applications........................................................................................................... 22 Timing Specifications .......................................................................................................................................... 23 Chapter 3. Parameter Settings ............................................................................................................ 26 PHY Tab.............................................................................................................................................................. 27 PHY Function ............................................................................................................................................. 27 Enable 3G Level-B ..................................................................................................................................... 27 LN Insertion................................................................................................................................................ 28 CRC Insertion............................................................................................................................................. 28 VPID Insertion ............................................................................................................................................ 28 LDR Path for SD ........................................................................................................................................ 28 Include PLL for LDR................................................................................................................................... 28 10-bit Mode for SD Tx ................................................................................................................................ 28 Separate Data Input for SD........................................................................................................................ 29 SD Data Width ........................................................................................................................................... 29 © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG82_01.5, December 2011 2 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Table of Contents VPID Extraction.......................................................................................................................................... 29 10-bit Mode for SD Rx................................................................................................................................ 29 Clock Enable Port ...................................................................................................................................... 29 Custom Format Tab ............................................................................................................................................ 29 Custom Format Support for HD ................................................................................................................. 30 Custom Format Support for 3G.................................................................................................................. 30 Value or Range .......................................................................................................................................... 30 EAV2SAV cycles- Value ............................................................................................................................ 30 EAV2SAV Cycles- Minimum ...................................................................................................................... 31 EAV2SAV Cycles- Maximum ..................................................................................................................... 31 SAV2EAV Cycles- Value............................................................................................................................ 31 SAV2EAV Cycles- Minimum ...................................................................................................................... 31 SAV2EAV Cycles- Maximum ..................................................................................................................... 31 Advanced Tab ..................................................................................................................................................... 31 3G/HD/SDProgram Time ........................................................................................................................... 31 Lock Match Threshold................................................................................................................................ 31 Unlock Error Threshold .............................................................................................................................. 31 Chapter 4. IP Core Generation............................................................................................................. 32 Licensing the IP Core.......................................................................................................................................... 32 Getting Started .................................................................................................................................................... 32 IPexpress-Created Files and Top Level Directory Structure............................................................................... 35 Running Functional Simulation ........................................................................................................................... 37 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 37 Hardware Evaluation........................................................................................................................................... 38 Enabling Hardware Evaluation in Diamond................................................................................................ 38 Enabling Hardware Evaluation in ispLEVER.............................................................................................. 38 Updating/Regenerating the IP Core .................................................................................................................... 38 Regenerating an IP Core in Diamond ........................................................................................................ 38 Regenerating an IP Core in ispLEVER ...................................................................................................... 39 Chapter 5. Application Support........................................................................................................... 40 Tri-Rate SDI PHY IP Loopback and Passthrough Sample Designs ................................................................... 40 Loopback Design ....................................................................................................................................... 40 Passthrough Design............................................................................................................................................ 41 Simulating the Sample Design ............................................................................................................................ 42 Testbench and Configuration File .............................................................................................................. 43 Implementing and Testing the Sample Design ................................................................................................... 45 Board Switch Assignments for Sample Designs ........................................................................................ 45 Transmitter Testing .................................................................................................................................... 46 Receiver Testing ........................................................................................................................................ 46 LCD Display ............................................................................................................................................... 47 Loopback Testing....................................................................................................................................... 47 Passthrough Testing .................................................................................................................................. 47 Chapter 6. Core Verification ................................................................................................................ 48 Chapter 7. Support Resources ............................................................................................................ 49 Lattice Technical Support.................................................................................................................................... 49 Online Forums............................................................................................................................................ 49 Telephone Support Hotline ........................................................................................................................ 49 E-mail Support ........................................................................................................................................... 49 Local Support ............................................................................................................................................. 49 Internet ....................................................................................................................................................... 49 References.......................................................................................................................................................... 49 Lattice Tri-Rate SDI PHY IP Website......................................................................................................... 49 SMTPE Website......................................................................................................................................... 49 IPUG82_01.5, December 2011 3 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Table of Contents LatticeECP3 ............................................................................................................................................... 50 Revision History .................................................................................................................................................. 50 Appendix A. Resource Utilization ....................................................................................................... 51 LatticeECP3 FPGAs............................................................................................................................................ 51 Ordering Information .................................................................................................................................. 51 IPUG82_01.5, December 2011 4 Tri-Rate SDI PHY IP User’s Guide Chapter 1: Introduction Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video production facilities. The availability of high-speed serial inputs/outputs and general purpose programmable logic makes FPGAs (field programmable gate arrays) ideal devices to be used for acquisition, mixing, storage, editing, processing and format conversion applications. Simpler applications use FPGAs to acquire SDI data from one or more SD (standard definition), HD (high definition) or 3G (3-Gigabit HD) sources, perform simple processing and re-transmit the video data in SDI format. Such applications require an SDI PHY (physical layer) interface and some basic processing blocks like a color space converter. In more complex applications, the acquired video is taken through multiple processing phases, like de-interlacing, video format conversion, filtering, scaling, graphics mixing and picture-in-picture display. FPGA devices can also be used as a bridge between SDI video sources and backplane protocols such as PCI Express or ethernet, with or without any additional video processing. In an FPGA-based SDI solution, the physical interface portion is often the most challenging part of the solution. This is because the PHY layer includes several device-dependent components like the high-speed I/Os (inputs/outputs), serializer/de-serializer, clock/data recovery, word alignment and timing signal detection logic. Video processing, on the other hand, is algorithmic and is usually achieved using proprietary algorithms developed by the user’s in-house design engineering teams. The Lattice Tri-Rate SDI PHY intellectual property (IP) core is a complete SDI PHY interface that connects to the high-speed SDI serial data on one side (through LatticeECP3™ SERDES) and the formatted parallel video data on the other side. It enables faster development of applications for processing, storing, and bridging SDI video data. It is comprised of the following major functional blocks: SDI encoder/decoder, word alignment, CRC detection and checking, VPID (video payload identifier) insertion and extraction, and rate detection logic. The IP core supports the following interface standards and source formats for SDI as specified in standards published by the Society for Motion Picture and Television Engineers (SMPTE). Interface: SMPTE 259M-2006 [1] (SD), SMPTE 292M-1998 [2] (HD) and SMPTE 424 M [3] (3G) SD source formats: SMPTE 125M [4] and SMPTE 267M [5] (13.5 MHz only) HD source formats: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9] 3G source formats: SMPTE 425M [10] The Tri-Rate SDI PHY IP core, when connected with the LatticeECP3 SERDES, can transmit and/or receive any of the supported video standards and formats through a common physical serial interface. The Tri-Rate SDI PHY IP core can automatically scan and lock on to any of the supported video streams. Receiving multiple standards requires appropriate external clocks to be supplied by the application in response to commands from the Tri-Rate SDI PHY IP core. IPUG82_01.5, December 2011 5 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Introduction Quick Facts Table 1-1 gives quick facts about the Tri-Rate SDI PHY IP core for LatticeECP3 devices. Table 1-1. Tri-Rate SDI PHY IP Core Quick Facts Tri-Rate SDI PHY IP Core Tx Only Core Requirements Typical Resource Utilization Rx Only Both Tx and Rx FPGA Families Supported LatticeECP3 Minimal Devices Needed LFE3-17EA-6FTN256C Targeted Device LFE3-95EA-7FN1156C Data Path Width 20 LUTs 850 1700 sysMEM EBRs 2500 0 Registers 500 1300 ® Lattice Implementation 1800 ® Lattice Diamond 1.3 or ispLEVER 8.1 Synopsys® Synplify™ Pro for Lattice E-2011.03L Design Tool Support1 Synthesis Mentor Graphics® Precision™ RTL Synthesis 2010a_Update 2.254 Aldec® Active-HDL™ 8.2 Lattice Edition Simulation Mentor Graphics ModelSim™ SE 6.5 1. Design tool support for IP core version 1.3. Features • Dynamic reception of multiple interface standards over the same physical cable: SD-SDI, HD-SDI and 3G-SDI interfaces • Automatic Rx (receive) rate detection and dynamic Tx (transmit) rate selection • Multiple SD source formats support: SMPTE 125M [4] and SMPTE 267M [5] (13.5 MHz only) • Multiple HD source formats support: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9] • Support for 3G source formats, including 3G Level-B format: SMPTE 425M [10] • Word alignment and timing reference sequence (TRS) detection • Field, vertical blanking (vblank) and horizontal blanking (hblank) timing signals generation • CRC computation, error checking and insertion for HD/3G • Line number (LN) decoding and encoding for HD/3G • Custom source format support for HD/3G • Video Payload Identifier (VPID) insertion and extraction for HD/3G • 10-bit parallel input/output support for SD • Soft-logic based low data-rate (LDR) serializer for SD transmission Video Interface and Source Format Support This Tri-Rate SDI PHY IP core supports SMPTE 259, SMPTE 292 and SMPTE 424 interface standards. IPUG82_01.5, December 2011 6 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Introduction SMPTE 259 standard is applicable to 4:2:2 video streams defined by SMPTE 125M and SMPTE 267M. These source formats are briefly described below. 1. SMPTE 125M: System M – 525 lines and 60 fields based on ITU-R BT.601. The video is transmitted in the form of one luminance (Y) and two color-difference components (scaled versions of R-Y and B-Y). It follows a 4:2:2 family level of ITU-R BT.601 with a nominal luminance sampling at 13.5 MHz allowing for both 8-bit and 10-bit data types. 2. SMPTE 267M: System M – 525 lines and 59.94 fields, wide screen, 16x9 aspect ratio, based on ITU-R BT.601. The video is transmitted in the form of one luminance (Y) and two color-difference components (scaled versions of R-Y and B-Y). It follows a 4:2:2 family level of ITU-R BT.601 with a nominal luminance sampling at 13.5 MHz or 18 MHz, allowing for both 8-bit and 10-bit data types. This IP core supports all of SMPTE 125M and only the 13.5 MHz version of SMPTE 267M. SMPTE 292 defines a serial data rate of 1.485 Gbps and 1.485/M Gbps, where M = 1.001. This interface standard supports the source formats defined in the four SMPTE standards: SMPTE 260M, SMPTE 295M, SMPTE 274M and SMPTE 296M. The IP core can transmit, receive and identify all of these source formats. In addition to these formats, the IP core can be configured to receive any custom source format as long as the data conforms to the SMPTE 292M interface standard. This is achieved by allowing the user to define the source format in terms of the number of words between SAV (start of active video) and the next EAV (end of active video) and the number of words between EAV and the next SAV. It is also possible to have the IP receive multiple custom source formats by specifying a range for the above values. The source format support for SMPTE 424M is specified by the SMPTE 425M specification [10]. SMPTE 425 defines four mapping structures that map the HD source formats to the 3G interface. The higher stream rate is used to accommodate 4:2:2 50p, 4:2:2 60p, 4:4:4, 4:4:4:4 and 12-bit formats. The Lattice Tri-Rate SDI PHY IP core detects the interface standard as 3G and the source format as one of many video and frame formats. The IP also supports the transmission and reception of 3G Level-B video formats. The following mapping nomenclature specified in SMPTE 425M are supported: • SMPTE 372M dual link payloads on a 3 Gbps interface • 2x720-line video payloads on a 3 Gbps interface • 2x1080-line video payloads on a 3 Gbps interface IPUG82_01.5, December 2011 7 Tri-Rate SDI PHY IP User’s Guide Chapter 2: Functional Description This chapter describes the functionality of the Tri-Rate SDI PHY IP core. The high-level functional diagram of the Tri-Rate SDI PHY IP core is shown in Figure 2-1. Figure 2-1. Tri-Rate SDI PHY IP Core, High-Level Functional Diagram Rate Detection/ Control rx_hd_sdn rx_tg_sdn rx_lb_lan rxdata rx_clk Decoder / Descrambler VPID Extraction CRC Checker Word Alignment/ TRS Detection vpid_out crc errors pd_out timing signals Format Detection Receive Logic vid_active vid_format frame_format Transmit Logic txdata Scrambler/ Encoder VPID Insertion CRC/LN Insertion pd_in pdi_clk trs_in vpid_in txd_ldr Low-Speed Serializer Figure 2-1 shows the top-level functional view of the IP core. As shown, the Tri-Rate SDI PHY IP core does not include the LatticeECP3 SERDES in it. The top portion of the diagram shows the receiver and the bottom portion the transmitter. The Tri-Rate SDI PHY IP core is capable of receiving any of the video formats specified in the SMPTE 259M, SMPTE 292M and SMPTE 424M interface standards through the same physical input without the need for any manual intervention. The receiver can dynamically support the different video stream rates: SD video at 270 Mbps, HD integer frame rate video at 1.485 Gbps, HD fractional frame rate video at 1.4835 Gbps, 3G integer frame rate video at 2.97 Gbps and 3G fractional frame rate video at 2.967 Gbps. The multi-rate receiver cyclically scans for each of the video rates until it identifies and locks to the incoming video data. When scanning for a video rate, the IP core gives out the interface rate that it is trying to receive. The SERDES settings and reference clocks have to be changed to match this rate information. If there is a valid video corresponding to the scanned rate, the IP core locks to the video source and provides the parallel data and status outputs for that video. If no video is received or if there are multiple errors in the received data, the receiver goes on to scan the next rate. The scanning process continues until the receiver “locks” to the incoming video, that is, when the video data reception is valid and error-free for a few lines of video data. The Tri-Rate SDI PHY IP core is also capable of supporting dynamically varied transmit rates. The different video rates, viz., SD, HD and 3G are identified by the rate select input signals. The Tri-Rate SDI PHY IP core assumes that the clocks and the data applied at the inputs correspond to the rate select signals. Receiver A high-level block diagram of the tri-rate SDI receiver is shown in Figure 2-2. The receive side logic is comprised of the following logic blocks: decoder/descrambler, word alignment/TRS detection, rate detection and control, format IPUG82_01.5, December 2011 8 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description detection, CRC checker, XYZ word decoder, LN decoder and VPID extraction module. A description of each of these blocks is given below. Figure 2-2. Tri-Rate SDI Receiver, High-Level Block Diagram Rate Detection/ Control rx_lb_lan rx_tg_sdn rx_hd_sdn rxdata rx_clk Decoder / Descrambler rx_rate eav_error sav_error vid_active trs_out ychannel Word Alignment/ TRS Detection pd_out Format Detection vid_format frame_format CRC Checker y1_crc_error c1_crc_error y2_crc_error c2_crc_error xyz Word Decoder field vblank hblank LN Decoder VPID Extraction ln1_out ln2_out vpid1_out vp1_valid vp1_cserr vp1_parerr vp1_lineok Decoder/Descrambler All the interface standards supported by the Tri-Rate SDI PHY IP core specify the same scrambling and encoding methods. The polynomials used are given in the sub-section on the scrambler. The decoder/descrambler is implemented in the 20-bit parallel path. The input data is first decoded to NRZ and then descrambled following an essentially reverse process of the encoding and scrambling operations. Word Alignment/TRS Detection The receiver reads the raw, possibly misaligned parallel data from the SERDES. The word alignment block determines the degree of misalignment (offset) by looking for the special TRS sequences in the data. TRS is the unique sequence, 3FFh,000h,000h, in the video stream that marks either the end of active video (EAV) or the start of active video (SAV) time instants. In HD and 3G Level-A video streams, since two independent video streams are interleaved, the timing reference sequence to look for is 3FFh, 3FFh, 000h, 000h, 000h, 000h. The TRS for 3G Level-B video is 3FFh, 3FFh, 3FFh, 3FFh, 000h, 000h, 000h, 000h, 000h, 000h, 000h, 000h. Once the offset is determined, the words are re-aligned using the offset value. Rate Detection and Control This module is the heart of the multi-rate SDI receiver infrastructure. Rate detection is the process of determining the interface standard of the incoming video stream. Rate detection is performed by sequentially scanning the input for different interface standards. During each rate scan, the receiver identifies the rate that is being scanned through some output ports, to allow the external modules like the SERDES and clock generator, to be set to that rate. Once the clock generator and the SERDES are set to a data rate, the receiver tries to receive the signal for that rate. The receiver checks the TRS instances (number of active words and total words) to see if they are consistent with the source formats for the interface standard that is being received. If they match, the receiver locks to this IPUG82_01.5, December 2011 9 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description video stream and asserts the vid_active signal. On the other hand, if the TRS instances are not consistent with the source formats that are expected for the current scanned rate, the receiver advances to scan the next rate. The rate detection state machine is set to scan for the HD rate first, followed by 3G and SD rates and then to go back to scan HD to start the sequence over. The state machine advances to scan the next rate only if that rate is enabled by the dynamic input signal rx_rate. For each scan rate, the state machine goes through three states“Program”, “Check” and “Lock”. The state advances are based on the number of TRS matches, TRS mismatches and time-out errors. A time-out error occurs when a TRS is not received in a reasonably long duration of time. During the “Program” state, the external clock sources are set to provide the relevant clocks and/or the SERDES dividers are set to receive the relevant rate. If a TRS is received or if the number of time-out errors is more than the value set using “3G (HD/SD) Programming time” parameter, the state machine advances to the “Check” state. While in the “Check” state, if the number of TRS matches reaches the value set for “Lock match threshold” parameter, the state machine advances to “Lock” state. On the other hand, if the number of TRS mismatches and timeout errors exceeds the “Unlock error threshold” value, the state machine advances to the “Check” state for the next rate. While in the “Lock” state, the state machine continues to be in that state as long the number of time-out and TRS mismatch errors are within “Unlock error threshold” value. When the number of errors exceeds the threshold while in the “Lock” state, the state machine advances to the “Check” state for the next rate. SMPTE 292M and SMPTE 424M also define a fractional frame rate video stream compliant with the North American standards. Thus SMPTE 292M includes a 1.4835 Gbps data rate in addition to the 1.485 Gbps rate and SMPTE 424M includes a 2.967 Gbps data rate in addition to the 2.97 Gbps rate. This IP core supports both the integer and fractional frame rates, as long as the data and clock inputs to the IP core are consistent with the corresponding rates. While the IP core can receive both integer and fractional frame rate standards, it will not be able to distinguish between the two. However, integer or fractional frame rate standards can be easily determined by constructing a small logic circuit outside the IP to compare the frequency of the receive recovered clock with that of another clock of known frequency (like the receive reference clock or the 100 MHz clock available on the LatticeECP3 Video Protocol Board). Format Detection This module determines the source format of the input video stream. The format is based on the number of active words, number of total words and whether the video is interlaced. The format is provided through the vid_format and frame_format output ports. For 3G Level-B video (3G-b), the stream 1 video data is used for format detection. CRC Checker The CRC checker computes the CRC values for each of the video streams and components and compares those with the CRC values available in CR0 and CR1 words of the received video. In HD and 3G Level-A video (3G-a) streams, there are two CRC words per line that contain the CRC value for the previous line. The CRC checker computes the CRC for each line, compares with the received CRC and flags an error if there is a mismatch. For 3G-b, there are four CRC words, one each for the Y and C components of each stream. Errors are flagged separately for each of the four CRC comparisons. XYZ Word Decoder This block decodes the “XYZ” word that follows the TRS in the video stream. By decoding the XYZ word, the video timing signals field, hblank (horizontal blanking) and vblank (vertical blanking) are determined. XYZ word is also used to determine whether the TRS corresponds to an EAV or a SAV instant. LN Decoder In HD and 3G video formats, the line number is encoded as a two-word sequence and inserted after the XYZ word of the EAV sequence. The LN decoder block decodes the line number from the LN double words and gives out the line number value on the ln1_out port. For 3G-b, the line numbers for stream 1 and stream 2 video are separately given out on ln1_out and ln2_out ports respectively. IPUG82_01.5, December 2011 10 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description VPID Extraction The VPID extraction module extracts the video payload information (SMPTE 352M [11]) embedded in the HANC part of the video stream. In addition to the VPID bytes, this module also provides some error and status signals. The status signal vp1_valid indicates whether the last received VPID information was valid and the signal vp1_lineok indicates if the VPID was available in the appropriate line numbers for the received format. The error signals vp1_cserr and vp1_parerr are used to denote the checksum error and parity error respectively. Transmitter The transmitter supports dynamic multi-rate operation catering to SD, HD and 3G standards. The transmit rate is set through the input ports, hd_sdn_in and lb_lan_in as well by the frequency of pdi_clk. The transmitter and receiver are independent of each other and each can be used to transport any rate or format. A high-level block diagram of the transmitter is shown in Figure 2-3. Figure 2-3. Multi-Rate SDI Transmitter, High-Level Block Diagram LN Encoder txdata Scrambler / Encoder LN/CRC Insertion ln1_in ln1_set ln2_in ln2_set hd_sdn_in lb_lan_in trs_in sd8b_mode pdi_clk pd_in CRC Computation txd_ldr LowSpeed Serializer VPID insertion Scrambler / Encoder video8b vpid1_in vpid2_in pd_in_sd The input data to the transmitter is SMPTE-formatted parallel video data, which typically includes active video, blanking, ANC (Ancillary), and TRS words. If the CRC and line number (LN) words for HD/3G are available in the video stream, the IP core can pass them on. If the CRC and/or LN information is not available from the stream, the IP can fill them in and insert them in the stream at the right places. The transmitter is comprised of the following logical modules: LN encoder, CRC computation, VPID insertion, LN/CRC insertion, scrambler/encoder and lowspeed serializer. A brief description of each of these modules is given below. LN Encoder The LN encoder converts the raw line number value read from the input port to two LN words for insertion in the video stream. This module is used only for HD/3G inputs. This module is optional and used only when the LN words are not already available in the video data stream. For 3G-b video, there are two line number input ports, ln1_in and ln2_in, one for each of the two 3G-b video streams. CRC Computation The CRC computation module is optionally added if the CRC insertion option is enabled through the IP GUI. The CRC is computed separately for each Y and C component of the entire active line, encoded to two CRC words per component and embedded at the appropriate places in the next line. For 3G-b streams, there are four separate IPUG82_01.5, December 2011 11 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description CRC computations, one for each component and each stream. Line-based CRC is supported only for HD/3G standards, i.e., when the input hd_sdn_in is high. The CRC is computed using the following polynomial equation: CRC (X) = X18 + X5 + X4 + 1 VPID Insertion This module prepares the VPID words and determines the checksum from the raw VPID value(s) read from vpid1_in (and vpid2_in) port for insertion into the video stream. This module also determines the line number of the current video line and the appropriate line number when the VPID must be inserted for the current standard. LN/CRC Insertion This module inserts the computed CRC and LN words at appropriate places in the data stream before the data is sent to the Scrambler/Encoder module. Scrambler/ Encoder This module performs scrambling and NRZI (Non-Return to Zero-Inverted) encoding per the requirements set forth in SMPTE 259M, SMPTE 292M and SMPTE 424M standards. The scrambler implements the following equation: G1(x) = x9 + x4 + 1 The NRZI encoder is defined by the following equation: G2(x) = x + 1 Low-Speed Serializer This block is the FPGA fabric-based serializer used for SD video transmission. This is required when fractional frame rate HD/3G and SD streams are to be transmitted from different channels of the same SERDES quad. In this scenario, the low-speed serializer replaces the SERDES serializer for SD transmission. Signal Descriptions The top-level interface for the Tri-Rate SDI PHY IP core is shown in Figure 2-4. A brief description of the signals is given in Table 2-1. While the figure and table show the exhaustive port list for the IP core, some ports may not be available for a selected configuration. IPUG82_01.5, December 2011 12 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Figure 2-4. Tri-Rate SDI PHY IP Core, Top-Level Interface pd_out pdo_clk vid_active vid_format frame_format trs_out ychannel field rx_clk rx_full_clk rx_hd_sdn rx_tg_hdn rx_lb_lan hblank ln1_out FPGA Rx Interface rxdata SERDES/Board Rx Interface vblank ln2_out eav_error sav_error y1_crc_error c1_crc_error y2_crc_error c2_crc_error vpid1_out vp1_valid vp1_cserr vp1_parerr vp1_lineok vpid2_out Tri-Rate SDI PHY IP Core vp2_valid vp2_cserr ce Common Interface rstn vp2_parerr vp2_lineok rx_rate pd_in pdi_clk tx_half_clk pd_in_sd FPGA Tx Interface txdata SERDES/Board Tx Interface txd_ldr trs_in hd_sdn_in lb_lan_in sd8b_mode ln1_in ln1_set ln2_in ln2_set vpid1_in vpid2_in clk27_in clk270_in clk27_out clk270_out IPUG82_01.5, December 2011 13 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Table 2-1. Top-Level I/O Interface Port Bits I/O Description SERDES/Board Rx Interface rxdata 20 I Received data (parallel) from the SERDES. This input is read in using rx_clk. rx_clk 1 I This clock is synchronous with rxdata. The frequency of this clock is 148.5 MHz or 148.35 MHz for 3G, 74.25 MHz or 74.175 MHz for HD and 13.5 MHz for SD. This usually comes from the Rx recovered clock (rx_half_clk_chx) from the SERDES CDR. I This clock is required if 10-bit/27 MHz SD output is enabled (i.e. when the 10-bit mode for SD Rx option is selected). This clock must be frequency-synchronous with rx_clk and should be exactly double the frequency of rx_clk while receiving SD video. The Rx recovered clock from the SERDES (rx_full_clk_chx) can be directly used for this clock. rx_full_clk 1 rx_hd_sdn 1 O HD or SD status output. This signal indicates the rate that is being received by the IP (a zero value for SD and a one value for HD or 3G). This signal can be used to set the SERDES to receive the right rate and/or command the clock generator to output the appropriate clock. rx_tg_hdn 1 O 3G or HD status output. This signal indicates the rate that is being received by the IP (a zero value if SD or HD and a one value if 3G). This signal can be used to set the SERDES to receive the right rate and/or command the clock generator to output the appropriate clock. rx_lb_lan 1 O 3G Level-B or not status output. This signal indicates whether the received video is a 3G Level-B stream or not. This output is one if the received video is 3G Level-B and zero otherwise. SERDES/Board Tx Interface txdata 20 O Transmit data (parallel) to the SERDES. This data is synchronous with the tx_half_clk or pdi_clk, depending on whether 10-bit mode for SD Tx is enabled or not. txd_ldr 1 O Low data rate transmit data. This is the transmit data for the SD rate, serialized in the IP to be connected to the out-of-band transmit path of the SERDES channel. This output is typically connected to txd_ldr_chx of the SERDES. rstn 1 I System-wide asynchronous active-low reset signal. This signal resets all the registers in the IP. ce 1 I Optional clock enable signal. A zero input at ce freezes all the switching operations in the IP. It is useful for putting the IP in a power save mode. 20 O Parallel data output. This is the parallel video data output from the receiver. This data is synchronous with the receiver clock rx_clk, if 10-bit mode for SD Rx is disabled. It is synchronous with the pdo_clk if 10 bits mode for SD Rx is enabled. Common Interface FPGA Rx Interface pd_out pdo_clk 1 O Parallel data output clock. This clock port is available when the 10-bit mode for SD Rx option is selected. This clock is a multiplexed version of rx_clk and rx_full_clk. If this clock is available, the output data as well as output status and control signals are synchronous with this clock. vid_active 1 O Video active signal. This output signal is high if the receiver is locked to a valid video stream at the receiver input. Video format output. The format is identified as follows: vid_format 2 O 00 – 1440 x 486/576 01 – 1280 x 720 10 – 1920 x 1035 11 – 1920 x 1080 For 3G-b outputs, the video format corresponds to stream 1 video. IPUG82_01.5, December 2011 14 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Table 2-1. Top-Level I/O Interface (Continued) Port Bits I/O Description Frame format output. This output identifies the number of fields and whether the video is interlaced or progressive as follows: frame_format 3 O 000 – Unknown or custom 001 – 24p or 23.98p or 23.98psF 010 – 25p, 25psF 011 – 30p or 29.97p or 29.97psF 100 – 50i 101 – 60i or 59.94i 110 – 50p 111 – 60p or 59.94p For 3G-b outputs, the frame format corresponds to stream 1 video. trs_out 1 O Timing reference sequence output. This output is high during the start of the TRS sequence, i.e., during the time when 3FFh or FFFFFh is available on pd_out. For 3G-b video, this output is high during the Y-channel FFFFFh word. ychannel 1 O Y-channel indicator. This output is meaningful only when 3G-b video is received. This output is one when Y-channel data is given out at pd_out and zero when C-channel data is given out. field 1 O Field number. This is the field number information available in the XYZ word. The field value at this output changes state when the XYZ word appears at the output. For 3G-b video, the field output corresponds to stream 1 video and it changes state when the ychannel XYZ word appears at the output. vblank 1 O Vertical blanking signal. The value at this output changes state when the XYZ word appears at the output. For 3G-b video, the vblank output corresponds to stream 1 video and it changes state when the y-channel XYZ word appears at the output. hblank 1 O Horizontal blanking signal. The value at this output changes state when the XYZ word appears at the output. For 3G-b video, the hblank output corresponds to stream 1 video and it changes state when the y-channel XYZ word appears at the output. ln1_out 11 O Line number output. This provides the line number corresponding to the current parallel data output. This output is not valid for SD video rates. The value at this output changes when LN1 word is given out at pd_out port. When 3G-b video is being received, this output corresponds to stream 1 video and changes state when y-channel LN1 word is given out at pd_out port. ln2_out 11 O Line number output for stream 2 video. This output is valid only when 3G-b video is being received. The output changes state when y-channel LN1 word is given out at pd_out port. eav_error 1 O EAV error output. This one-cycle pulse indicates that an EAV has been received at an incorrect time instant or that the EAV has not been received when it should have been received. sav_error 1 O SAV error output. This one-cycle pulse indicates that a SAV has been received at an incorrect time instant or that the SAV has not been received when it should have been received. y1_crc_error 1 O This signal indicates that a CRC error has been detected for the y-channel of the current line. This output is not valid for SD video rates. The CRC error output goes high during the clock cycle when the CRC comparison is made. When 3G-b video is being received, this output denotes the CRC error for the y-channel of stream 1 video. c1_crc_error 1 O This signal indicates that a CRC error has been detected for the c-channel of the current line. This output is not valid for SD video rates. The CRC error output goes high during the clock cycle when the CRC comparison is made. When 3G-b video is being received, this output denotes CRC error for the c-channel of stream 1 video. y2_crc_error 1 O This signal is valid only when receiving 3G-b video. This output indicates that a CRC error has been detected for the y-channel of the current line of stream 2 video. c2_crc_error 1 O This signal is valid only when receiving 3G-b video. This output indicates that a CRC error has been detected for the c-channel of the current line of stream 2 video. vpid1_out (vpid2_out) 32 O Video payload identifier output. This output is not valid when receiving SD video. The VPID bytes are organized as follows: {byte4, byte3, byte2, byte1}. When receiving 3G-b video, this output corresponds to the VPID for stream 1. The stream 2 VPID in that case is available at vpid2_out port. IPUG82_01.5, December 2011 15 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Table 2-1. Top-Level I/O Interface (Continued) Port Bits I/O vp1_valid (vp2_valid) 1 O VPID valid output. This output indicates that the VPID received is valid as determined by the ADF, DID and SDID words. When receiving 3G-b video, this output corresponds to stream 1. The stream 2 VPID valid in that case is available at vp2_valid port. vp1_cserr (vp2_cserr) 1 O VPID checksum error output. This output denotes a checksum error for the received VPID. When receiving 3G-b video, this output corresponds to stream 1 video. The stream 2 VPID checksum error in that case is available at vp2_cserr port. vp1_parerr (vp2_parerr) 1 O VPID parity error output. This output denotes a parity error for the received VPID. When receiving 3G-b video, this output corresponds to stream 1. The stream 2 VPID parity error in that case is available at vp2_parerr port. O VPID line okay output. This output indicates that the VPID was embedded in the correct line number of the received video. VPID needs to be embedded at line 10 for progressive transports and lines 10 and 572 for interlaced transports. When receiving 3G-b video, this output corresponds to stream 1 video. The stream 2 VPID line okay indication in that case is available at vp2_lineok port. vp1_lineok (vp2_lineok) 1 Description This input command controls the rates scanned by the receiver. Each bit enables the scanning of one of the rates, as shown below: rx_rate 3 I rx_rate [2]: 0 - disable 3G scan, 1 - enable 3G scan rx_rate [1]: 0 - disable HD scan, 1 - enable HD scan rx_rate [0]: 0 - disable SD scan, 1 - enable SD scan This is an asynchronous control input. The receiver scans only for the rates that are enabled. However, if the scan for one of the rates is disabled when that rate is being received, the reception is not affected. FPGA Tx Interface pd_in pdi_clk tx_half_clk pd_in_sd 20 1 1 10 I Parallel data input. This is the parallel video data for transmission. The data is read with pdi_clk. If the 10-bit mode for SD Tx is enabled, only the lower 10 bits of the data are read in when reading SD data. I Clock input for the parallel input data. The data at pd_in is read using this clock. This clock should have the same frequency as the transmit reference clock to the SERDES (divided appropriately by 1, 2 and 11 for 3G, HD and SD respectively). In a typical usage, this clock is the same as Tx half clock from the SERDES if 10-bit mode for SD Tx is disabled and a multiplexed version of Tx half clock and Tx full clock if 10-bit mode for SD Tx is enabled. I This additional clock input is required, if the 10-bit mode for SD Tx option is selected. This clock must be frequency-synchronous with pdi_clk and must correspond to the 20-bit data width. The frequency of this clock is 148.5 MHz or 148.35 MHz for 3G, 74.25 MHz or 74.175 MHz for HD and 13.5 for SD. The SERDES tx_half_clk output can be connected to this input, as long as pdi_clk is derived from the same SERDES output clock. I Optional parallel data input for SD. If available, the data on this port is read in with clk27_in. trs_in 1 I Timing Reference Sequence identifier for the input video stream. This is a one-clock cycle wide pulse that identifies the TRS instance in the parallel input data. This input is high during the start of the TRS sequence for HD and 3G-a inputs, i.e., during the time when FFFFFh is presented on pd_in. For 3G-b video, this input is high during the Y-channel FFFFFh word. The trs_in signal is used for the computation of CRC as well as to determine CRC, LN and VPID insertion instants. This signal is not used for SD or if CRC, LN and VPID insertions are all disabled for HD/3G. hd_sdn_in 1 I HD/SD input. This input must be zero to transmit SD video and one for 3G or HD video. lb_lan_in 1 I 3G Level-B indicator input. This input must be one if the input is a 3G-b video and zero otherwise. I SD 8-bit mode. If this input is high, the incoming data is considered to be 8 bits wide. Only the most significant 8 bits (bits [9:2]) are read from the port. The least significant 2 bits are set to zero for all data except the leading TRS sequence (or ANC identifier). When the most significant 8 bits are 1’s, then the least significant 2 bits are made equal to ‘11’. sd8b_mode 1 IPUG82_01.5, December 2011 16 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Table 2-1. Top-Level I/O Interface (Continued) Port ln1_in (ln2_in) ln1_set (ln2_set) Bits 11 1 I/O Description I Line number input. This input is read in HD/3G modes only. The line number is read in when ln1_set is high. When transmitting 3G-b video, this input provides the line number for stream 1 video. In that case, ln2_in is used to read the line number for the stream 2 video and ln2_set is used as strobe. I Line number set signal. This signal is used as a strobe to read the value at the ln1_in port. The line number must be set during or before LN0 word is applied at the pd_in input. When transmitting 3G-b video, this input serves as a strobe for the line number for stream 1 video. In that case, ln2_set is used to strobe the line number for the stream 2 video. vpid1_in (vpid2_in) 32 I Video payload identifier input. This input is not used when transmitting SD video. The VPID bytes are organized in the following order: {byte4, byte3, byte2, byte1}. When transmitting 3G-b video, this input corresponds to the VPID for stream 1. The stream 2 VPID in that case is read from the vpid2_in input port. clk27_in 1 I This is the 27 MHz input clock for the optional 10-bit/27 MHz SD Tx interface. This clock must be frequency-synchronous with pdi_clk (exactly double that of pdi_clk) during SD operation, if the parameter LDR path for SD is not selected. clk270_in 1 I This is the 270 MHz serial clock used for SD serialization in soft logic. This port is available if the LDR path for SD option is selected and the Include PLL for LDR option is not selected. This clock frequency must be exactly 10 times that of clk27_in. clk27_out 1 O SD LDR clock output. This 27 MHz clock is synchronous with clk270_out and is available if Include PLL for LDR is selected. This clock, along with clk270_out is useful for feeding another IP instance. clk270_out 1 O High-speed SD LDR clock output. This 270 MHz clock is synchronous with clk27_out and is available if Include PLL for LDR is selected. This clock, along with clk27_out is useful for feeding another IP instance. Interfacing with Tri-Rate SDI PHY IP Core The Tri-Rate SDI PHY IP core is a single-channel transmit/receive PHY and it does not include the SERDES. This section provides some detail on interfacing with the IP, including connecting the IP with the LatticeECP3 SERDES. SERDES/Board Tx Interface The encoded and formatted parallel data from the IP core is given out of the 20-bit txdata output port. This directly connects to the SERDES parallel input for serialization. The output from the IP is synchronous with tx_half_clk or pdi_clk, depending on whether 10-bit mode for SD Tx is enabled or not. By deriving the pdi_clk from SERDES’ Tx half clock and Tx full clock, the data can be made synchronous with the SERDES Tx PLL clock. The Tx half clock from the SERDES can then be used to drive data into SERDES Tx (for SERDES’ txi_clk). Refer to Figure 2-5 for an illustration of how the clocks and data are synchronized for the Tx path. IPUG82_01.5, December 2011 17 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Figure 2-5. LDR and 10-Bit Data Path for Tx if (sd_tx_10bits=1) 1 pd_in 2 1 pdi_clk tx_half_clk 2 Basic Tri-rate IP Tx module without 10 bits or LDR options (20 bits, halfrate - 148.5/ 74.25/13.5) tx_data if (sd_ldr=1) pd_in_sd 4 3 if ((sd_ldr=1) and (pdinsd_port=0)) SD8bits Scrambler Serializer txd_ldr 5 6 clk27_in PLL 5 6 clk270_in Notes on switch positions: If (sd_tx_10bits=1) connection 1 is active, else connection 2 is active. If (pdinsd_port=0) connection 3 is active, else connection 4 is active. If (sdpll_exclude=1) connection 5 is active, else connection 6 is active. SD 10-bit Mode for Tx The Tri-Rate SDI PHY IP is designed to directly interface with the LatticeECP3 SERDES. Since the width of the SERDES data interface has to be fixed at 20 bits for multi-rate operation, the data transfer frequency is fixed at 13.5 MHz for SD rate. In the simplest configuration, the IP takes in 20 bits of SD data at 13.5 MHz to be consistent with the SERDES interface. However, since most SD video is typically available as 10-bit, 27 MHz data, the IP offers the 10-bit option for the SD interface. The 10-bit SD options are provided separately for Tx and Rx paths. With the 10bit mode for SD Tx option, SD data is applied at the lower 10 bits of pd_in and the corresponding 27 MHz clock is applied at the pdi_clk input. The clock synchronization used in the IP core for the SD 10 bits and SD LDR options are shown in Figure 2-5. SD LDR Mode This is the SD low data rate transmit mode. This mode is used if it is necessary to transmit fractional frame rate HD or 3G video and SD video in different channels of the same SERDES quad. LatticeECP3 SERDES has only one transmit PLL for each quad. This means that the transmit frequencies of different channels in the quad must either be same or one of the permissible divided frequencies. If the SERDES PLL is tuned for 2.97 GHz, the channels can transmit 2.97 Gbps, 1.485 Gbps and 270 Mbps. However, if the PLL is tuned for 2.967 GHz, the channels can only transmit 2.967 Gbps and 1.4835 Gbps. They cannot be used to transmit 270 Mbps. In this scenario, the LDR path is employed for transmitting the SD video. In the LDR scheme, a serializer is built in the soft logic and its output is multiplexed with the SERDES serial output at the driver end of the SERDES. The multiplexer at the output of the SERDES is dynamically controlled by the SERDES input control signals txd_ldr_en_chx. As shown in Figure 2-5, the parallel data for the LDR serializer can come from either the main input data bus, pd_in or the dedicated 10-bit SD input bus pd_in_sd. If the data is read from the common input bus, the input clock pdi_clk and the LDR clock, clk27_in must be frequency-synchronized during the time SD is transmitted. The 270 MHz bit-rate clock for LDR, clk270_in must be exactly 10 times the frequency of clk27_in. IPUG82_01.5, December 2011 18 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description VPID Extraction The VPID extraction option enables the extraction of VPID bytes embedded in the horizontal ancillary (HANC) data area of specific lines in the video stream. In addition to the VPID bytes, a few other signals are brought out to indicate a valid VPID, the appropriate lines carrying VPID information, checksum error and parity error. FPGA Tx Interface The FPGA side transmit interface consists of the parallel video data to be transmitted, LN/ VPID input data, clocks and rate identification inputs. If SD transmission is not used or if the SD parallel data is available as 20-bit/13.5 MHz data, only one clock (pdi_clk) is required for the entire transmit logic. In that case, the pdi_clk as well as the txi_clk can both be connected to the Tx half clock from the SERDES. However, if the SD data is available as a 10-bit/27 MHz data stream, the 10-bit mode for SD Tx option needs to be enabled. In this case, the additional tx_full_clk input can be connected to the Tx full clock from the SERDES. The pdi_clk can be a multiplexed version of Tx full clock and Tx half clock from the SERDES. Most of the transmit logic and the data output to SERDES Tx uses tx_half_clk as shown in Figure 2-5. When the 10-bit mode for SD Tx option is enabled, the 10-bit parallel input for SD video is applied at pd_in_sd. In this case, the SD transmit path is independent and asynchronous with the HD/3G transmit path. The SD data is applied with respect to the clk27_in clock and the entire SD transmit logic operates with this clock. In addition to the 27 MHz clock, another bit-rate clock at 270 MHz (having exactly 10 times the frequency of the 27 MHz clock), is also required for the LDR transmission. If the Include PLL for LDR option is selected, the 270 MHz clock is internally generated within the IP. In this case, both the 27 MHz and the 270 MHz clocks are given out through clk27_out and clk270_out ports. Custom Format Valid HD and 3G rates are identified by matching the relative time instants of EAV and SAV timing signals to the possible source format standards in that rate. The IP supports receiving non-standard formats, by accepting custom formats for 3G and HD rates. The custom formats are specified by the time from EAV to SAV and from SAV to EAV. The time can be specified as a fixed value or a range defined by a minimum and a maximum. The custom format for 3G-b is set based on the format of the stream 1HD component that is part of the 3G video. Advanced Settings The Advanced Settings tab allows the user to specify the programming time and threshold values. The programming time is specified by a number proportional to the time from which the receiver waits from switching to a new rate and before looking for TRS matches for that rate. Lock match threshold is the number of TRS matches to wait, before locking to a video rate. Unlock error threshold is the number of TRS or timeout errors after which the receiver unlocks to scan for the next rate. SERDES/Board Rx Interface The deserialized parallel output from the SERDES can be directly connected to the rxdata port. The parallel data connection to and from the SERDES is always 20 bits wide irrespective of any SD 10-bit mode set in the IP. The parallel data is read in using rx_clk. If the data comes directly out of the SERDES Rx, then the Rx recovered clock from the SERDES must be connected to the rx_clk input. If the 10-bit mode for SD Rx option is enabled, the IP core needs the 27 MHz recovered clock for the SD data to be applied at the rx_full_clk port. The output signals, rx_hd_sdn, rx_tg_hdn and rx_lb_lan indicate the rate that the receiver is trying to receive or lock on to. It is important for that these signals be used to promptly change the SERDES divider settings or the frequency of the clock generator that supplies the input clock ports. The outputs rx_hd_sdn and rx_tg_hdn can be used to drive the clock divider controls of the LatticeECP3 SERDES to select one of the three rates (3G, HD and SD) to receive. IPUG82_01.5, December 2011 19 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description FPGA Rx Interface The FPGA Rx interface includes the parallel output data, output clock, video status/format outputs, video timing signals, LN output, CRC and EAV/SAV error outputs, VPID bytes and VPID status/error outputs. The parallel data output is synchronous with the pdo_clk if 10 bits mode for SD option is enabled and with the rx_clk otherwise. The pdo_clk is derived by multiplexing rx_clk and rx_full_clk using FPGA logic as shown in Figure 2-6. Figure 2-6. SD 10-Bit Data Path for Rx rxdata 10'b0 Basic Tri-rate IP Rx module without 10-bit SD Rx option (20-bit, halfrate – 148.5/ 74.25/13.5) 0 1 pd_out 0 1 rx_clk rx_hd_sdn pdo_clk rx_full_clk if (sd_rx_10bits = 1) The vid_format and frame_format values are determined from the relative EAV/SAV positions in the received data and whether the field value is toggling or not. The y-channel data is always used for format determination. For 3Gb video, the format determination is based on the y-channel data of stream 1 video. The line number output, ln1_out (and ln2_out, if receiving 3G-b video) is the line number contained in the LN0 and LN1 words of the received y-channel data. If it is not necessary to scan for all the three rates, it is possible to disable the scanning of a particular rate or rates. The 3-bit rx_rate input can be used to independently disable the scanning of a rate or a combination of rates. The scan enable inputs can be dynamically changed. Rate scan disable applies only when the receiver goes on to scan a rate. Therefore, disabling a rate that is being currently received or locked on to will not affect the reception of that rate. SD 10-Bit Mode for Rx Similar to the 10-bit option for SD Tx, the 10-bit option for SD Rx provides SD data output at 27 MHz and 10 bits. A block diagram of the 10-bit mode is shown in Figure 2-6. The SD output is available at the lower 10 bits of the common pd_out port. If this option is selected, the IP provides an output clock, pdo_clk that is synchronous with the output data. The output clock pdo_clk is the multiplexed version of rx_half_clk and rx_full_clk, the recovered clocks from the SERDES. Video Payload Identification and Extraction The 4-byte video payload identifier (VPID) added to the ancillary data space of SDI interfaces is defined in the SMPTE 352M standard. The VPID bytes are added as ancillary data and follow the general format of ANC data defined by the SMPTE 291M [12] standard. The VPID is inserted in the y-channel (for 3G-b, in the y-channel of both stream 1 and stream 2 videos) on particular video lines depending on the video format. Figure 2-7 shows the organization of VPID bytes in the SDI formatted data. IPUG82_01.5, December 2011 20 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Figure 2-7. Format and Structure of Video Payload Identifier HD stream, 20 bits at 74.25 MHz or 3G Level-A stream, 20 bits at 148.5 MHz SAV 000 (Y) (1) XYZ (Y) (1) Y data 000 (C) (1) Cb data 000 (Y) (1) XYZ (C) (1) 3FF (Y) (1) 000 (C) (1) Data 3FF (C) (1) CS (Y) byte4 (Y) byte3 (Y) byte2 (Y) YCR1 CCR1 byte1 (Y) YCR0 CCR0 04h LN1 (Y) LN1 (C) 01h LN0 (Y) LN0 (C) 41h XYZ (Y) XYZ (C) 3FF (Y) 000 (Y) 000 (C) 000 (Y) 000 (Y) 000 (C) 3FF (Y) 3FF (Y) 3FF (C) Other ANC data Y data VPID Cr data ADF CS CRC DC LN SDID EAV DID VPID ANC data 3G Level-B stream, 20 bits at 148.5 MHz ADF CS CRC DC LN SDID EAV DID VPID ANC data VPID SAV 3FF (C) (1) 3FF (Y) (1) 000 (C) (1) 000 (Y) (1) 000 (C) (1) 000 (Y) (1) XYZ (C) (1) XYZ (Y) (1) Cb data (1) Y data (1) Cr data (1) Y data (1) Data 3FF (C) (2) 3FF (Y) (2) 000 (C) (2) 000 (Y) (2) 000 (C) (2) 000 (Y) (2) XYZ (C) (2) XYZ (Y) (2) Cb data (2) Y data (2) Cr data (2) Y data (2) CS (Y) (1) byte1 (Y) (1) byte1 (Y) (2) CS (Y) (2) 04h (1) 04h (2) byte4 (Y) (1) 01h (1) 01h (2) byte4 (Y) (2) 41h (1) 41h (2) byte3 (Y) (1) 3FF (Y) (1) 3FF (Y) (2) byte3 (Y) (2) 3FF (Y) (1) 3FF (Y) (2) byte2 (Y) (1) 000 (Y) (1) 000 (Y) (2) byte2 (Y) (2) 3FF (C) (1) 3FF (Y) (1) 000 (C) (1) 000 (Y) (1) 000 (C) (1) 000 (Y) (1) XYZ (C) (1) XYZ (Y) (1) LN0 (C) (1) LN0 (Y) (1) LN1 (C) (1) LN1 (Y) (1) CCR0 (1) YCR0 (1) CCR1 (1) YCR1 (1) 3FF (C) (2) 3FF (Y) (2) 000 (C) (2) 000 (Y) (2) 000 (C) (2) 000 (Y) (2) XYZ (C) (2) XYZ (Y) (2) LN0 (C) (2) LN0 (Y) (2) LN1 (C) (2) LN1 (Y) (2) CCR0 (2) YCR0 (2) CCR1 (2) YCR1 (2) Other ANC data The VPID bytes, byte1, byte2, byte3 and byte4 are combined into one 32-bit word as {byte4, byte3, byte2, byte1} for input/output purposes. Thus vpid1_in, vpid2_in, vpid1_out and vpid2_out follow the same byte organization format given above. The line number for VPID insertion is determined by counting the line numbers from field transitions and using the video format from the input VPID bytes. On the receive side, the VPID bytes are extracted, if present, and given out through vpid1_out port (and vpid2_out port, if 3G-b video is received). If the ANC data packet is recognized as a VPID ANC packet based on DID and SDID matches, then vp1_valid is asserted high. If a valid VPID is available at the expected line numbers, vp1_lineok is asserted. If VPID is valid, then vp1_cserr and vp1_parerr indicate the occurrence of checksum and parity errors respectively. When receiving 3G-b video, the status and error signals for stream 2 video are given out through vp2_valid, vp2_lineok, vp2_cserr and vp2_parerr ports. Integer Frame-Rate Applications Figure 2-8 shows a typical IP configuration and its connection with the SERDES for integer frame rate transmission applications. The figure does not list all the signals and connections, only the essential ones. In this configuration, the SERDES is configured to use REFCLK for transmit reference clock and FPGA fabric clock for the receive reference clock. Only one clock source, 148.5 MHz, is required for the transmission and reception of all the three SDI rates. Multi-rate compatibility is achieved using the built-in clock dividers and multiplexers in the SERDES. IPUG82_01.5, December 2011 21 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description refclkp rxdata_ch0 rxdata refclkn rx_div11_mode_ch0 rx_hd_sdn rx_rate_mode_ch0 rx_tg_hdn fpga_rxrefclk_ch0 LatticeECP3 SERDES hdinp_ch0 hdinn_ch0 hdoutp_ch0 hdoutn_ch0 txdata_ch0 txdata tx_div2_mode_ch0 tx_div11_mode_ch0 txiclk_ch0 Rx Interface rx_clk tx_half_clk_ch0 pd_out Tri-Rate SDI Physical Layer IP Core SERDES Tx Interface 148.5 MHz Clock Source rx_half_clk_ch0 Tx Interface rxiclk_ch0 SERDES Rx Interface Figure 2-8. Tri-Rate IP Usage for Integer Frame Rate Applications pd_in hd_sdn_in pdi_clk tg_hdn_in As shown above, one 148.5 MHz clock source is sufficient for multi-rate transmission/reception as long as fractional frame rate HD/3G transmission is not required. Fractional Frame-Rate Applications In order to transmit fractional frame-rate HD or 3G simultaneously with SD transmission in the same SERDES quad, the low data rate (LDR) transmit path in the SERDES needs to be employed for SD transmission. Figure 2-9 shows this application scenario. As shown in the figure, a 27 MHz clock is required for this configuration in addition to the 148.35 MHz fractional frame rate reference clock. The control ldr_core2tx_en is driven by hd_sdn_in to switch the SERDES output between the SERDES serializer and the LDR data from the IP core. refclkn fpga_rxrefclk_ch0 hdinn_ch0 rxdata rx_div11_mode_ch0 rx_hd_sdn rx_div2_mode_ch0 rx_tg_hdn Tri-Rate SDI Physical Layer IP Core LatticeECP3 SERDES hdoutp_ch0 txd_ldr_ch0 txd_ldr hdoutn_ch0 txdata_ch0 txdata tx_div2_mode_ch0 ldr_core2tx_en tx_div11_mode_ch0 txiclk_ch0 tx_half_clk_ch0 27 MHz Clock Source SERDES Tx interface hdinp_ch0 rx_clk rxdata_ch0 clk27_in Rx Interface refclkp 148.35 MHz Clock Source rx_half_clk_ch0 Tx Interface rxiclk_ch0 SERDES Rx interface Figure 2-9. Tri-Rate IP Usage for Fractional Frame Rate Applications pd_out pdo_clk pd_in pd_in_sd hd_sdn_in pdi_clk tg_hdn_in IPUG82_01.5, December 2011 22 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Two sample designs provided with the IP core can be used to implement a complete SDI transmit/receive system on the LatticeECP3 Video Protocol Board. The designs are available in the user’s IP project directory after the TriRate SDI PHY IP is generated. A detailed explanation of the sample designs and their usage is provided in the TriRate SDI PHY IP Loopback and Passthrough Sample Designs User’s Guide available in the IP project directory. Timing Specifications The timing for the Tx data and controls for HD/3G-a is given in Figure 2-10. The Tx timing for 3G-b is shown in Figure 2-11. Figure 2-10. Tx Data and Controls for HD/3G-a pdi_clk Set LN at least 3 cycles before LN0 ln1_set ln1_in x ln x 3FF x x trs_in pd_in [19:10] 000 000 XYZ LN0 CR0 LN1 CR1 ANC0 3FF 000 Figure 2-11. Tx Data and Controls for 3G-b pdi_clk Set LN at least 3 cycles before LN0 ln1_set ln2_set ln1_in ln2_in x x ln trs_in pd_in [19:10] x 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CR0 CR0 For SD transmission, the trs_in signal is not used. For HD and 3G-a inputs, trs_in must coincide with the “3FF” data as shown in Figure 2-10. However, for 3G-b inputs, the trs_in should go high when the y-channel “3FF” (or the second “3FF”) occurs in the stream as shown in Figure 2-11. The line number for both cases must be set at least three cycles before the LN0 word is given at pd_in. Figure 2-12 shows the timing for the rate-select control signals for different transmit rates. IPUG82_01.5, December 2011 23 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Figure 2-12. Rate-select Control Signals for Different Transmit Rates trs_in (eav) (sav) lb_lan_in tg_hdn_in hd_sdn_in pd_in 3Ga data HD data SD data 3Gb data The timing diagram for the Rx side data and status signals for HD/3G-a is shown in Figure 2-13 and that for 3G-b is shown in Figure 2-14. The timing for the multi-rate receive operation is shown in Figure 2-15. Figure 2-13. Rx Data and Status Signals for HD/3G-a rx_clk rxdata [19:10] x 3FF 000 000 XYZ LN0 LN1 CR0 CR1 d1 d2 d3 XYZ LN0 LN1 CR0 CR1 d1 Output Latency pd_out [19:10] x 3FF 000 000 d2 trs_out field hblank vblank ln1_out ln2_out current line number previous line number y1_crc_error y1_crc_error IPUG82_01.5, December 2011 24 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Functional Description Figure 2-14. Rx Data and Status Signals for 3G-b rx_clk rxdata [19:10] 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CR0 CR0 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CR1 Output Latency pd_out [19:10] x 3FF 3FF 000 000 CR0 trs_out field hblank vblank ln1_out ln2_out previous line number current line number y1_crc_error y1_crc_error Figure 2-15. Control Signals for Rx-Side Rate Variations Rx input stream rx_hd_sdn, rx_tg_hdn 3G HD SD 3G pd_out HD SD 3G HD SD 3G SD 3G HD 3G HD 3G vid_active IPUG82_01.5, December 2011 25 Tri-Rate SDI PHY IP User’s Guide Chapter 3: Parameter Settings The IPexpress™ tool is used to create IP and architectural modules in the Diamond and ispLEVER software. Refer to “IP Core Generation” on page 32 for a description on how to generate the IP. Table 3-1 provides the list of user configurable parameters for the Tri-Rate SDI PHY IP core. The parameter settings are specified using the Tri-Rate SDI PHY IP core Configuration GUI in IPexpress. The numerous Tri-Rate SDI PHY IP core parameter options are partitioned across multiple GUI tabs as shown in this chapter. Table 3-1. Parameter Specifications for the Tri-Rate SDI PHY IP Core Parameters Range/Options Default Tx, Rx, Both Both Yes / No Yes PHY Settings PHY function Enable 3G Level-B LN insertion Off / On On CRC insertion Off / On On VPID insertion Off / On On LDR path for SD Yes / No No Include PLL for LDR Yes / No No 10-bit mode for SD Tx Yes / No Yes Separate data input for SD SD data width Yes / No No 8 bits, 10 bits, dynamic 8/10 bits 10 bits VPID extraction Off / On On 10-bit mode for SD Rx Yes / No Yes Yes / No No Yes / No No Optional Ports Clock enable port Custom Format Settings Custom format support for HD Custom format support for 3G Value or Range Yes / No No Value, Range Value EAV2SAV cycles- Value 200 to 8000 - EAV2SAV cycles- Minimum 200 to 8000 - EAV2SAV Cycles- Maximum 200 to 8000 - SAV2EAV Cycles- Value 200 to 6000 - SAV2EAV Cycles- Minimum 200 to 6000 - SAV2EAV Cycles- Maximum 200 to 6000 - 3G (HD/SD) Program time 1,10 3 Lock match threshold 1,10 3 Unlock error threshold 1,10 3 Advanced Settings IPUG82_01.5, December 2011 26 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Parameter Settings PHY Tab Figure 3-1 shows the contents of the PHY tab. Figure 3-1. PHY Tab PHY Function This parameter configures the IP core for Tx, Rx or both Tx and Rx functions. “Tx,” “Rx,” and “Both” parameters allow the user to specify receive-only, transmit-only, or both receive and transmit functions in the IP core. Even if both functions are available, the receive and transmit logic are independent of each other. The transmit and receive rates, however, may be limited by the reference clock and banding requirements imposed by the SERDES quad. Enable 3G Level-B 3G Level-B support is enabled if this box is checked. This parameter enables both reception and transmission of 3G Level-B video. If 3G-b support is not required, this option may be turned off to reduce the device utilization. The 3G Level-B parameter enables the removal of 3G-b support in the IP core when it is not required. Disabling 3G-b support in the IP results in reduced device utilization. Since the 3G-b video contains two independent HD streams, the Level-B option adds several I/O ports to support the second stream. These include ports for line number input, line number output, CRC error output, VPID input, VPID output and VPID status outputs. IPUG82_01.5, December 2011 27 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Parameter Settings LN Insertion This parameter determines whether line number is calculated and inserted in the Tx data. If LN insertion is selected, the core reads the raw line number value(s) from the input port(s), encodes to LN words and inserts them at appropriate locations. LN insertion is available for HD or 3G modes only. If it is required to insert line numbers in the format required by the SMPTE 292/424 standards, the IP core can be set to encode the raw line number information at the input ports to the two line number words in the stream. The values at ln1_in and ln2_in are read into registers whenever the signals ln1_set and ln2_set, respectively, are asserted high. The line number values at the registers are read in when the XYZ word is presented at pd_in, encoded and inserted after the XYZ word in the transmitted stream. If LN insertion is on and CRC insertion is off, it is the user’s responsibility to make sure the CRC check words take into account the encoded LN words also. CRC Insertion If this parameter is selected, the core computes the CRC values for the incoming line and inserts them at the appropriate places in the line. This is available for HD and 3G modes only. The parallel input data from the pd_in port is directly used word-by-word for transmission in most cases. If the input is HD or 3G, there is an option to have the IP core compute CRC for each input data line and insert that in appropriate places in the transmitted data stream. If the CRC Insertion option is disabled (off), then it is assumed that the incoming data comes with the appropriate CRC words in it. VPID Insertion This control selects whether VPID is inserted by the IP. If VPID insertion is enabled, an input port vpid1_in is available (if 3G-b support is also enabled, a second input port vpid2_in is provided) for reading in the VPID bytes. The VPID bytes read from the input port are formatted with other standard words and inserted at appropriate places in the input video stream depending on the format of the input (as determined from the input VPID bytes). VPID insertion is available for HD and 3G modes only. The VPID insertion option enables automatic insertion of the video payload identifier to the video stream according to SMPTE 352M specifications. The IP converts the raw VPID bytes from the user to a 352M ANC payload by adding ancillary data flag (ADF), data identifier (DID), secondary data identifier (SDID), parity to each of the VPID bytes and the checksum word. The IP also determines the interface line number of the input video line by monitoring the XYZ words. The VPID payload is inserted in line number 10 (and line number 572 for interlaced transports) after the last CRC word in the y-channel of each stream. The IP uses the video format information contained in the VPID bytes to determine the interface line number. LDR Path for SD This control specifies whether an LDR (low data rate) path is included for SD transmission. An LDR path is required to dynamically support SD and fractional frame rate HD/3G transmission in the same quad. If LDR is enabled, a serializer and some associated logic are included in the IP core to support the SD transmission. Include PLL for LDR This control determines if a PLL needs to be included inside the IP to perform the 10x multiplication of the 27 MHz clock for LDR transmit path. If this is not selected, but the LDR option is selected, an additional input port is provided for the user to supply a 270 MHz clock. This option permits the use of PLL in only one of the IP instances, when multiple IP instances are used. 10-bit Mode for SD Tx This parameter specifies support for 10-bit/27 MHz SD input mode and allows the IP to accept SD parallel input data at 10 bits/27 MHz. IPUG82_01.5, December 2011 28 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Parameter Settings Separate Data Input for SD This parameter provides a separate input port for SD data. If this option is not selected, the SD input is read in from the lower 10 bits of the common input data bus, pd_in. This option is available only if the LDR path for SD is selected. SD Data Width This parameter configures the user data width for SD standard video. If this is 10 bits, the data is directly used. If this is 8 bits, the user data drives the most significant 8 bits of the internal data bus and the least significant 2 bits are filled by the IP with zeros, except when the input 8 bits are all ones, when they are filled with ones. If configured as dynamic, the 8 bit or 10 bit mode is decided by the input signal sd8b_mode. VPID Extraction If this parameter is enabled, the IP extracts the video payload identifier (VPID) from the received video stream. The VPID bytes as well as some status/error signals are given out independently for each video link. 10-bit Mode for SD Rx This parameter enables the IP to provide SD parallel output data at 10 bits/27 MHz. Clock Enable Port This parameter configures if a clock enable port is required in the IP core. This option must be selected only if required, as the clock enable port increases the resource utilization of the IP core. Custom Format Tab Figure 3-2 shows the contents of the Custom Format tab. IPUG82_01.5, December 2011 29 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Parameter Settings Figure 3-2. Custom Format Tab Custom Format Support for HD This parameter enables custom HD format detection by the IP. If custom format detection is required, additional parameters need to be set. Custom format is detected by accommodating user-defined ranges for the number of words (gap) between SAV and EAV and between EAV and SAV. Custom Format Support for 3G This parameter enables custom 3G format detection by the IP. If custom format detection is required, additional parameters need to be set. Custom format is detected by accommodating user-defined ranges for the number of words between SAV and EAV and between EAV and SAV. Value or Range This control specifies how the SAV to EAV and EAV to SAV gaps are specified. The IP accepts specific values as well as a range for these gap parameters. EAV2SAV cycles- Value This is the value for the gap between the EAV and the SAV. The value is computed as: Words/total line – Words/active line - 5 for HD 2*(Words/total line – Words/active line) - 5 for 3G-a 2*(Words/total line – Words/active line) – 9 for 3G-b IPUG82_01.5, December 2011 30 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Parameter Settings EAV2SAV Cycles- Minimum When the custom format parameter is set to “Range”, this parameter specifies the minimum value for the EAV2SAV cycles range. EAV2SAV Cycles- Maximum When the custom format parameter is set to “Range”, this parameter specifies the maximum value for the EAV2SAV cycles range. SAV2EAV Cycles- Value This is the value for the gap between the SAV and the EAV. The value is computed as: Words/active line + 3 for HD 2*(Words/active line) + 3 for 3G-a 2*(Words/active line) + 7 for 3G-b SAV2EAV Cycles- Minimum When the custom format parameter is set to “Range”, this parameter specifies the minimum value for the SAV2EAV cycles range. SAV2EAV Cycles- Maximum When the custom format parameter is set to “Range”, this parameter specifies the maximum value for the SAV2EAV cycles range. Advanced Tab Figure 3-3 shows the contents of the Advanced tab. Figure 3-3. Advanced Tab 3G/HD/SDProgram Time Programming time for 3G/HD/SD. This parameter defines how long to wait for the SERDES to be programmed after the Rx scan rate is changed. The duration is specified by a number which is approximately equal to the number of total words in a line. Lock Match Threshold This parameter specifies the number of TRS matches necessary for the receiver to be locked to the video. Unlock Error Threshold This parameter specifies the number of TRS errors to tolerate before the receiver switches to the unlocked state or to scan for the next rate. IPUG82_01.5, December 2011 31 Tri-Rate SDI PHY IP User’s Guide Chapter 4: IP Core Generation This chapter provides information on how to generate the Tri-Rate SDI PHY IP core using the Diamond or ispLEVER software IPexpress tool, and how to include the core in a top-level design. The Tri-Rate SDI PHY IP core can be used in LatticeECP3 device families. For information and known issues on this core, see the Lattice Tri-Rate SDI PHY IP Readme document. This file is available once the core is installed in Diamond or ispLEVER. The document provides information on creating an evaluation version of the core for use in Diamond or ispLEVER and simulation. Licensing the IP Core An IP core- and device-specific license is required to enable full, unrestricted use of the Tri-Rate SDI PHY IP core in a complete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at: http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm Users may download and generate the Tri-Rate SDI PHY IP core and fully evaluate the core through functional simulation and implementation (synthesis, map, place and route) without an IP license. The Tri-Rate SDI PHY IP core also supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited time (approximately four hours) without requiring an IP license. See “Hardware Evaluation” on page 38 for further details. However, a license is required to enable timing simulation, to open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout limitation. Getting Started The Tri-Rate SDI PHY IP core is available for download from the Lattice IP Server using the IPexpress tool in Diamond or ispLEVER. The IP files are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP core has been installed, it will be available in the IPexpress GUI dialog box shown in Figure 41. The IPexpress tool GUI dialog box for the Tri-Rate SDI PHY IP core is shown in Figure 4-1. To generate a specific IP core configuration the user specifies: • Project Path – Path to the directory where the generated IP files will be loaded. • File Name – “username” designation given to the generated IP core and corresponding folders and files. • (Diamond) Module Output – Verilog or VHDL. • (ispLEVER) Design Entry Type – Verilog HDL or VHDL • Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3, etc.). Only families that support the particular IP core are listed. • Part Name – Specific targeted part within the selected device family. IPUG82_01.5, December 2011 32 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation Figure 4-1. IPexpress Dialog Box (Diamond Version) Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. To generate an IP configuration, the user clicks the Customize button in the IPexpress tool dialog box to display the Tri-Rate SDI PHY IP core Configuration GUI, as shown in Figure 4-2. From this dialog box, the user can select the IP parameter options specific to their application. Refer to “Parameter Settings” on page 26 for more information on the Tri-Rate SDI PHY IP core parameter settings. IPUG82_01.5, December 2011 33 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation Figure 4-2. Configuration Dialog Box (Diamond Version) IPUG82_01.5, December 2011 34 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation IPexpress-Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3. Figure 4-3. LatticeECP3 Tri-Rate SDI PHY Core Directory Structure IPUG82_01.5, December 2011 35 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation Table 4-1 provides a list of key files and directories created by the IPexpress tool and how they are used. The IPexpress tool creates several files that are used throughout the design cycle. The names of most of the created files are customized to the user’s module name specified in the IPexpress tool. Table 4-1. File List File Description _inst.v This file provides an instance template for the IP. _beh.v This file provides the front-end simulation library for the Tri-Rate SDI PHY IP core. sdi_params.v This file provides the user options of the IP for the simulation model. _bb.v This file provides the synthesis black box for the user’s synthesis. .ngo This file provides the synthesized IP core. ecp3pcs.txt This file contains the PCS/SERDES memory map initialization. This file must be copied in to the simulation directory as well as the software project directory. .lpc This file contains the IPexpress tool and Tri-Rate SDI PHY IP GUI options used to recreate or modify the core in the IPexpress tool. .ipx The IPX file holds references to all of the elements of an IP or Module after it is generated from the IPexpress tool (Diamond version only). The file is used to bring in the appropriate files during the design implementation and analysis. It is also used to re-load parameter settings into the IP/Module generation GUI when an IP/Module is being re-generated. pmi_*.ngo These files contain the embedded block RAMs (EBRs) used by the IP core. These files need to be pointed to by the Build step by using the search path property. Most of the files required to use the Tri-Rate SDI PHY IP core in a user’s design reside in the root directory created by the IPexpress tool. This includes the synthesis black box, simulation model, and post synthesis NGO files for the PMI modules. The \sdi_eval and subtending directories provide files supporting Tri-Rate SDI PHY IP core evaluation. The \sdi_eval directory contains files/folders with content that is constant for all configurations of the Tri-Rate SDI PHY IP core. The \ subfolder (\sdi_phy_eval0 in this example) contains files/folders with content specific to the configuration. The Tri-Rate SDI PHY ReadMe document is also provided in the \sdi_eval directory. For example information and known issues on this core, see the Lattice Tri-Rate SDI PHY ReadMe document. This file is available when the core is installed. The document provides information on creating an evaluation version of the core for use in Diamond or ispLEVER and simulation. The \sdi_eval directory provides an evaluation design which can be used to determine the size of the IP core and a design which can be pushed through the Diamond or ispLEVER software including front-end and timing simulations. The models directory provides the library element for the PCS and PLLs. The \ directory contains top-level design for the configuration specified by the customer. The  \\impl directory provides project files supporting Precision RTL and Synplify synthesis flows. The sample top-level design pulls the user ports out to external pins. This design and associated project files can be used to determine the size of the core and to push it through the mechanics of the Diamond or ispLEVER software design flow. The \\sim directory provides project files supporting RTL and timing simulation for both the ActiveHDL and ModelSim simulators. The \\src directory provides the top-level source code for the eval design. The \testbench directory provides a top-level testbench file. IPUG82_01.5, December 2011 36 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation Running Functional Simulation Simulation support for the Tri-Rate SDI PHY IP core is provided for Aldec and ModelSim simulators. The Tri-Rate SDI PHY IP core simulation model is generated from the IPexpress tool with the name _beh.v. This file is an obfuscated simulation model. An obfuscated simulation model is Lattice’s unique IP protection technique which scrambles the Verilog HDL while maintaining logical equivalence. VHDL users will use the same Verilog model for simulation. When compiling the Tri-Rate SDI PHY IP core, the file, sdi_params.v must be compiled with the model. This files provides “define constants” that are necessary for the simulation model. The ModelSim environment is located in \\sdi_eval\\sim\modelsim. Users can run the ModelSim simulation by performing the following steps: 1. Open ModelSim. 2. Under the File tab, select Change Directory and choose folder  \\sdi_eval\\sim\modelsim\scripts. 3. Under the Tools tab, select Tcl > Execute Macro and execute one of the ModelSim “do” scripts shown, depending on whether RTL or netlist simulation is required. The Aldec Active-HDL environment is located in \\sdi_eval\\sim\aldec. Users can run the Aldec evaluation simulation by performing the following steps: 1. Open Active-HDL. 2. Under the Tools tab, select Execute Macro. 3. Browse to the directory \\sdi_eval\\sim\aldec\scripts and execute one of the Active-HDL “do” scripts shown. Synthesizing and Implementing the Core in a Top-Level Design The Tri-Rate SDI PHY IP core itself is synthesized and provided in NGO format when the core is generated through the IPexpress tool. You can combine the core in your own top-level design by instantiating the core in your top level file and then synthesizing the entire design with either Synplify or Precision RTL Synthesis. The top-level file _top.v provided in \\sdi_eval\\src\rtl\top\ supports the ability to implement the Tri-Rate SDI PHY IP core in isolation. Push-button implementation of this toplevel design with either Synplify or Precision RTL Synthesis is supported via the Diamond or ispLEVER software project files _top.syn located in the  \\sdi_eval\\impl\synplify\core_only and the \\sdi_eval\\impl\precision\core_only directories, respectively. To use the project file in Diamond: 1. Choose File > Open > Project. 2. Browse to  \\sdi_eval\\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open .ldf. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project. 4. Select the Process tab in the left-hand GUI window. IPUG82_01.5, December 2011 37 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation 5. Implement the complete design via the standard Diamond GUI flow. To use the project file in ispLEVER: 1. Choose File > Open Project. 2. Browse to  \\sdi_eval\\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open .syn. At this point, all of the files needed to support top-level synthesis and implementation will be imported to the project. 4. Select the device top-level entry in the left-hand GUI window. 5. Implement the complete design via the standard ispLEVER GUI flow. Hardware Evaluation The Tri-Rate SDI PHY IP core supports supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in userdefined designs. Enabling Hardware Evaluation in Diamond Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be enabled/disabled in the Strategy dialog box. It is enabled by default. Enabling Hardware Evaluation in ispLEVER In the Processes for Current Source pane, right-click the Build Database process and choose Properties from the dropdown menu. The hardware evaluation capability may be enabled/disabled in the Properties dialog box. It is enabled by default. Updating/Regenerating the IP Core By regenerating an IP core with the IPexpress tool, you can modify any of its settings including device type, design entry method, and any of the options specific to the IP core. Regenerating can be done to modify an existing IP core or to create a new but similar one. Regenerating an IP Core in Diamond To regenerate an IP core in Diamond: 1. In IPexpress, click the Regenerate button. 2. In the Regenerate view of IPexpress, choose the IPX source file of the module or IP you wish to regenerate. 3. IPexpress shows the current settings for the module or IP in the Source box. Make your new settings in the Target box. 4. If you want to generate a new set of files in a new location, set the new location in the IPX Target File box. The base of the file name will be the base of all the new file names. The IPX Target File must end with an .ipx extension. 5. Click Regenerate. The module’s dialog box opens showing the current option settings. 6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the About tab in IPexpress for links to technical notes and user guides. IP may come with additional information. As IPUG82_01.5, December 2011 38 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor IP Core Generation the options change, the schematic diagram of the module changes to show the I/O and the device resources the module will need. 7. To import the module into your project, if it’s not already there, select Import IPX to Diamond Project (not available in stand-alone mode). 8. Click Generate. 9. Check the Generate Log tab to check for warnings and error messages. 10.Click Close. The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP core required to support simulation, synthesis and implementation. The IP core may be included in a user's design by importing the .ipx file to the associated Diamond project. To change the option settings of a module or IP that is already in a design project, double-click the module’s .ipx file in the File List view. This opens IPexpress and the module’s dialog box showing the current option settings. Then go to step 6 above. Regenerating an IP Core in ispLEVER To regenerate an IP core in ispLEVER: 1. In the IPexpress tool, choose Tools > Regenerate IP/Module. 2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. 4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc extension. 5. Click Next. The IP core’s dialog box opens showing the current option settings. 6. In the dialog box, choose desired options. To get information about the options, click Help. Also, check the About tab in the IPexpress tool for links to technical notes and user guides. The IP core might come with additional information. As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG82_01.5, December 2011 39 Tri-Rate SDI PHY IP User’s Guide Chapter 5: Application Support This chapter provides application support information for the Tri-Rate SDI PHY IP core. Tri-Rate SDI PHY IP Loopback and Passthrough Sample Designs When the Tri-Rate SDI PHY IP core is generated using IPexpress, two sample top-level designs are created. The designs, named “loopback” and “passthrough”, are created under  /sdi_eval/impl//loopback  and /sdi_eval/impl//passthru respectively. Further information about these two designs is given in the following sections. The designs can be implemented directly on the LatticeECP3 Video Protocol Board (VPB) if the IP was created using the default parameters in the IP GUI. The LatticeECP3 VPB has the LFE3-95E-7FN1156CES device on it. If one or more parameters are changed in the IP GUI, the sample designs can still be used, but may require some changes depending on the parameters used to configure the IP. Loopback Design The loopback design is meant to test the transmit (Tx) and receive (Rx) logic of the IP without the help of an external SDI source or sink. The design includes the Lattice video pattern generator module in FPGA logic, LatticeECP3 SERDES PCS and a character LCD display interface in addition to the IP. The loopback scheme is shown in Figure 5-1. Figure 5-1. The Loopback Scheme LCD display Optional Waveform Generator rxdata TG 700, etc connect for loopback Tri-Rate SDI PHY IP LatticeECP3 SERDES Optional Waveform Monitor WFM 7100, 7120, etc txdata Lattice Video Pattern Generator LatticeECP3 FPGA A waveform monitor and/or a waveform generator can be optionally used instead of the loopback cable to monitor and/or source the SDI video. All the transmit functions and most of the receive functions of the IP can be tested with the loopback setup. One major output that is not tested using a loopback cable connection is the actual parallel received data and its relative timing to other status outputs. The passthrough design can be used to test the received video data. The loopback design is designed for and tested on the VPB that includes the LatticeECP3-95E-7, 1156-ball fpBGA package, commercial grade silicon. A detailed block diagram of the loopback design is shown in Figure 5-2. IPUG82_01.5, December 2011 40 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Figure 5-2. Block Diagram of the Loopback Design LCD display 27 MHz OSC vid_active vid_format frame_format rx_half_clk_ch0 rxiclk_ch1 148.5 MHz fpga_rxrefclk_ch0 PLL Equalizer rxdata_ch1 rx_clk rxdata DIP switches hdinp_ch0 hdinn_ch0 connect for loopback hdoutp_ch0 hdoutn_ch0 148.5 MHz Tx 4915 refclkp refclkn txdata_ch0 txdata pd_in pdi_clk txiclk_ch0 tx_half_clk tx_full_clk_ch0 tx_half_clk_ch0 PLL hd_sdn_in tg_hdn_in lb_lan_in patho_cbn cb_patho_type pg_std_num Tri-Rate SDI PHY IP LatticeECP3 SERDES Driver LCD Interface Lattice Video Pattern Generator tx_half_clk 27 MHz XTL tx_full_clk LatticeECP3 FPGA hd_sdn_in Passthrough Design The passthrough design is set up to receive video from a standard SDI source and re-transmit it through the IP to a SDI monitor. This design does not use a pattern generator in the FPGA. The passthrough scheme is shown in Figure 5-3. Figure 5-3. Passthrough Scheme LCD display Waveform Generator rxdata TG 700, etc. Tri-Rate SDI PHY IP LatticeECP3 SERDES FIFO Waveform Monitor WFM 7100, 7120, etc txdata LatticeECP3 FPGA IPUG82_01.5, December 2011 41 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support As shown in Figure 5-3, the output data from the receiver is fed to the transmitter through a FIFO. Another major change in passthrough design from the loopback design is the Tx clocking scheme. Since the transmit rate must exactly match the receive rate, the passthrough design uses the recovered clock from the SERDES receiver to clock the transmit logic. A detailed block diagram of the passthrough design is shown in Figure 5-4. As shown in the figure, the recovered clock is cleaned up using a GS 4915 clock cleaner and used as the transmit reference clock. Figure 5-4. Block Diagram of the Passthrough Design LCD display hd_sdn_in = rx_hd_sdn tg_hdn_in = rx_tg_hdn rx_hd_sdn rx_half_clk_ch0 rxiclk_ch1 PLL rx_clk vid_active vid_format frame_format LCD Interface rx_full_clk_ch0 rxdata SDI source Rx 4915 PLL SDI Monitor Equalizer hdinp_ch0 hdinn_ch0 rxdata_ch1 pd_out pdo_clk fpga_rxrefclk_ch0 LatticeECP3 SERDES 148.5 MHz Tri-Rate SDI PHY IP 27 MHz XTL Driver Tx 4915 148.5 MHz hdoutp_ch0 hdoutn_ch0 refclkp refclkn FIFO pd_in txdata_ch0 txdata pdi_clk txiclk_ch0 tx_full_clk_ch0 tx_half_clk_ch0 tx_half_clk LatticeECP3 FPGA tx_half_clk tx_full_clk hd_sdn_in Simulating the Sample Design The IP project directory contains the simulation environment to run loopback testing of the IP. The environment includes the testbench, test configuration file and simulation script file. The testbench instantiates the loopback sample design with an additional pattern checker that is enabled for simulation. To simulate the design using the Aldec ActiveHDL simulator: 1. Open Aldec ActiveHDL. 2. From the menu, select Tools -> Execute Macro. 3. Browse to /sdi_eval//sim/aldec/scripts/_rtl.do. 4. This will start the compilation and simulation. After several minutes, the simulation will end with the test status. A simulation script is also provided for the ModelSim simulator. IPUG82_01.5, December 2011 42 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Testbench and Configuration File The testbench instantiates and tests the demo design that includes the SDI IP, Lattice video pattern generator and a data checker. The testbench applies a number of different video streams, each spanning a certain number of lines. The total number of video streams to be applied and the rate, standard and number of lines for each video stream are read from the configuration file sdi_config.mem. This configuration file can be edited to change the test patterns or their duration. A sample configuration file with comments is shown below. Sample sdi_config.mem File (All entries are in binary) 00000110 101 00111 000000000100 011 01111 000000000100 001 01100 000000000100 111 01110 000000000100 000 01010 000000000100 011 00010 000000000100 - Number of video streams to be applied (=6) - Rate: 000-SD, 001-HD, 011-3Ga, 101-3Gb-DS, 111-3Gb-DL - Video Pattern number (refer to Table 1) - Number of lines of video to apply after lock | | Data for video stream 2 | | | | Data for video stream 4 The Lattice video pattern generator module provided with the IP can generate different types of color bar and pathological patterns. The pattern numbers for different video formats and rates are given in Table 5-1. Table 5-1. Pattern Generator Standards tg_hdn_in hd_sdn_in pg_std_num pg_std_num (Decimal) vid_format frame_format Content 0 0 0 xxxx0 0 1440 x 486 60i 4:2:2 0 0 0 xxxx1 1 1440 x 576 50i 4:2:2 0 0 1 x0000 0 1920 x 1035 60i 4:2:2 0 0 1 x0001 1 1920 x 1080 50i, 295M 4:2:2 0 0 1 x0010 2 1920 x 1080 30p 4:2:2 0 0 1 x0011 3 1920 x 1080 60i 4:2:2 0 0 1 x0100 4 1920 x 1080 25p 4:2:2 0 0 1 x0101 5 1920 x 1080 50i 4:2:2 0 0 1 x0110 6 1920 x 1080 24p 4:2:2 0 0 1 x0111 7 1280 x 720 60p 4:2:2 0 0 1 x1000 8 2048x1080 24p 4:2:2 1 1 00000 0 1920 x 1080 60p 4:2:2 lb_lan_in SD HD 3G-A 0 IPUG82_01.5, December 2011 43 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Table 5-1. Pattern Generator Standards (Continued) lb_lan_in tg_hdn_in hd_sdn_in pg_std_num pg_std_num (Decimal) vid_format frame_format Content 0 1 1 00001 1 1920 x 1080 50p 4:2:2 0 1 1 00010 2 1280 x 720 60p 4:4:4:4 0 1 1 00011 3 1280 x 720 50p 4:4:4:4 0 1 1 00100 4 1920 x 1080 30p 4:4:4:4 0 1 1 00101 5 1280 x 720 30p 4:4:4:4 0 1 1 00110 6 1920 x 1080 25p 4:4:4:4 0 1 1 00111 7 1280 x 720 25p 4:4:4:4 0 1 1 01000 8 1920 x 1080 24p 4:4:4:4 0 1 1 01001 9 1280 x 720 24p 4:4:4:4 0 1 1 01010 10 1920 x 1080 60i 4:4:4:4 0 1 1 01011 11 1920 x 1080 50i 4:4:4:4 0 1 1 01100 12 1920 x 1080 30p 4:4:4, 12 bits 0 1 1 01101 13 1920 x 1080 25p 4:4:4, 12 bits 0 1 1 01110 14 1920 x 1080 24p 4:4:4, 12 bits 0 1 1 01111 15 1920 x 1080 60i 4:4:4, 12 bits 0 1 1 10000 16 1920 x 1080 50i 4:4:4, 12 bits 0 1 1 10001 17 1920 x 1080 30p 4:2:2, 12 bits 0 1 1 10010 18 1920 x 1080 25p 4:2:2, 12 bits 0 1 1 10011 19 1920 x 1080 24p 4:2:2, 12 bits 0 1 1 10100 20 1920 x 1080 60i 4:2:2, 12 bits 0 1 1 10101 21 1920 x 1080 50i 4:2:2, 12 bits 0 1 1 11000 24 2048 x 1080 30p 4:4:4, 12 bits 0 1 1 11001 25 2048 x 1080 25p 4:4:4, 12 bits 0 1 1 11010 26 2048 x 1080 24p 4:4:4, 12 bits 0 1 1 11011 27 2048 x 1080 30p 4:4:4:4, 10 bits 0 1 1 11100 28 2048 x 1080 25p 4:4:4:4, 10 bits 0 1 1 11101 29 2048 x 1080 24p 4:4:4:4, 10 bits 3G-B-Dual Stream 1 0 1 xx000 0 1920 x 1035 60i 4:2:2 1 0 1 xx001 1 1920 x 1080 50i (295) 4:2:2 1 0 1 xx010 2 1920 x 1080 30p 4:2:2 1 0 1 xx011 3 1920 x 1080 60i 4:2:2 1 0 1 xx100 4 1920 x 1080 25p 4:2:2 1 0 1 xx101 5 1920 x 1080 50i 4:2:2 1 0 1 xx110 6 1920 x 1080 24p 4:2:2 1 0 1 xx111 7 1280 x 720 60p 4:2:2 1 1 1 00000 0 1920 x 1080 60p 4:2:2 1 1 1 00001 1 1920 x 1080 50p 4:2:2 1 1 1 00100 4 1920 x 1080 30p 4:4:4:4 1 1 1 00110 6 1920 x 1080 25p 4:4:4:4 1 1 1 01000 8 1920 x 1080 24p 4:4:4:4 1 1 1 01010 10 1920 x 1080 60i 4:4:4:4 3G-B-Dual Link IPUG82_01.5, December 2011 44 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Table 5-1. Pattern Generator Standards (Continued) lb_lan_in tg_hdn_in hd_sdn_in pg_std_num pg_std_num (Decimal) vid_format frame_format Content 1 1 1 01011 11 1920 x 1080 50i 4:4:4:4 1 1 1 01100 12 1920 x 1080 30p 4:4:4, 12 bits 1 1 1 01101 13 1920 x 1080 25p 4:4:4, 12 bits 1 1 1 01110 14 1920 x 1080 24p 4:4:4, 12 bits 1 1 1 01111 15 1920 x 1080 60i 4:4:4, 12 bits 1 1 1 10000 16 1920 x 1080 50i 4:4:4, 12 bits 1 1 1 10001 17 1920 x 1080 30p 4:2:2:4, 12 bits 1 1 1 10010 18 1920 x 1080 25p 4:2:2:4, 12 bits 1 1 1 10011 19 1920 x 1080 24p 4:2:2:4, 12 bits 1 1 1 10100 20 1920 x 1080 60i 4:2:2:4, 12 bits 1 1 1 10101 21 1920 x 1080 50i 4:2:2:4, 12 bits Only the integer frame rates (24p, 30p, 60i and 60p) are shown in Table 5-1, but the corresponding fractional frame rates (23.98p, 29.97p, 59.94i and 59.94p) can be generated by using the fractional clocks (74.175 MHz and 148.35 MHz). Implementing and Testing the Sample Design The sample designs can be implemented by simply opening the provided Diamond or ispLEVER project files. • In Diamond, check Bitstream File under Export Files in the Process tab. Then, right-click Bitstream File and choose Run. • In ispLEVER, run the Generate Bitstream Data process in the Project Navigator. The VPB requires that both the LatticeECP3 and MachXO devices on it be programmed for proper operation. The MachXO controls several peripheral devices on the board, including the clock generator and clock cleaner chip sets. The MachXO source, constraint and project files for the loopback and passthrough configurations are created under /sdi_eval//impl//MachXO. Open the MachXO project by double-clicking on the project file and create the bitstream by following the usual process. Board Switch Assignments for Sample Designs Both the loopback and the passthrough sample designs use the following reset buttons: • Pushbutton switch SW10 – Master reset (both logic and SERDES reset). Depress the switch momentarily for reset. • Pushbutton switch SW9 – SERDES Rx reset. Depress the switch momentarily for reset. The loopback design uses the DIP switches shown in Table 5-2. The switches have a “0” value when pushed toward the bottom of the board (toward the PCI Express fingers). They take on a “1” value when pushed toward the top of the board (toward the channel link connector). Table 5-2. Switch Connections on the VPB Switch Name SW1-1 hd_sdn_in SW1-2 tg_hdn_in SW1-3 lb_lan_in SW1-4 txd_ldr_en IPUG82_01.5, December 2011 Description Pattern generator transmit rate {lb_lan_in, tg_hdn_in, hd_sdn_in} 000- SD, 001- HD, 011- 3Ga, 101- 3Gb-DS, 111- 3Gb-DL Selects the LDR path for the SERDES output when the transmitted rate is SD. The switch has no effect when transmitting 3G or HD rates. 0 - Selects SERDES path, 1 - Selects LDR path. 45 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Table 5-2. Switch Connections on the VPB (Continued) Switch Name Description SW3-1 SW3-2 SW3-3 Standard number = {SW4-1,SW3-4,SW3-3,SW3-2,SW3-1}. See Table 5-1 for the format. Video Standard SW3-4 SW4-1 Color bar or pathological pattern type {SW4-3,SW4-2}. SW4-2 patho_cb_type SW4-3 When “patho_cbn”=0 When “patho_cbn”=1 00 – 100% color bar 00 – SDI checkfield 01 – 75% color bar 01 – Equalizer pattern 1x – SMPTE color bar 10 – PLL pattern 11 – Undefined SW4-4 patho_cbn Pathological or color bar. 0 – Color bar, 1 – Pathological. Note that the pattern generator interprets the lb_lan_in, tg_hdn_in and hd_sdn_in values differently from the IP. The values shown in Table 5-1 and Table 5-2 are for the pattern generator. For example, the pattern generator differentiates 3G Level-B-DS and 3G Level-B-DL using the values 101 and 111 for {lb_lan_in, tg_hdn_in, hd_sdn_in} whereas the IP identifies all 3G Level-B streams with the value 111. Transmitter Testing Connect the transmitter output BNC connector labeled “SDI Tx #0” to an SDI monitor. Set the DIP switches according to the rate and pattern to be transmitted. The selected pattern is displayed in the monitor. Receiver Testing Connect an SDI source to the receiver input-BNC connector, labeled “SDI Rx #1”. The received rate and standard are displayed on the character LCD display. If the LCD display unit is not connected, the status can also be read from the LEDs. The LEDs also display the SERDES and CRC error status. Note that the 3G Level-B identified by the IP and displayed in the LCD is based on the format for stream 1 of the 3G video. The LED status (0 is off, 1 is lit) is shown in Table 5-3. Table 5-3. LED Status Display LED Color Name D10 Blue rx_los_ch1 Rx loss of signal (LOS): 0 – No LOS error, 1 – LOS error Description D11 Green rx_lol_ch1 Rx loss of lock: 0 – Rx CDR is locked, 1 – Rx CDR loss of lock error D12 Orange crc_error CRC error detected. 0 – No CRC error, 1 – CRC error D13 Red pll_lol D14 Blue rx_hd_sdn D15 Green rx_tg_hdn Receiver’s 3G/HD rate status: 0 – Not 3G, 1 – 3G. D16 Orange D17 Red vid_format Detected video format output: {D17,D16} 00 – 1440x486/576 01 – 1280x720 10 – 1920x1035 11 – 1920x1080 IPUG82_01.5, December 2011 SERDES transmit PLL loss of lock: 0 – PLL locked, 1 – PLL unlocked. Receiver’s HD/SD rate status: 0 – SD, 1 – HD. 46 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Application Support Table 5-3. LED Status Display LED Color D22 Blue D23 Green Name frame_format D24 Orange D26 Red vid_active Description Detected frame format output: {D24,D23,D22} 000 – Reserved 001 – 24p or 23.98p or 23.98 psF 010 – 25p 011 – 30p or 29.97p 100 – 50i 101 – 60i or 59.94i 110 – 50p 111 – 60p or 59.94p Video active output: 0 – Receiver not locked to any video,1 – Locked to video. LCD Display There are four display pages in the LCD display as shown in Table 5-4. Table 5-4. Display Pages Line 1 Page 0 Page 1 Page 2 Page 3 Tx Rate/Format TX VPID Rx VPID Rx PCT Line 2 Rx Rate/Format The display for each of the pages is formatted as given below. Tx or Rx Rate/Format T –> 3Ga 1080 60i R –> 3Gb 1080 59.9p TX or RX VPID T –> VP R –> VP Rx PCT (Rx Placer error, Crc error, Time) PCT –> < crc_error> Placer error is either a SAV error or an EAV error. Time is the time elapsed since reset (pushbutton SW8). Use pushbutton switch SW7 to cycle the LCD display through pages. Use pushbutton switch SW8 to reset the errors and time. Loopback Testing Connect the transmitter output labeled “SDI Tx #0” to the receiver input labeled “SDI Rx #1”. Change the switches to generate different rates and formats and verify the reception at the LCD display. You can also remove the loopback cable and connect the output to a SDI monitor and feed the input from a SDI generator. Note that the Tx and Rx rates and formats are not related to each other and can be selected independently. Passthrough Testing Connect a SDI Generator to the input labeled “SDI Rx #1” and a SDI Monitor to the output labeled “SDI Tx #0”. Set the desired rate and pattern in the signal generator and see the same video passed through to the output. The DIP switches are not read in the passthrough mode. IPUG82_01.5, December 2011 47 Tri-Rate SDI PHY IP User’s Guide Chapter 6: Core Verification The functionality of the Lattice Tri-Rate SDI PHY IP core has been verified via simulation and hardware testing in a variety of environments, including: • Simulation environment verifying Tri-Rate SDI PHY functionality using Lattice video pattern generator. • Hardware testing of the simulation environment in loopback mode, with a cable providing the loopback of serial transmit out to serial receive in. The video stream was generated using the internal video pattern generator and the status of the received video was displayed on the LCD display. • Hardware testing in passthrough mode where an external video source was used for transmission. The sample design received the video stream using the IP receiver and re-transmitted it through the IP transmitter. IPUG82_01.5, December 2011 48 Tri-Rate SDI PHY IP User’s Guide Chapter 7: Support Resources This chapter contains information about Lattice Technical Support, additional references, and document revision history. Lattice Technical Support There are a number of ways to receive technical support. Online Forums The first place to look is Lattice Forums (http://www.latticesemi.com/support/forums.cfm). Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers. Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a.m. to 6 p.m. Pacific Time. • For USA & Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • techsupport@latticesemi.com • techsupport-asia@latticesemi.com Local Support Contact your nearest Lattice Sales Office. Internet www.latticesemi.com References Lattice Tri-Rate SDI PHY IP Website Information on the Lattice Tri-Rate SDI PHY IP can be found at: http://www.latticesemi.com/products/intellectualproperty/ipcores/triratesdiphy.cfm SMTPE Website The Society of Motion Picture and Television Engineers (SMPTE) website contains specifications and documents referred to in this user's guide. The SMPTE URL is: http://www.smpte.org 1. SMPTE 259M-2006 - SDTV Digital Signal/Data- Serial Digital Interface 2. SMPTE 292M-1998 Television - Bit-Serial Digital Interface for high-Definition Television Systems IPUG82_01.5, December 2011 49 Tri-Rate SDI PHY IP User’s Guide Lattice Semiconductor Support Resources 3. SMPTE 424M-2006 Television - 3 Gbps Signal/Data Serial Interface 4. SMPTE 125M-1995 Television - Component Video Signal 4:2:2- Bit-Parallel Digital Interface 5. ANSI/SMPTE 267M-1995 Television - Bit-Parallel Digital Interface- Component Video Signal 4:2:2 16x9 Aspect Ratio 6. SMPTE 260M-1999 Television - 1125/60 High-Definition Production System- Digital Representation and BitParallel Interface 7. SMPTE 274M-2003 Television - 1920 x 1080 Image Sample Structure, Digital Representation and Digital Timing Reference Sequences for Multiple Picture Rates 8. SMPTE 295M-1997 Television - 1920 x 1080 50 Hz- Scanning and Interface 9. SMPTE 296M-2001 Television - 1280 x 720 Progressive Image Sample Structure- Analog and Digital Representation and Analog Interface 10.SMPTE 425M-2006 3Gbps Signal/Data Serial Interface - Source Image Format Mapping 11.SMPTE 352M-2002 for Television (Dynamic) - Video Payload Identification for Digital Interfaces 12.SMPTE 291M-2006 for Television - Ancillary Data Packet and Space Formatting LatticeECP3 • HB1009, LatticeECP3 Family Handbook • EB39, LatticeECP3 Video Protocol Board User’s Guide • TN1176, LatticeECP3 SERDES/PCS Usage Guide Revision History Date Document Version IP Core Version Change Summary May 2009 01.0 1.0 Initial release. October 2009 01.1 1.1 Added support for 3G Level-B and VPID insertion/extraction. July 2010 01.2 1.1 Divided document into chapters. Added table of contents. Added Quick Facts tables in Chapter 1, “Introduction.” Added new content in Chapter 4, “IP Core Generation.” Added new content in Chapter 5, “Application Support.” Added new content in Chapter 6, “Core Verification.” July 2010 01.3 1.1 Updated Figure 2-9. November 2010 01.4 1.2 Added Diamond software support throughout. December 2011 01.5 1.3 Added support for 8-bit TRS HD cameras. Expanded custom support to include 2K formats. IPUG82_01.5, December 2011 50 Tri-Rate SDI PHY IP User’s Guide Appendix A: Resource Utilization This appendix gives resource utilization information for Lattice FPGAs using the Tri-Rate SDI PHY IP core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com/software. LatticeECP3 FPGAs Table A-1. Performance and Resource Utilization1 Sample Configuration Slices LUTs Registers Tx Clock Rx Clock 1 1306 2506 1795 181 150 2 918 1747 1283 248 176 3 926 1772 1243 185 178 4 733 1403 1009 285 149 5 436 845 491 182 — 6 905 1714 1321 — 164 1. Performance and utilization data are generated using an LFE3-95EA-7FN1156C device with Lattice Diamond 1.3 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Table A-2. Parameter Settings for Sample Configurations1 Core Configuration 1 2 3 4 5 6 PHY function Parameter Name Both Both Both Both Tx Rx Enable 3G Level-B Yes Yes No No Yes Yes LN insertion On On On On On — CRC insertion On On On On On — VPID insertion On Off On Off On — LDR path for SD No No No No No — Include PLL for LDR — — — — — — 10-bit mode for SD Tx Yes Yes Yes Yes Yes — Separate input for SD — — — — — — SD data width 10 10 10 10 10 — VPID extraction On Off On Off — On 10-bit mode for SD Rx Yes Yes Yes Yes — Yes Clock enable port No No No No No No 1. The Tri-Rate SDI Physical Layer IP core is an IPexpress user-configurable core and can be used to generate any allowable configuration. Ordering Information The Ordering Part Number (OPN) for all configurations of the Tri-Rate SDI Physical Layer IP core targeting LatticeECP3 devices is TR-SDI-PHY-E3-U1. IPUG82_01.5, December 2011 51 Tri-Rate SDI PHY IP User’s Guide