DEMO MANUAL DC1370A
LTC2262-14/-12,
LTC2261-14/-12, LTC2260-14/-12, LTC2259-14/-12,
LTC2258-14/-12, LTC2257-14/-12, LTC2256-14/-12,
14-/12-Bit, 25Msps to 150Msps ADCs
Description
Demonstration circuit 1370A supports a family of 14-/12-Bit
25Msps to 150Msps ADCs. Each assembly features one
of the following devices: LTC2262-14, LTC2262-12
LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12,
LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12,
LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, high
speed, high dynamic range ADCs.
Demonstration circuit 1370A supports the LTC2262 family
full rate CMOS, and DDR CMOS output mode. This family
of ADCs is also supported by demonstration circuit 1369,
which is compatible with DDR LVDS output modes.
Performance Summary
Several versions of the 1370A demo board supporting the
LTC2262 14-/12-Bit series of A/D converters are listed in
Table 1. Depending on the required resolution and sample
rate, the DC1370A is supplied with the appropriate ADC.
The circuitry on the analog inputs is optimized for analog
input frequencies from 5MHz to 170MHz. Refer to the
data sheet for proper input networks for different input
frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and QuikEval and PScope are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
(TA = 25°C)
PARAMETER
CONDITIONS
VALUE
Supply Voltage – DC1370A
Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 150mA
Optimized for 3.6V
[3.5V ⇔ 6.0V Min/Max]
Analog Input Range
Depending on SENSE Pin Voltage
1VP-P to 2VP-P
Logic Input Voltages
Minimum Logic High
1.3V
Maximum Logic Low
0.6V
Minimum High Level Output Voltage
1.750V (1.790V Typical)
Maximum Low Level Output Voltage
0.050V (0.010V Typical)
Logic Output Voltages (OVDD = 1.8V))
Sampling Frequency (Convert Clock Frequency)
See Table 1
Convert Clock Level
Single-Ended Encode Mode (ENC – Tied to GND)
0V to 3.6V
Convert Clock Level
Differential Encode Mode (ENC – Not Tied to GND)
0.2V to 3.6V
Resolution
See Table 1
Input Frequency Range
See Table 1
SFDR
See Applicable Data Sheet
SNR
See Applicable Data Sheet
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DEMO MANUAL DC1370A
Quick Start Procedure
Table 1. DC1370A Variants
DC1370A VARIANTS
ADC PART NUMBER
RESOLUTION
MAXIMUM SAMPLE RATE
INPUT FREQUENCY
1370A-A
LTC2261-14
14-Bit
125Msps
5MHz to 170MHz
1370A-B
LTC2260-14
14-Bit
105Msps
5MHz to 170MHz
1370A-C
LTC2259-14
14-Bit
80Msps
5MHz to 170MHz
1370A-D
LTC2258-14
14-Bit
65Msps
5MHz to 170MHz
1370A-E
LTC2257-14
14-Bit
40Msps
5MHz to 170MHz
1370A-F
LTC2256-14
14-Bit
25Msps
5MHz to 170MHz
1370A-G
LTC2261-12
12-Bit
125Msps
5MHz to 170MHz
1370A-H
LTC2260-12
12-Bit
105Msps
5MHz to 170MHz
1370A-I
LTC2259-12
12-Bit
80Msps
5MHz to 170MHz
1370A-J
LTC2258-12
12-Bit
65Msps
5MHz to 170MHz
1370A-K
LTC2257-12
12-Bit
40Msps
5MHz to 170MHz
1370A-L
LTC2256-12
12-Bit
25Msps
5MHz to 170MHz
1370A-M
LTC2262-14
14-Bit
150Msps
5MHz to 170MHz
1370A-N
LTC2262-12
12-Bit
150Msps
5MHz to 170MHz
Demonstration circuit 1370A is easy to set up to evaluate
the performance of the LTC2262 A/D converters. Refer to
Figure 1 for proper measurement equipment setup and
follow the procedure:
Setup
If a DC890 QuikEval™II Data Acquisition and Collection
System was supplied with the DC1370A demonstration
circuit, follow the DC890 Quick Start Guide to install the
required software and for connecting the DC890 to the
DC1370A and to a PC.
DC1370A Demonstration Circuit Board Jumpers
The DC1370A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP2: PAR/SER: Selects Parallel or Serial programming
mode. (Default - Serial)
JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle
Stabilizer. (Default - Enable)
JP4: SHDN: Enables and disables the LTC2262.
(Default - Enable)
Applying Power and Signals to the DC1370A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1370A,
the DC890 must FIRST be connected to a powered USB
port or provided an external 6V to 9V BEFORE applying
3.6V to 6.0V across the pins marked V+ and GND on the
DC1370A. DC1370A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1370A demonstration circuit requires up
to 150mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an un-powered
hub, in which case it must be supplied an external 6V to
9V on turrets G7(+) and G1(–) or the adjacent 2.1mm
power jack.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequencies above 170MHz, refer to the LTC2262 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
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2
DEMO MANUAL DC1370A
quick start procedure
3.5V to 6V
+
JUMPERS ARE SHOWN IN
DEFAULT POSITIONS
ANALOG INPUT
N
PARALLEL DATA OUTPUT
TO DC890
PARALLEL/SERIAL
PROGRAMMING MODE
DUTY CYCLE
STABILIZER
SHDN
SINGLE ENDED
ENCODE CLOCK
Figure 1. DC1370A Setup
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR. In the
case of the DC1370A the bandpass filter used for the clock
should be used prior to the DC1075A.
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
NOTE: Apply an encode clock to the SMA connector on
the DC1370A demonstration circuit board marked J7.
As a default the DC1370A is populated to have a single
ended input.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
Encode Clock
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3VP-P or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075A that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2262 family.
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3
DEMO MANUAL DC1370A
quick start procedure
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. In the case of the DC1370A
a bandpass filter used for the clock should be used prior
to the DC1075A. Data sheet FFT plots are taken with 10
pole LC filters made by TTE (Los Angeles, CA) to suppress
signal generator harmonics, nonharmonically related spurs
and broadband noise. Low phase noise Agilent 8644B
generators are used with TTE bandpass filters for both
the clock input and the analog input.
Manual Configuration settings:
Bits: 14 (or 12 for 12-bit parts)
Alignment: 14
FPGA Ld: CMOS
Channs: 2
Bipolar: Unchecked
Positive-Edge Clk: Checked
Apply the analog input signal of interest to the SMA connectors on the DC1370A demonstration circuit board
marked J5 AIN+. These inputs are capacitive coupled to
balun transformers ETC1-1-13.
An internally generated conversion clock output is available on J1 which could be collected via a logic analyzer, or
other data collection system if populated with a SAMTEC
MEC8-150 type connector or collected by the DC890
QuikEval™II Data Acquisition Board using PScope™
software.
Software
The DC890 is controlled by the PScope System Software
provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC890
was provided, follow the DC890 Quick Start Guide and
the instructions below.
To start the data collection software if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double
click the PScope Icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1370A demonstration circuit is properly connected
to the DC890, PScope should automatically detect the
DC1370A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to ADC Configuration....
Check the Config Manually box and use the following
configuration options, see Figure 2:
Figure 2. ADC Configuration
If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC890 Quick Start Guide and in
the online help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1370A board
serially through the DC890. There are several options
available in the LTC2262 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Board Options icon on the PScope toolbar (Figure 3).
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4
DEMO MANUAL DC1370A
quick start procedure
Clock Inversion: Selects the polarity of the CLKOUT signal
• Normal (Default): Normal CLKOUT polarity
• Inverted: CLKOUT polarity is inverted
Figure 3. PScope Toolbar
This will bring up the menu shown in figure 4.
Clock Delay: Selects the phase delay of the CLKOUT signal:
• None (Default): No CLKOUT delay
• 45 deg: CLKOUT delayed by 45 degrees
• 90 deg: CLKOUT delayed by 90 degrees
• 135 deg: CLKOUT delayed by 135 degrees
Clock Duty Cycle: Enable or disables Duty Cycle Stabilizer
• Stabilizer off (Default): Duty Cycle Stabilizer Disabled
• Stabilizer on: Duty Cycle Stabilizer Enabled
Output Current: Selects the LVDS output drive current.
This option is not used on the DC1370A
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Figure 4. Demo Board Configuration Options
Internal Termination: Enables LVDS Internal Termination.
This option is not used on the DC1370A
This menu allows any of the options available for the
LTC2262 family to be programmed serially. The LTC2262
family has the following options:
• Off (Default): Disables internal termination
Power Control: Selects between normal operation, nap,
and sleep modes
Outputs: Enables Digital Outputs
• Normal (Default): Entire ADC is powered, and active
• Disabled: Disables digital outputs
• On: Enables internal termination
• Enabled (Default): Enables digital outputs
• Nap: ADC core powers down while references stay active
• Shutdown: The entire ADC is powered down
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5
DEMO MANUAL DC1370A
quick start procedure
Output Mode: Selects Digital Output Mode
Alternate Bit: Alternate Bit Polarity (ABP) Mode
• Full Rate (Default): Full rate CMOS output mode
• Off (Default): Disables alternate bit polarity
• Double LVDS: double data rate LVDS output mode
(This mode is not supported by the DC1370A, please
use the DC1369)
• On: Enables alternate bit polarity (Before enabling ABP,
be sure the part is in offset binary mode)
• Double CMOS: double data rate CMOS output mode
Test Pattern: Selects Digital Output Test Patterns
• Off (Default): ADC data presented at output
• All out =1: All digital outputs are 1
• All out = 0: All digital outputs are 0
• Checkerboard: OF, and D13-D0 Alternate between 101
0101 1010 0101 and 010 1010 0101 1010 on alternating samples
• Alternating: Digital outputs alternate between all 1’s and
all 0’s on alternating samples
• Randomizer: Enables Data Output Randomizer
• Off (Default): Disables data output randomizer
• On: Enables data output randomizer
• Two’s complement: Enables Two’s Complement Mode
• Off (Default): Selects offset binary mode
• On: Selects two’s complement mode
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1370A demo board.
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6
DEMO MANUAL DC1370A
Parts List
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
1
0
C1
CAP, 0402 OPTION
OPTION
2
12
C2, C3, C6, C7, C38, C39, C52,
C53, C58, C60, C61, C63
CAP, 0402, 0.01µF, 10%, 16V, X7R
AVX 0402YC103KAT
3
2
C10, C9
CAP, 0402, 8.2pF, 5%, 50V, COG
AVX 04025A8R2JAT2A
4
6
C12, C15, C18, C19, C21, C37
CAP, 0402, 0.1µF, 10%, 10V, X5R
TDK C1005X5R1A104K
5
3
C13, C17, C23
CAP, 0402, 1µF, 10%, 10V, X5R
TDK C1005X5R1A105K
6
3
C14, C22, C57
CAP, 0603, 1µF, 10%, 16V, X7R
TDK C1608X7R1C105K
7
1
C20
CAP, 0402, 1µF, 10%, 10V, X5R
MURATA GRM155R61A105KE15D
8
1
C24
CAP, 0603, 4.7µF, 20%, 6.3V, X5R
TDK C1608X5R0J475MT
9
13
C26–C36, C40, C56
CAP, 0603, 0.1µF, 10%, 50V, X7R
TDK C1608X7R1H104K
10
1
C51
CAP, 0402, 4.7pF, ±0.25pF, 50V, NPO
AVX 04025A4R7CAT2A
11
3
C54, C55, C59
CAP, 1206, 22µF, 10%, 6.3V, X5R
AVX 12066D226KAT2A
12
9
R9, R10, R46, R48, R54, R56,
C62, C64, R75
RES, 0402, 0Ω JUMPER
VISHAY CRCW04020000Z0ED
13
1
D1
DIODE, SCHOTTKY SOT-23
AVAGO HSMS-2822
14
3
JP2, JP3, JP4
HEADER, 3-PIN, 2mm
SAMTEC TMM-103-02-L-S
15
3
J5, J7, J9
CONN, BNC, SMA 50Ω EDGE-LANCH
E.F.JOHNSON, 142-0701-851
16
1
J8
HEADER, 2 × 7, 2mm
MOLEX 87331-1420
17
1
L1
IND, 0603, 56µH, 5%
MURATA LQP18MN56NG02D
18
3
L2, L3, L4
FERRITE BEAD, 1206
MURATA BLM31PG330SN1L
19
1
L5
IND, 0603 BEAD
OPTION
IND, 0603 OPT
20
0
L6
21
6
RN1, RN2, RN3, RN4, RN5, RN6 RES ARRAY, 33Ω
VISHAY CRA04SS08333R0JTD
OPTION
22
2
R1,R2
RES, 0402, 301Ω, 1%, 1/16W
VISHAY CRCW0402301RFKED
23
0
R4, R5, R49, R52, R53, R55,
R57, R74
RES, 0402 OPTION
OPTION
24
1
R6
RES, 0402, 10kΩ, 5%, 1/16W
VISHAY CRCW040210K0JNED
25
1
R7
RES, 0402, 64.9kΩ, 1%, 1/16W
VISHAY CRCW040264K9FKED
26
2
R8, R47
RES, 0402, 100kΩ, 1%, 1/16W
YAGEO RC0402FR-07100KL
27
4
R14, R33, R34, R35
RES, 0402, 1kΩ, 5%, 1/16W
PANASONIC ERJ-2GEJ102X
28
1
R16
RES, 0402, 100Ω, 5%, 1/16W
VISHAY CRCW0402100RJNED
29
1
R24
RES, 0402, 100kΩ, 5%, 1/16W
VISHAY CRCW0402100KJNED
30
3
R25, R26, R29
RES, 0603, 4.99kΩ, 1%, 1/16W
AAC CR16-4991FM
31
3
R36, R44, R45
RES, 0402, 86.6Ω, 1%, 1/16W
VISHAY CRCW040286R6FKED
32
2
R40, R39
RES, 0402, 24.9Ω, 1%, 1/16W
YAGEO RC0402FR-0724R9FL
33
1
R50
IND, 36nH
COILCRAFT 0402CS-36NXJB
34
1
R51
RES, 0402, 301Ω, 1%, 1/16W OPTION
OPTION
35
5
TP1, TP2, TP3, TP4, TP5
TURRETS
MILLMAX 2501-2-00-80-00-00-07-0
36
1
T1
XFMR, 1:1
MACOM MABA-007159-000000
37
1
T2
XFMR, 1:1 CT
M/A-C0M MABAES0060
38
1
T3
XFMR, 1:4 CT
COILCRAFT WBC4-1WLB
39
1
U1
IC, 24LC025-I/ST
MICROCHIP TECH. 24LC025-I/ST
40
2
U7, U3
IC, BI-DIRECTIONAL INTERFACE
FAIRCHILD FXLH42245
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7
DEMO MANUAL DC1370A
Parts List
41
1
U4
IC, LDO Micropower Regulators
LINEAR TECH. LT1763CDE-1.8
42
1
U5
IC, 8-BIT, I/0 EXPANDER
PHILIPS SEMI PCF8574TS/3
43
2
U10, U6
IC, LDO Micropower Regulators
LINEAR TECH. LT1763CDE
44
1
U8
IC, ULP INVERTER
FAIRCHILD NC7SP14P5X
45
1
U9
IC, EEPROM
MICROCHIP TECH. 24LC32A-I/ST
46
3
XJP2, XJP3, XJP4
47
4
SHUNT, 2mm
SAMTEC 2SN-BK-G
STANDOFF, SNAP ON
KEYSTONE_8831
Schematic Diagram
dc1730afa
8
A
B
C
TP2
ENC-
GND
GND
TP5
TP3
3.5V - 6V
V+
TP4
2
C18
0.1uF
0.1uF
C9
8.2pF
R36
86.6
1%
0.01uF
1
C26
J9
0.1uF
0.1uF
1uF
4.7uF
1uF
C22
C14
0.01uF
C60
OPT
5
8
12
1
4
9
10
11
8
12
1
4
9
10
11
C31
C30
L6
0.1uF
0.1uF
C7
0.01uF
0.1uF
C32
0.1uF
GND
BYP
SENSE
OUT
OUT
SHDN
NC
NC
NC
NC
IN
IN
GND
BYP
SENSE
OUT
OUT
U6 LT1763CDE
SHDN
NC
NC
NC
NC
IN
IN
7
6
5
2
3
7
6
5
2
3
R75
0
1%
U4 LT1763CDE-1.8
R53 OPT
2
0.01uF
C39
L5
BEAD
1uF
C57
22uF
C55
8
12
1
4
9
10
11
0.1uF
C21
0.1uF
C15
R10 0
R40
24.9
1%
R39
24.9
1%
R2
301
1%
1%
SHDN
NC
NC
NC
NC
IN
IN
GND
BYP
SENSE
OUT
OUT
U10 LT1763CDE
R8 100K
VDD
R54 0
R4 OPT
1uF
C20
7
6
5
2
3
4
10
9
8
7
6
5
4
3
2
1
22uF
C59
VDD
39
JP2
R14
1K
R16
100
3
2
1
1%
PAR/SER
R33
1K
R47 100K
0.1uF
C37
37
VDD
PAR/SER
OVDD
SER
R46 0
L4
BEAD
2
PAR
C62
C64
2
VDD
VDD
R55 OPT
OPT
R52
1
R51
OPT
1
OPT
VDD
1uF
C23
1uF
C13
PAR/SER
REFL
REFL
REFH
REFH
GND
AIN-
AIN+
1uF
C17
TP1
R49
0.01uF
C58
VDD
U2 *
EXT REF
PAR/SER
0.01uF
C3
C51
4.7pF
C61
0.01uF
R5 OPT
R48 0
R57 OPT
R1
301
1%
+3.3V
L2
BEAD
R7 64.9K 1%
L3
22uF
C54
0.01uF
C63
BEAD
0.1uF
VDD
C40
0.1uF
C12
0.1uF
C36
T3
WBC4-1WL
0.01uF
C38
C2 0.01uF
R74
OPT
1%
C35
0.1uF
T2
MABAES0060
C34
D1
HSMS-2822
1
R50 36nH
R56 0
C33
C10
8.2pF
R44
86.6
1%
56uH
C19
L1
C24
VIN
OPT
C1
0.1uF
0.1uF
J7
C29
C28
+3.3V
ENC+
GND
J5
VDD
AIN+
T1
MABA-007159-000000
2
1
R45 86.6 1%
3
C6
2
1
GND
41
R9 0
11
D
2
1
2
1
2
1
2
1
40
VDD
ENC+
12
SENSE
38
VREF
13
ENC-
35
CS
CS
36
14
SCK
VCM
15
SDI
SCK
34
OF+
SDI
16
SD0
OFSDO
33
D13
D0
3
2
1
VDD
CS
R34
1K
D4
D5
D6
D7
OGND
OVDD
CLKOUT-
CLKOUT+
D8
D9
21
22
23
24
25
26
27
28
29
30
OX40
SCL
SDA
6
7
9
2
4
3
8
1
A0
A1
A2
SCL
SDA
NC
NC
3
3
2
1
R35
1K
P0
P1
P2
P3
P4
P5
P6
P7
NC
NC
10
11
12
14
16
17
19
20
18
13
33
8
7
6
5
RN6 33
8
7
6
5
RN2
1
2
3
4
SDI
1
2
3
4
RN3 33
VDD
1
2
3
4
SHDN
JP4
OVDD
3
+3.3V
DIS
EN
INT
U5
PCF8574TS/3
DUTY CYCLE STAB.
DIS
EN
JP3
31
D10
32
D12
17
D11
D1
18
D2
19
D3
20
4
8
7
6
5
1
2
3
4
+3.3V
NC
EEVCC
EESDA
EESCL
EEGND
CS
SCK/SCL
MOSI/SDA
MISO
R6 10K
CS
J8
OVDD
8
7
6
5
OVDD
VUNREG
5V
RN5 33
SCK
SDI
SD0
1
2
3
4
RN4 33
8
7
6
5
GND
GND
GND
1
2
14
10
9
11
12
6
4
7
5
OVDD
A0
A1
A2
A3
A4
A5
A6
A7
TR
OE
+3.3V
A0
A1
A2
A3
A4
A5
A6
A7
TR
OE
8
7
6
5
2
1
2
3
4
0.01uF
0.01uF
APPROVALS
2
05/22/12 06:30:35
DESIGNER
ENGINEER
APPROVED
CHECKED
DRAWN MI
CS
SCK
SDI
SD0
10/31/07
DATE
1
REVISION HISTORY
R24
100K
R25 4.99K 1%
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
R26 4.99K 1%
SCL
SDA
TECHNOLOGY
U1 24LC025-I/ST
1
8
2 A0 VCC 7
WP 6
3 A1
4 A2 SCL 5
A3 SDA
C27 0.1uF
+3.3V
SDA
SCL
VCC_IN
VSS
ENABLE
R29 4.99K 1%
VCC_IN
SDA
VSS
SCL
FAST DAACS BOARD ID CIRCUITRY
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
EDGE-CON-100
APPROVED
Clarence M.
A
B
C
D
SCALE:NONE
1
SHEET
DC1370A
FILENAME: 1370A-3.DSN
DWG NO
1
OF
2
3
REV
SCH, LTC2261CUJ, HIGH SPEED LOW POWER
125MSPS ADC FAMILY, CMOS
VCC_IN
VSS
SCL
SDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
P1
05/21/12
Change
DATE
08/20/08
PROTO
3
DESCRIPTION
3.1
REV
SIZE CAGE CODE
TITLE
VCC_IN
SDA
SCL
VSS
C53
C52
U9 24LC32A-I/ST
8
A0 VCC 7
A1
WP 6
A2 SCL 5
A3 SDA
D7
D6
D5
D4
D3
D2
D1
D0
D13
D12
D11
D10
D9
D8
ECO
C56 0.1uF
21
20
19
18
17
16
15
14
21
20
19
18
17
16
15 +CLK
14 -CLK
ENABLE
NC7SP14P5X
U8
B0
B1
B2
B3
B4
B5
B6
B7
+3.3V
B0
B1
B2
B3
B4
B5
B6
B7
+3.3V
CONTRACT NO.
33
OXA2
RN1
1
2
3
4
4
3
4
5
6
7
8
9
10
2
22
2
OVDD
U7
FXLH42245
3
4
5
6
7
8
9
10
2
22
U3
FXLH42245
1
1
VCCA
5
5
VDD
GND
15
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3
8
13
5
3
VCCA
24
23
VCCB
VCCB
GND
GND
GND
GND
11
12
13
25
24
23
VCCB
VCCB
GND
GND
GND
GND
11
12
13
25
This circuit is proprietary to Linear Technology and supplied
for use with Linear Technology parts.
Customer Notice:Linear Technology has made a best effort to
design a circuit that meets customer-supplied specifications;
however, it remains the customers responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly
affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
DEMO MANUAL DC1370A
Schematic Diagram
dc1730afa
9
DEMO MANUAL DC1370A
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
dc1730afa
10 Linear Technology Corporation
LT 0712 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012