DC1762A-F

DEMO MANUAL DC1762A LTC2165, LTC2164, LTC2163 LTC2162, LTC2161, LTC2160, LTC2159, LTC2269 16-Bit, 20Msps to125Msps ADCs Description Demonstration circuit 1762A supports a family of 16-Bit 20Msps to 125Msps ADCs. Each assembly features one of the following devices: LTC®2165, LTC2164, LTC2163, LTC2162, LTC2161, LTC2160, LTC2159, or LTC2269 high speed, high dynamic range ADCs. Depending on the required resolution and sample rate, the DC1762A is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 140MHz. Refer to the data sheet for proper input networks for different input frequencies. Demonstration circuit 1762A supports the LTC2165 family DDR LVDS output mode. Design files for this circuit board are available at http://www.linear.com/demo The versions of the 1762A demo board supporting the LTC2165 series of A/D converters are listed in Table 1. L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks and PScope is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Table 1. DC1762A Variants DC1762A VARIANTS 1762A-A 1762A-B 1762A-C 1762A-D 1762A-E 1762A-F 1762A-G 1762A-H ADC PART NUMBER LTC2165 LTC2164 LTC2163 LTC2162 LTC2161 LTC2160 LTC2159 LTC2269 Performance Summary RESOLUTION 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit MAXIMUM SAMPLE RATE 125Msps 105Msps 80Msps 65Msps 40Msps 25Msps 20Msps 20Msps INPUT FREQUENCY 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz 5MHz to 140MHz (TA = 25°C) PARAMETER CONDITIONS MIN Supply Voltage – DC1762A Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide up to 500mA. 4.5 6 V Analog Input Range Depending on SENSE Pin Voltage 1 2 VP-P Logic Input Voltages Minimum Logic High Maximum Logic Low 1.3 0.6 V V Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) Common Mode Minimum Logic Levels (100Ω Load, 3.5mA Mode) Common Mode 350 1.25 247 1.25 mV V mV V Sampling Frequency (Convert Clock Frequency) See Table 1 Convert Clock Level Single-Ended Encode Mode (ENC– Tied to GND) Differential Encode Mode (ENC– Not Tied to GND) Resolution See Table 1 Input Frequency Range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet 0 0.2 TYP MAX 3.6 3.6 UNITS V V dc1762afb 1 DEMO MANUAL DC1762A Quick Start Procedure Demonstration circuit 1762A is easy to set up to evaluate the performance of the LTC2165 A/D converter family. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below: DC1762 Demonstration Circuit Board Jumpers Setup JP2 PAR/SER: Selects parallel or serial programming mode. (default: serial) If a DC890 USB demonstration circuit was supplied with the DC1762A demonstration circuit, follow the DC890 Quick Start Guide to install the required software and for connecting the DC890 to the DC1762A and to a PC. The DC1762A demonstration circuit board should have the following jumper settings as default positions: (as per Figure 1) JP3 Duty Cycle Stabilizer: enables/disables duty cycle stabilizer. (default: enable) JP4 SHDN: Enables and disables the LTC2165. (default: enable) JP5 NAP: Enables and disables NAP mode. (default: enable) JP6 LVDS/CMOS: Selects between LVDS and CMOS output signaling. (default: LVDS) 4.5V TO 6V ANALOG INPUT PARALLEL DATA OUTPUT TO DC890 PARALLEL/SERIAL PROGRAMMING MODE DUTY CYCLE STABILIZER SHDN NAP LVDS/CMOS SINGLE-ENDED ENCODE CLOCK FROM DC1075 dc1762a F01 Figure 1. DC1762 Setup dc1762afb 2 DEMO MANUAL DC1762A quick start procedure Applying Power and Signals to the DC1762A Demonstration Circuit If a DC890 is used to acquire data from the DC1762A, the DC890 must FIRST be connected to a powered USB port or provided an external 6V to 9V BEFORE applying 4.5V to 6V across the pins marked V+ and GND on the DC1762A. DC1762A requires 4.5V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1762A demonstration circuit requires up to 500mA depending on the sampling rate and the A/D converter supplied. The DC890 data collection board is powered by the USB cable and does require an external power supply when collecting data from and LVDS demo board. It must be supplied an external 6V to 9V on turrets G7(+) and G1(–) or the adjacent 2.1mm power jack. Analog Input Network For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequencies above 140MHz, refer to the respective ADC data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less than 5MHz, or above 140MHz. In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. In the case of the DC1762A, a bandpass filter used for the clock should be used prior to the DC1075 clock divider board. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. Apply the analog input signal of interest to the SMA connector on the DC1762A demonstration circuit board marked J5 AIN+. This input is capacitively coupled to a Balun transformer ETC1-1-13 (lead free part number: MABA007159-000000). Encode Clock NOTE: Apply an encode clock to the SMA connector on the DC1762A demonstration circuit board marked J3 ENC+. As a default the DC1762A is populated to have a single-ended input. For the best noise performance, the encode input must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075 that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2165. Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1762A a bandpass filter used for the clock should be used prior to the DC1075. Datasheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non-harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used with TTE bandpass filters for both the clock input and the analog input. An internally generated conversion clock output is available on J1 which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8150 type connector or collected by the DC890 QuikEval-II Data Acquisition Board using PScope™ software. dc1762afb 3 DEMO MANUAL DC1762A quick start procedure Software The DC890 is controlled by the PScope System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a DC890 was provided, follow the DC890 Quick Start Guide and the instructions below. To start the data collection software if PScope.exe, is installed (by default) in \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC1762A demonstration circuit is properly connected to the DC890, PScope should automatically detect the DC1762A, and configure itself accordingly. If necessary the procedure below explains how to manually configure PScope. Under the Configure menu, go to ADC Configuration… Check the Config Manually box and use the following configuration options, see Figure 2. Manual Configuration settings: Bits: 16 Alignment: 16 FPGA Ld: DDR LVDS Figure 2: ADC Configuration the PScope window. Additional information and help for PScope is available in the DC890 Quick Start Guide and in the online help available within the PScope program itself. Serial Programming PScope has the ability to program the DC1762A board serially through the DC890. There are several options available in the LTC2165 family that are only available through serially programming. PScope allows all of these features to be tested. Channs: 2 These options are available by first clicking on the Set Demo Bd Options icon on the PScope toolbar (Figure 3). Bipolar: Unchecked This will bring up the menu shown in Figure 4. Positive-Edge Clk: Unchecked If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button should result in time and frequency plots displayed in Figure 3: PScope Toolbar dc1762afb 4 DEMO MANUAL DC1762A quick start procedure Clock Inversion: Selects the polarity of the CLKOUT signal: • Normal (Default): Normal CLKOUT polarity • Inverted: CLKOUT polarity is inverted Clock Delay: Selects the phase delay of the CLKOUT signal: • None (Default): No CLKOUT delay • 45 deg: CLKOUT delayed by 45 degrees • 90 deg: CLKOUT delayed by 90 degrees • 135 deg: CLKOUT delayed by 135 degrees Clock Duty Cycle: Enables or disables duty cycle stabilizer • Stabilizer off (Default): Duty cycle stabilizer disabled • Stabilizer on: Duty cycle stabilizer enabled Output Current: Selects the LVDS output drive current • 1.75mA (Default): LVDS output driver current • 2.1mA: LVDS output driver current • 2.5mA: LVDS output driver current • 3.0mA: LVDS output driver current • 3.5mA: LVDS output driver current Figure 4: Demobd Configuration Options This menu allows any of the options available for the LTC2165 family to be programmed serially. The LTC2165 family has the following options: • 4.0mA: LVDS output driver current • 4.5mA: LVDS output driver current Internal Termination: Enables LVDS internal termination • Off (Default): Disables internal termination • On: Enables internal termination Power Down: Selects between normal operation, nap, and sleep modes: Outputs: Enables digital outputs • Normal (Default): Entire ADC is powered, and active. • Enabled (Default): Enables digital outputs • Nap: ADC core powers down while references stay active. • Disabled: Disables digital outputs • Shutdown: The entire ADC is powered down. dc1762afb 5 DEMO MANUAL DC1762A quick start procedure Output Mode: Selects digital output mode Alternate Bit: Alternate Bit Polarity (ABP) Mode • Full Rate: Full rate CMOS output mode (This mode is not supported by the DC1762A) • Off (Default): Disables alternate bit polarity • Double LVDS (Default): Double data rate LVDS output mode • Double CMOS: Double data rate CMOS output mode (This mode is not supported by the DC1762A) Test Pattern: Selects digital output test patterns • Off (Default): ADC data presented at output • All out =1: All digital outputs are 1 • All out = 0: All digital outputs are 0 • Checkerboard: OF, and D13-D0 Alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternating samples. • On: Enables alternate bit polarity (Before enabling ABP, be sure the part is in offset binary mode) Randomizer: Enables Data Output Randomizer • Off (Default): Disables data output randomizer • On: Enables data output randomizer Two’s complement: Enables two’s complement mode • Off (Default): Selects offset binary mode • On: Selects two’s complement mode Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1762A demo board. • Alternating: Digital outputs alternate between all 1’s and all 0’s on alternating samples. dc1762afb 6 DEMO MANUAL DC1762A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components 1 1 CN1 Capacitor, Array, 0508, 2.2µF, 20%, 10V, X5R AVX W2L14D225MAT1A 2 7 C1, R28, R32, R47, R48, R53, R54 Resistor, 0402, 0Ω, Jumper Vishay CRCW04020000Z0ED 3 7 C2, C3, C6, C7, C8, C59, C60 Capacitor, 0402, 0.01µF, 10%, 16V, X7R AVX 0402YC103KAT 4 2 C9, C10 Capacitor, 0402, 8.2pF, 5%, 50V, COG AVX 04025A8R2JAT2A 5 8 C12, C13, C15, C18, C19, C21, C37, C61 Capacitor, 0402, 0.1µF, 10%, 10V, X5R TDK C1005X5R1A104K 6 2 C14, C22 Capacitor, 0603, 1µF, 10%, 16V, X7R TDK C1608X7R1C105K 7 2 C17, C23 Capacitor, 0402, 2.2µF, 20%, 6.3V, X5R Taiyo Yuden JMK105BJ225MV-T 8 1 C24 Capacitor, 0603, 4.7µF, 20%, 6.3V, X5R TDK C1608X5R0J475MT 9 11 C26-C32, C34-C36, C62 Capacitor, 0603, 0.1µF, 10%, 50V, X7R TDK C1608X7R1H104K 10 0 C33, C40, C41 Capacitor, 0603, 0.1µF, 10%, 50V, X7R Option TDK C1608X7R1H104K Option 11 2 C38, C39 Capacitor, 0402, 22pF, 5%, 16V, NPO AVX 0402YA220JAT2A 12 1 C51 Capacitor, 0402, 4.7pF, ±0.25pF, 50V, NPO AVX 04025A4R7CAT2A 13 2 C54, C55 Capacitor, 1206, 1µF, 10%, 16V, X7R AVX 1206YC105KAT2A 14 5 JP2, JP3, JP4, JP5, JP6 Header, 3-Pin, 2mm Samtec TMM-103-02-L-S 15 3 J5, J7, J9 Connector, BNC, SMA, 50Ω, Edge-Lanch E. F. Johnson, 142-0701-851 16 2 L1, L5 Inductor, 0603, 56µH, 5% Murata LQP18MN56NG02D 17 3 L2, L3, L4 Ferrite Bead, 1206 Murata BLM31PG330SN1L 18 1 RN2 Resistor, Array, 33Ω Vishay CRA04SS08333R0JTD 19 2 R1, R2 Resistor, 0402, 49.9Ω, 1%, 1/16W Vishay CRCW040249R9FKED 20 0 R4, R5 Resistor, 0402, 5.1Ω, 1%, 1/16W Option Vishay CRCW04025R10FNED Option 21 1 R6 Resistor, 0402, 10kΩ, 5%, 1/16W Vishay CRCW040210K0JNED 22 1 R7 Resistor, 0402, 180kΩ, 1%, 1/16W Vishay CRCW0402180KFKED 23 1 R8 Resistor, 0402, 330kΩ, 1%, 1/16W Vishay CRCW0402330KFKED 24 4 R9, R10, R11, R12 Resistor, 0402, 10Ω, 1%, 1/16W Vishay CRCW040210R0FKED 25 6 R14, R33, R34, R35, R37, R38 Resistor, 0402, 1kΩ, 5%, 1/16W Vishay CRCW04021K00JNTDE3 26 2 R15, R41 Resistor, 0402, 3kΩ, 1%, 1/16W Vishay CRCW04023K00FKED 27 4 R16, R27, R46, R55 Resistor, 0402, 100Ω, 5%, 1/16W Vishay CRCW0402100RJNED 28 9 R17-R23, R30, R31 Resistor, 0201, 100Ω, 5%, 1/16W Vishay CRCW0201100RFNTD 29 1 R24 Resistor, 0402, 100kΩ, 5%, 1/16W Vishay CRCW0402100KJNED 30 3 R25, R26, R29 Resistor, 0603, 4.99kΩ, 1%, 1/16W AAC CR16-4991FM 31 3 R36, R44, R45 Resistor, 0402, 86.6Ω, 1%, 1/16W Vishay CRCW040286R6FKED 32 2 R39, R40 Resistor, 0402, 33.2Ω, 1%, 1/16W Vishay CRCW040233R2FKED 33 0 R49, R50, R51, R52 Resistor, 0402, 100Ω, 5%, 1/16W Option Vishay CRCW0402100RJNED Option 34 5 TP1, TP2, TP3, TP4, TP5 Turrets Millmax 2501-2-00-80-00-00-07-0 dc1762afb 7 DEMO MANUAL DC1762A parts list ITEM QTY 35 1 36 1 REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER T1 XFMR, 1:1 Macom MABA-007159-000000 T2 XFMR, 1:1 CT M/A-C0M MABAES0060 T2 - Alternate XFMR, 1:1 CT Coilcraft WBC1-1LB 37 1 T3 XFMR, 1:1 Macom MABA-007159-000000 38 1 U1 IC, EEPROM Microchip Tech. 24LC025-I/ST 39 1 U2 Refer to Schematic Table Linear, Technology 40 1 U3 IC, FIN1108 Fairchild FIN1108 41 2 U4, U6 IC, Adjustable 1.1A Regulators Linear, Technology LT3080EDD 42 1 U5 IC, 8-Bit I/0 Expander Philips Semi PCF8574TS/3 43 1 U8 IC, LVDS Single Port High Speed Repeater Fairchild FIN1101K8X 44 5 JP2, JP3, JP4, JP5, JP6 Shunt, 2mm Samtec 2SN-BK-G 45 4 Standoff, Snap On KEYSTONE_8831 dc1762afb 8 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D TP2 GND GND GND TP4 TP5 TP3 3.5V - 6V V+ ENC- J9 J7 C6* 2.2uF C17 TP1 ENC+ AIN+ J5 EXT REF 4.7uF 0603 OPT C1 1uF 0603 C22 1uF 0603 C14 8.2pF 8.2pF C24 C10 C9 OPT R44 86.6 1% 56nH R36 86.6 1% C60 L1 R45 86.6 1% R53 0 0 R47 3 2 1 5 5 7 8 5 7 8 REST VOUT VOUT VOUT VOUT VCTRL VIN VIN REST VOUT VOUT VOUT VOUT 4 3 2 1 9 4 3 2 1 9 C2 0.01uF U6 LT3080EDD VCTRL VIN VIN T3 R57 OPT 0.1uF C12 T2 MABAES0060 0.1uF 330K 1% C20 R8 C55 10uF 1206 0.1uF C16 VDD 0.01uF C3 C15* C54 10uF 1206 R7 100 R27 R41 3K 1% R15 3K 1% L3 R4 5.1 1% R1 49.9 1% R2 49.9 1% R5 5.1 1% BEAD BEAD BEAD L4 L2 R46 OPT R52 OPT +3.3V 0.1uF C37 100 R55 R51 100 4 * C61 OPT 9 8 7 6 5 4 3 2 1 * 0 VDD GND GND PAR/SER REFL REFH REFL REFH GND AIN- AIN+ C23 2.2uF SDO R16 100 JP3 3 2 1 VDD R34 1K 20Msps 20Msps LTC2159CUP LTC2269CUP -H 25Msps -F -G 40Msps LTC2160CUP -E 65Msps 80Msps LTC2163CUP 125Msps 105Msps LTC2162CUP 39 SAMPLE RATE CS LTC2164CUP LTC2165CUP U2 DUTY CYCLE STAB. DIS EN ENC- ENC+ 43 LTC2161CUP -D -C -B -A ASSY R32 0 R28 12 11 VDD 3 2 1 VCM NAP JP5 10 U2 DIS PAR/SER AIN- AIN+ VCM1 VDD R49 OPT VDD OVDD 5 6 3 2.2uF 7 2 4 8 CN1 R11 10 1% R12 10 1% 1 C51* R40 33.2 1% R39 33.2 1% R48 OPT OPT L5 C13* R54 OPT R10 10 1% R9 10 1% C21* 180K 1% MABA-007159-000000 5 1 2 4 3 U4 LT3080EDD 0.01uF C59 PAR/SER R33 1K OPT C25 R56 OPT VDD PAR/SER R50 OPT SER PAR JP2 C7* T1 MABA-007159-000000 EN R37 1K VDD SDO 44 R14 1K 4 48 VDD 47 14 VDD 13 VDD GND 46 SENSE 15 ENC+ 45 VREF ENC16 42 17 SDO CS CS OF+ GND SCK 18 SCK SDI 19 SDI 41 OFGND 20 40 21 3 2 1 R38 1K VDD 25 26 27 28 29 30 31 32 33 34 35 36 16 16 16 16 16 16 16 16 SCK OVDD R19 100 0201 R18 100 0201 R17 100 0201 DIS EN 5 < AIN < 170 3 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 5 < AIN < 170 1 2 3 4 0201 3 2 1 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF C6, C7 SDI 1.0uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 8 7 6 5 10puF 4.7puF 4.7puF 4.7puF 4.7puF 4.7puF 4.7puF 4.7puF C51 0.1uF +3.3V C62 C13, C15, C21 R35 1K RIN+ VCC DOUT+ DOUT- U8 FIN1101K8X RINGND EN GND R31 100 VDD SHDN JP4 OUT-ENABLE1 R30 100 0201 3 FREQUENCY RANGE LVDS/CMOS JP6 D4_5- D4_5+ D6_7- D6_7+ CLKOUT- CLKOUT+ OGND OVDD D8_9- D8_9+ D10_11- D10_11+ No. of BITS DIS EN D14_15- D14_15+ D0_1- 37 D12_13- 38 D12_13+ D0_1+ 22 D2_323 D2_3+ 24 GND 49 5 R20 100 0201 R23 100 0201 C28 C29 C30 VBB IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4IN5IN5+ IN6+ IN6IN7IN7+ IN8+ IN8- EN12 EN34 EN56 EN78 EN P0 P1 P2 P3 P4 P5 P6 P7 NC NC 0.1uF 0603 +3.3V OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUR4+ OUT4OUT5OUT5+ OUT6+ OUT6OUT7OUT7+ OUT8+ OUT8- C32 0.1uF 0603 C38 0.1uF 0603 C36 22pF C39 +3.3V CS SCK SDI SDO R6 10K OPT 0603 C40 OPT 0603 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 EDGE-CON-100 2    R24 100K  C27 0.1uF U1 24LC02ST 1 8 2 A0 VCC 7 WP 6 3 A1 4 A2 SCL 5 A3 SDA 1% R26 4.99K 1% SCL SDA R25 4.99K  1   DEMO CIRCUIT 1762A LTC21XXCUP FAMILY HIGH SPEED LOW POWER ADC FAMILY, LVDS   1        SDA VSS SCL APPROVED Clarence M. CLARENCE M. VCC_IN 1. ALL CAPACITORS AND RESISTORS ARE 0402.   N/A +3.3V OUT-ENABLE1 R29 4.99K 1% VCC_IN SDA VSS SCL FAST DAACS BOARD ID CIRCUITRY 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 06/08/12 DATE 12/13/10 1.1 Part Added P1 1 PROTO 1 REVISION HISTORY DESCRIPTION REV NOTES: UNLESSOTHERWISE SPECIFIED, 001 ECO C41 CLK+ CLK-  OPT 0603 C33 0.1uF 0603 C35 0.1uF 0603 C19 D14/15+ D14/15D12/13+ D12/13D10/11+ D10/11D8/09+ D8/09D6/07+ D6/07D4/05+ D4/05D2/03+ D2/03D0/01+ D0/01- 22pF C34 8 7 6 5 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 0.1uF 0603 33 0.1uF 0603 0.1uF 0603 RN2 1 2 3 4 C18 C26 0.1uF 0603 C31 10 11 12 14 16 17 19 20 18 13 VDD  0.1uF 0603 A0 A1 A2 SCL SDA NC NC INT +3.3V 24 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 3 22 27 46 13 2   TECHNOLOGY             0.1uF 0603 6 7 9 2 4 3 8 1 U5 PCF8574TS/3 SCL SDA R22 100 0201 +3.3V R21 100 0201 OUT-ENABLE1 U3 FIN1108 5 VDD GND 15 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 VDD A B C D DEMO MANUAL DC1762A Schematic Diagram dc1762afb 9 DEMO MANUAL DC1762A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation dc1762afb 10 Linear Technology Corporation LT 0912 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2011