LT1167CS8-1#TRPBF

LT1167 Single Resistor Gain Programmable, Precision Instrumentation Amplifier DESCRIPTION FEATURES n n n n n n n n n n n n n n Single Gain Set Resistor: G = 1 to 10,000 Gain Error: G = 10, 0.08% Max Input Offset Voltage Drift: 0.3μV/°C Max Meets IEC 1000-4-2 Level 4 ESD Tests with Two External 5k Resistors Gain Nonlinearity: G = 10, 10ppm Max Input Offset Voltage: G = 10, 60μV Max Input Bias Current: 350pA Max PSRR at G = 1: 105dB Min CMRR at G = 1: 90dB Min Supply Current: 1.3mA Max Wide Supply Range: ±2.3V to ±18V 1kHz Voltage Noise: 7.5nV/√Hz 0.1Hz to 10Hz Noise: 0.28μVP-P Available in 8-Pin PDIP and SO Packages The LT ®1167 is a low power, precision instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. The low voltage noise of 7.5nV/√Hz (at 1kHz) is not compromised by low power dissipation (0.9mA typical for ± 2.3V to ±15V supplies). The part’s high accuracy (10ppm maximum nonlinearity, 0.08% max gain error (G = 10)) is not degraded even for load resistors as low as 2k. The LT1167 is laser trimmed for very low input offset voltage (40μV max), drift (0.3μV/°C), high CMRR (90dB, G = 1) and PSRR (105dB, G = 1). Low input bias currents of 350pA max are achieved with the use of superbeta processing. The output can handle capacitive loads up to 1000pF in any gain configuration while the inputs are ESD protected up to 13kV (human body). The LT1167 with two external 5k resistors passes the IEC 1000-4-2 level 4 specification. The LT1167, offered in 8-pin PDIP and SO packages, requires significantly less PC board area than discrete multi op amp and resistor designs. The LT1167-1 offers the same performance as the LT1167, but its input current characteristic at high common mode voltage better supports applications with high input impedance (see the Applications Information section). APPLICATIONS n ■ ■ ■ ■ Bridge Amplifiers Strain Gauge Amplifiers Thermocouple Amplifiers Differential to Single-Ended Converters Medical Instrumentation L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Single Supply Barometer VS 3 2 LT1634CCZ-1.25 2 8 + 1/2 LT1490 1 Gain Nonlinearity LUCAS NOVA SENOR NPC-1220-015-A-3L – 4 1 – 4 5k R6 1k 5 6 R8 100k + – 5k 2 7 R2 12Ω 5k + 3 6 LT1167 G = 60 8 3 5 + TO 4-DIGIT DVM 4 5 1/2 LT1490 – 2 1 R1 825Ω RSET R3 50k 1 5k 6 OFFSET R4 ADJUST 50k VS NONLINEARITY (100ppm/DIV) R5 392k OUTPUT VOLTAGE (2V/DIV) G = 1000 RL = 1k VOUT = ±10V 7 R7 50k 0.2% ACCURACY AT 25°C 1.2% ACCURACY AT 0°C TO 60°C VS = 8V TO 30V VOLTS 2.800 3.000 3.200 INCHES Hg 28.00 30.00 32.00 1167 TA02 1167 TA01 1167fc 1 LT1167 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Supply Voltage ...................................................... ± 20V Differential Input Voltage (Within the Supply Voltage) ......................................................±40V Input Voltage (Equal to Supply Voltage)................. ± 20V Input Current (Note 3)..........................................±20mA Output Short-Circuit Duration ......................... Indefinite Operating Temperature Range ................. –40°C to 85°C Specified Temperature Range LT1167AC/LT1167C/ LT1167AC-1/LT1167C-1 (Note 4) ............ 0°C to 70°C LT1167AI/LT1167I/ LT1167AI-1/LT1167I-1 ........................ –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C TOP VIEW RG 1 8 RG –IN 2 – 7 +VS +IN 3 + 6 OUTPUT 5 REF –VS 4 N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 130°C/W (N8) TJMAX = 150°C, θJA = 190°C/W (S8) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1167ACN8#PBF LT1167ACN8#TRPBF LT1167AC 8-Lead PDIP 0°C to 70°C LT1167ACS8#PBF LT1167ACS8#TRPBF 1167A 8-Lead Plastic SO 0°C to 70°C LT1167AIN8#PBF LT1167AIN8#TRPBF LT1167AI 8-Lead PDIP –40°C to 85°C LT1167AIS8#PBF LT1167AIS8#TRPBF 1167AI 8-Lead Plastic SO –40°C to 85°C LT1167CN8#PBF LT1167CN8#TRPBF LT1167C 8-Lead PDIP 0°C to 70°C LT1167CS8#PBF LT1167CS8#TRPBF 1167 8-Lead Plastic SO 0°C to 70°C LT1167IN8#PBF LT1167IN8#TRPBF LT1167I 8-Lead PDIP –40°C to 85°C LT1167IS8#PBF LT1167IS8#TRPBF 1167I 8-Lead Plastic SO –40°C to 85°C LT1167CS8-1#PBF LT1167CS8-1#TRPBF 11671 8-Lead Plastic SO 0°C to 70°C LT1167IS8-1#PBF LT1167IS8-1#TRPBF 11671 8-Lead Plastic SO –40°C to 85°C LT1167ACS8-1#PBF LT1167ACS8-1#TRPBF 11671 8-Lead Plastic SO 0°C to 70°C LT1167AIS8-1#PBF LT1167AIS8-1#TRPBF 11671 8-Lead Plastic SO –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1167ACN8 LT1167ACN8#TR LT1167AC 8-Lead PDIP 0°C to 70°C LT1167ACS8 LT1167ACS8#TR 1167A 8-Lead Plastic SO 0°C to 70°C LT1167AIN8 LT1167AIN8#TR LT1167AI 8-Lead PDIP –40°C to 85°C LT1167AIS8 LT1167AIS8#TR 1167AI 8-Lead Plastic SO –40°C to 85°C LT1167CN8 LT1167CN8#TR LT1167C 8-Lead PDIP 0°C to 70°C LT1167CS8 LT1167CS8#TR 1167 8-Lead Plastic SO 0°C to 70°C LT1167IN8 LT1167IN8#TR LT1167I 8-Lead PDIP –40°C to 85°C LT1167IS8 LT1167IS8#TR 1167I 8-Lead Plastic SO –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1167fc 2 LT1167 ELECTRICAL CHARACTERISTICS VS = ±15V, VCM = 0V, TA = 25°C, RL = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS (NOTE 7) G Gain Range G = 1 + (49.4k/RG) Gain Error G=1 G = 10 (Note 2) G = 100 (Note 2) G = 1000 (Note 2) Gain Nonlinearity (Note 5) LT1167AC/LTC1167AI LT1167AC-1/LTC1167AI-1 MIN TYP MAX 1 10k LT1167C/LTC1167I LT1167C-1/LTC1167I-1 MIN TYP MAX 1 UNITS 10k 0.008 0.010 0.025 0.049 0.02 0.08 0.08 0.10 0.015 0.020 0.030 0.040 0.03 0.10 0.10 0.10 % % % % VO = ±10V, G = 1 VO = ±10V, G = 10 and 100 VO = ±10V, G = 1000 1 2 15 6 10 40 1.5 3 20 10 15 60 ppm ppm ppm VO = ±10V, G = 1, RL = 600 VO = ±10V, G = 10 and 100, RL = 600 VO = ±10V, G = 1000, RL = 600 5 6 12 15 6 7 15 20 ppm ppm 20 65 25 80 ppm 20 60 μV VOST Total Input Referred Offset Voltage VOST = VOSI + VOSO/G VOSI Input Offset Voltage G = 1000, VS = ±5V to ±15V 15 40 VOSO Output Offset Voltage G = 1, VS = ±5V to ±15V 40 200 50 300 μV IOS Input Offset Current 90 320 100 450 pA IB Input Bias Current 50 350 80 500 en Input Noise Voltage (Note 8) 0.1Hz to 10Hz, G = 1 0.1Hz to 10Hz, G = 10 0.1Hz to 10Hz, G = 100 and 1000 2.00 0.50 0.28 2.00 0.50 0.28 pA μVP-P μVP-P μVP-P Total RTI Noise = √eni2 + (eno/G)2 (Note 8) eni Input Noise Voltage Density (Note 8) fO = 1kHz 7.5 12 7.5 12 nV/√Hz eno Output Noise Voltage Density (Note 8) fO = 1kHz (Note 3) 67 90 67 90 nV/√Hz in Input Noise Current fO = 0.1Hz to 10Hz 10 10 pAP-P Input Noise Current Densty fO = 10Hz 124 124 fA/√Hz RIN Input Resistance VIN = ±10V 1000 GΩ CIN(DIFF) Differential Input Capacitance fO = 100kHz 1.6 1.6 pF CIN(CM) Common Mode Input Capacitance fO = 100kHz 1.6 1.6 pF VCM Input Voltage Range G = 1, Other Input Grounded VS = ±2.3V to ±5V VS = ±5V to ±18V CMRR PSRR Common Mode Rejection Ratio Power Supply Rejection Ratio 200 1000 –VS + 1.9 –VS + 1.9 200 +VS – 1.2 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.2 +VS – 1.4 V V 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 90 106 120 126 95 115 125 140 85 100 110 120 95 115 125 140 dB dB dB dB VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 105 125 131 135 120 135 140 150 100 120 126 130 120 135 140 150 dB dB dB dB IS Supply Current VS = ±2.3V to ±18V VOUT Output Voltage Swing RL = 10k VS = ±2.3V to ±5V VS = ±5V to ±18V 0.9 –VS + 1.1 –VS + 1.2 1.3 +VS – 1.2 –VS + 1.1 +VS – 1.3 –VS + 1.2 0.9 1.3 +VS – 1.2 +VS – 1.3 mA V V 1167fc 3 LT1167 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Output Current BW Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1, VOUT = ±10V Settling Time to 0.01% 10V Step G = 1 to 100 G = 1000 RREFIN Reference Input Resistance IREFIN Reference Input Current VREF Reference Voltage Range AVREF Reference Gain to Output LT1167AC/LTC1167AI LT1167AC-1/LTC1167AI-1 MIN TYP MAX CONDITIONS (NOTE 7) IOUT SR VS = ±15V, VCM = 0V, TA = 25°C, RL = 2k, unless otherwise noted. 20 27 LT1167C/LTC1167I LT1167C-1/LTC1167I-1 MIN TYP MAX 20 27 mA 1000 800 120 12 kHz kHz kHz kHz 1.2 V/μs 14 130 14 130 μs μs 20 20 kΩ 1000 800 120 12 0.75 VREF = 0V UNITS 1.2 0.75 50 –VS + 1.6 50 +VS – 1.6 –VS + 1.6 1 ±0.0001 μA +VS – 1.6 V 1 ±0.0001 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, RL = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS (NOTE 7) LT1167AC/LT1167AC-1 MIN TYP MAX LT1167C/LT1167C-1 MIN TYP MAX UNITS Gain Error G=1 G = 10 (Note 2) G = 100 (Note 2) G = 1000 (Note 2) l l l l 0.01 0.08 0.09 0.14 0.03 0.30 0.30 0.33 0.012 0.100 0.120 0.140 0.04 0.33 0.33 0.35 Gain Nonlinearity l VOUT = ±10V, G = 1 VOUT = ±10V, G = 10 and 100 l l VOUT = ±10V, G = 1000 1.5 3 20 10 15 60 3 4 25 15 20 80 ppm ppm ppm G/T Gain vs Temperature G < 1000 (Note 2) l 20 50 20 50 ppm/°C VOST Total Input Referred Offset Voltage VOST = VOSI + VOSO/G VOSI Input Offset Voltage VS = ±5V to ±15V l 18 60 23 80 μV VOSIH Input Offset Voltage Hysteresis (Notes 3, 6) VOSO Output Offset Voltage VS = ±5V to ±15V 500 μV VOSOH Output Offset Voltage Hysteresis (Notes 3, 6) 3.0 l 60 3.0 380 70 30 % % % % μV 30 μV VOSI/T Input Offset Drift (Note 8) (Note 3) l 0.05 0.3 0.06 0.4 μV/°C VOSO/T Output Offset Drift (Note 3) l 0.7 3 0.8 4 μV/°C 400 120 550 IOS Input Offset Current l 100 IOS/T Input Offset Current Drift l 0.3 IB Input Bias Current l 75 IB/T Input Bias Current Drift l 0.4 VCM Input Voltage Range CMRR Common Mode Rejection Ratio G = 1, Other Input Grounded VS = ±2.3V to ±5V VS = ±5V to ±18V l l –VS+2.1 –VS+2.1 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 l l l l 88 100 115 117 0.4 450 600 0.4 +VS–1.3 +VS–1.4 92 110 120 135 105 –VS+2.1 –VS+2.1 83 97 113 114 pA pA/°C +VS–1.3 +VS–1.4 92 110 120 135 pA pA/°C V V dB dB dB dB 1167fc 4 LT1167 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, RL = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS (NOTE 7) PSRR VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 l l l l Power Supply Rejection Ratio IS Supply Current VS = ±2.3V to ±18V l VOUT Output Voltage Swing RL = 10k VS = ±2.3V to ±5V VS = ±5V to ±18V l l IOUT Output Current SR Slew Rate VREF REF Voltage Range LT1167AC/LT1167AC-1 MIN TYP MAX LT1167C/LT1167C-1 MIN TYP MAX 103 123 127 129 98 118 124 126 115 130 135 145 1.0 –VS +1.4 –VS +1.6 1.5 UNITS 115 130 135 145 1.0 +VS –1.3 –VS+1.4 +VS –1.5 –VS+1.6 dB dB dB dB 1.5 mA +VS –1.3 +VS –1.5 V V l 16 21 16 21 mA G = 1, VOUT = ±10V l 0.65 1.1 0.65 1.1 V/μs (Note 3) l –VS +1.6 +VS –1.6 –VS +1.6 +VS –1.6 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V, –40°C ≤ TA ≤ 85°C, RL = 2k, unless otherwise noted. SYMBOL PARAMETER GN CONDITIONS (NOTE 7) LT1167AI/LT1167AI-1 MIN TYP MAX LT1167I/LT1167I-1 MIN TYP MAX UNITS Gain Error G=1 G = 10 (Note 2) G = 100 (Note 2) G = 1000 (Note 2) l l l l 0.014 0.130 0.140 0.160 0.04 0.40 0.40 0.40 0.015 0.140 0.150 0.180 0.05 0.42 0.42 0.45 % % % % Gain Nonlinearity (Notes 2, 4) VO = ±10V, G = 1 VO = ±10V, G = 10 and 100 VO = ±10V, G = 1000 l l l 2 5 26 15 20 70 3 6 30 20 30 100 ppm ppm ppm l 20 50 20 50 ppm/°C 20 75 25 100 μV G/T Gain vs Temperature G < 1000 (Note 2) VOST Total Input Referred Offset Voltage VOST = VOSI + VOSO/G VOSI Input Offset Voltage VOSIH Input Offset Voltage Hysteresis VOSO Output Offset Voltage VOSOH Output Offset Voltage Hysteresis (Notes 3, 6) VOSI/T Input Offset Drift (Note 8) (Note 3) l (Note 3) l (Notes 3, 6) 3.0 l 180 3.0 500 200 30 0.05 μV 600 30 0.3 0.06 μV 0.4 μV/°C μV/°C VOSO/T Output Offset Drift l 0.8 5 1 6 IOS Input Offset Current l 110 550 120 700 IOS/T Input Offset Current Drift l 0.3 IB Input Bias Current l 180 IB/T Input Bias Current Drift l 0.5 VCM Input Voltage Range VS = ±2.3V to ±5V VS = ±5V to ±18V l l –VS+2.1 –VS+2.1 CMRR Common Mode Rejection Ratio 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 l l l l 86 98 114 116 0.3 600 –VS+2.1 –VS+2.1 81 95 112 112 800 pA pA/°C +VS–1.3 +VS–1.4 90 105 118 133 pA pA/°C 0.6 +VS–1.3 +VS–1.4 90 105 118 133 220 μV V V dB dB dB dB 1167fc 5 LT1167 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, RL = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS (NOTE 7) PSRR VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 Power Supply Rejection Ratio IS Supply Current VOUT Output Voltage Swing IOUT Output Current l l l l LT1167AI/LT1167AI-1 MIN TYP MAX LT1167I/LT1167I-1 MIN TYP MAX 100 120 125 128 95 115 120 125 l VS = ±2.3V to ±5V VS = ±5V to ±18V 1.1 l l –VS +1.4 –VS +1.6 l 15 20 0.95 SR Slew Rate G = 1, VOUT = ±10V l 0.55 VREF REF Voltage Range (Note 3) l –VS +1.6 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Does not include the effect of the external gain resistor RG. Note 3: This parameter is not 100% tested. Note 4: The LT1167AC/LT1167C/LT1167AC-1/LT1167C-1 are designed, characterized and expected to meet the industrial temperature limits, but are not tested at –40°C and 85°C. I-grade parts are guaranteed. Note 5: This parameter is measured in a high speed automatic tester that does not measure the thermal effects with longer time constants. The magnitude of these thermal effects are dependent on the package used, heat sinking and air flow conditions. 112 125 132 140 1.6 112 125 132 140 1.1 +VS –1.3 –VS +1.4 +VS –1.5 –VS +1.6 dB dB dB dB 1.6 mA +VS –1.3 +VS –1.5 15 20 0.55 0.95 +VS –1.6 –VS +1.6 UNITS V V mA V/μs +VS –1.6 V Note 6: Hysteresis in offset voltage is created by package stress that differs depending on whether the IC was previously at a higher or lower temperature. Offset voltage hysteresis is always measured at 25°C, but the IC is cycled to 85°C I-grade (or 70°C C-grade) or –40°C I-grade (0°C C-grade) before successive measurement. 60% of the parts will pass the typical limit on the data sheet. Note 7: Typical parameters are defined as the 60% of the yield parameter distribution. Note 8: Referred to input. 1167fc 6 LT1167 TYPICAL PERFORMANCE CHARACTERISTICS Gain Nonlinearity, G = 100 NONLINEARITY (10ppm/DIV) Gain Nonlinearity, G = 10 NONLINEARITY (1ppm/DIV) NONLINEARITY (10ppm/DIV) Gain Nonlinearity, G = 1 1167 G01 Gain Nonlinearity, G = 1000 NONLINEARITY (100ppm/DIV) NONLINEARITY (ppm) 70 1167 G03 G = 100 OUTPUT VOLTAGE (2V/DIV) RL = 2k VOUT = ±10V Gain Nonlinearity vs Temperature 80 G = 1000 OUTPUT VOLTAGE (2V/DIV) RL = 2k VOUT = ±10V 1167 G02 G = 10 OUTPUT VOLTAGE (2V/DIV) RL = 2k VOUT = ±10V Gain Error vs Temperature 0.20 VS = ±15V VOUT = – 10V TO 10V RL = 2k 0.15 60 0.10 GAIN ERROR (%) G=1 OUTPUT VOLTAGE (2V/DIV) RL = 2k VOUT = ±10V 50 40 30 G = 1000 20 0.05 G=1 0 – 0.05 – 0.10 1167 G04 G = 1, 10 10 – 0.15 G = 100 0 – 50 – 25 75 50 25 TEMPERATURE (°C) 0 100 150 VS = ±15V G = 10* VOUT = ±10V RL = 2k G = 100* *DOES NOT INCLUDE G = 1000* TEMPERATURE EFFECTS OF RG – 0.20 – 50 – 25 0 25 50 TEMPERATURE (°C) 1167 G05 40 Distribution of Input Offset Voltage, TA = 25°C 30 137 N8 (2 LOTS) 165 S8 (3 LOTS) 302 TOTAL PARTS 30 25 20 15 10 Distribution of Input Offset Voltage, TA = 85°C 60 20 15 10 1167 G40 0 – 60 40 137 N8 (2 LOTS) 165 S8 (3 LOTS) 302 TOTAL PARTS 5 5 0 0 – 80 – 60 – 40 – 20 20 40 INPUT OFFSET VOLTAGE (μV) VS = ±15V G = 1000 25 PERCENT OF UNITS (%) PERCENT OF UNITS (%) 35 VS = ±15V G = 1000 1167 G06 35 PERCENT OF UNITS (%) Distribution of Input Offset Voltage, TA = – 40°C 100 75 VS = ±15V G = 1000 137 N8 (2 LOTS) 165 S8 (3 LOTS) 302 TOTAL PARTS 30 25 20 15 10 5 – 40 – 20 0 20 40 INPUT OFFSET VOLTAGE (μV) 60 1167 G41 0 0 – 80 – 60 – 40 – 20 20 40 INPUT OFFSET VOLTAGE (μV) 60 1167 G42 1167fc 7 LT1167 TYPICAL PERFORMANCE CHARACTERISTICS Distribution of Output Offset Voltage, TA = – 40°C 30 30 25 20 15 10 40 VS = ±15V G=1 137 N8 (2 LOTS) 165 S8 (3 LOTS) 25 302 TOTAL PARTS VS = ±15V G=1 PERCENT OF UNITS (%) 137 N8 (2 LOTS) 35 165 S8 (3 LOTS) 302 TOTAL PARTS Distribution of Output Offset Voltage, TA = 85°C 20 15 10 5 5 0 – 0.4 – 0.3 – 0.2 – 0.1 0 0.1 0.2 0.3 INPUT OFFSET VOLTAGE DRIFT (μV/°C) 137 N8 (2 LOTS) 165 S8 (3 LOTS) 302 TOTAL PARTS 30 25 20 15 10 0 14 8 N8 6 4 2 0 VS = ±15V TA = 25°C PERCENT OF UNITS (%) 40 270 S8 122 N8 392 TOTAL PARTS 30 20 10 – 60 20 60 – 20 INPUT BIAS CURRENT (pA) 100 1167 G10 0 – 100 5 Input Bias and Offset Current vs Temperature – 60 20 60 – 20 INPUT OFFSET CURRENT (pA) 100 1167 G11 500 INPUT BIAS AND OFFSET CURRENT (pA) 50 270 S8 122 N8 392 TOTAL PARTS 10 1 2 3 4 TIME AFTER POWER ON (MINUTES) 1167 G09 Input Offset Current 20 S8 10 1167 G47 Input Bias Current 30 VS = ±15V TA = 25°C G=1 12 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 OUTPUT OFFSET VOLTAGE DRIFT (μV/°C) 1167 G46 PERCENT OF UNITS (%) Warm-Up Drift 5 0 – 100 1167 G45 CHANGE IN OFFSET VOLTAGE (μV) VS = ±15V TA = – 40°C TO 85°C G=1 35 PERCENT OF UNITS (%) PERCENT OF UNITS (%) 10 40 –400 –300 –200 –100 0 100 200 300 400 OUTPUT OFFSET VOLTAGE (μV) 40 137 N8 (2 LOTS) 165 S8 (3 LOTS) 302 TOTAL PARTS 15 VS = ±15V TA = 25°C 10 Distribution of Output Offset Voltage Drift 20 50 15 1167 G44 Distribution of Input Offset Voltage Drift 25 20 – 200 –150 –100 –50 0 50 100 150 200 OUTPUT OFFSET VOLTAGE (μV) 1167 G43 VS = ±15V TA = – 40°C TO 85°C G = 1000 25 0 0 –400 –300 –200 –100 0 100 200 300 400 OUTPUT OFFSET VOLTAGE (μV) 30 30 5 5 0 VS = ±15V G=1 137 N8 (2 LOTS) 35 165 S8 (3 LOTS) 302 TOTAL PARTS PERCENT OF UNITS (%) 40 PERCENT OF UNITS (%) Distribution of Output Offset Voltage, TA = 25°C 400 VS = ±15V VCM = 0V 300 200 100 IOS 0 IB – 100 – 200 – 300 – 400 – 500 –75 – 50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1167 G12 1167fc 8 LT1167 Input Bias Current vs Common Mode Input Voltage Common Mode Rejection Ratio vs Frequency 500 COMMON MODE REJECTION RATIO (dB) 160 INPUT BIAS CURRENT (pA) 400 300 200 100 0 70°C 85°C –100 – 200 0°C – 300 – 40°C 25°C – 400 140 120 G = 100 G = 10 100 G=1 80 60 40 20 0 0.1 – 500 –15 –12 – 9 – 6 – 3 0 3 6 9 12 15 COMMON MODE INPUT VOLTAGE (V) VS = ±15V TA = 25°C 1k SOURCE IMBALANCE G = 1000 1 10 1k 100 FREQUENCY (Hz) 10k TA = 25°C 80 60 –10 10k 100k G = 10 10 20 1k 100 FREQUENCY (Hz) G = 100 20 0 10 G = 10 100 G=1 G = 1000 80 60 40 20 0 0.1 1 10 1k 100 FREQUENCY (Hz) 10k 100k Supply Current vs Supply Voltage 30 40 1 120 V + = 15V TA = 25°C 1.50 SUPPLY CURRENT (mA) G=1 0 0.1 G = 100 1167 G15 G = 1000 40 G = 100 100 140 50 G = 1000 G = 10 120 160 Gain vs Frequency 60 V – = – 15V GAIN (dB) POSITIVE POWER SUPPLY REJECTION RATIO (dB) Positive Power Supply Rejection Ratio vs Frequency 140 Negative Power Supply Rejection Ratio vs Frequency 1167 G14 1167 G13 160 100k NEGATIVE POWER SUPPLY REJECTION RATIO (dB) TYPICAL PERFORMANCE CHARACTERISTICS G=1 1.25 85°C 25°C 1.00 – 40°C 0.75 VS = ±15V TA = 25°C – 20 0.01 0.1 1 10 FREQUENCY (kHz) 100 1000 0.50 0 5 10 15 SUPPLY VOLTAGE ( V) 20 1167 G17 1167 G16 Voltage Noise Density vs Frequency 1167 G18 0.1Hz to 10Hz Noise Voltage, G=1 0.1Hz to 10Hz Noise Voltage, Referred to Input, G = 1000 VS = ±15V TA = 25°C 1/fCORNER = 10Hz 100 GAIN = 1 1/fCORNER = 9Hz GAIN = 10 1/fCORNER = 7Hz 10 GAIN = 100, 1000 VS = ±15V TA = 25°C NOISE VOLTAGE (0.2μV/DIV) VS = ±15V TA = 25°C NOISE VOLTAGE (2μV/DIV) VOLTAGE NOISE DENSITY (nV√Hz) 1000 BW LIMIT GAIN = 1000 0 1 10 100 1k FREQUENCY (Hz) 10k 100k 1167 G19 0 1 2 3 4 5 6 TIME (SEC) 7 8 9 10 1167 G20 0 1 2 3 4 5 6 TIME (SEC) 7 8 9 10 1167 G21 1167fc 9 LT1167 TYPICAL PERFORMANCE CHARACTERISTICS Current Noise Density vs Frequency 0.1Hz to 10Hz Current Noise Short-Circuit Current vs Time 50 VS = ±15V TA = 25°C VS = ±15V TA = 25°C OUTPUT CURRENT (mA) (SINK) (SOURCE) 100 RS VS = ±15V 40 CURRENT NOISE (5pA/DIV) CURRENT NOISE DENSITY (fA/√Hz) 1000 TA = – 40°C 30 TA = 25°C 20 TA = 85°C 10 0 – 10 TA = 85°C – 20 – 30 TA = – 40°C – 40 10 10 100 FREQUENCY (Hz) 1 1000 TA = 25°C – 50 1 0 2 3 4 5 6 TIME (SEC) 7 1167 G22 8 9 10 2 1 0 3 TIME FROM OUTPUT SHORT TO GROUND (MINUTES) 1167 G24 1167 G23 Overshoot vs Capacitive Load Large-Signal Transient Response Small-Signal Transient Response 100 70 5V/DIV OVERSHOOT (%) 80 20mV/DIV VS = ±15V VOUT = ±50mV RL = ∞ 90 60 50 AV = 1 40 30 AV = 10 20 10 G=1 VS = ±15V RL = 2k CL = 60pF AV ≥ 100 0 10 100 1000 CAPACITIVE LOAD (pF) 10000 10μs/DIV 1167 G28 G=1 VS = ±15V RL = 2k CL = 60pF 10μs/DIV 1167 G29 1167 G25 Output Impedance vs Frequency Small-Signal Transient Response VS = ±15V TA = 25°C G = 1 TO 1000 20mV/DIV 100 5V/DIV OUTPUT IMPEDANCE (Ω) 1000 Large-Signal Transient Response 10 1 0.1 1 10 100 FREQUENCY (kHz) 1000 G=1 VS = ±15V RL = 2k CL = 60pF 10μs/DIV 1167 G31 G = 10 VS = ±15V RL = 2k CL = 60pF 10μs/DIV 1167 G32 1167 G26 1167fc 10 LT1167 TYPICAL PERFORMANCE CHARACTERISTICS Undistorted Output Swing vs Frequency Large-Signal Transient Response Small-Signal Transient Response 20mV/DIV VS = ±15V TA = 25°C 30 G = 10, 100, 1000 G=1 25 5V/DIV PEAK-TO-PEAK OUTPUT SWING (V) 35 20 15 10 5 G = 100 VS = ±15V RL = 2k CL = 60pF 0 10 100 FREQUENCY (kHz) 1 1000 1167 G34 10μs/DIV G = 100 VS = ±15V RL = 2k CL = 60pF 10μs/DIV 1167 G35 1167 G27 Settling Time vs Gain Large-Signal Transient Response Small-Signal Transient Response 100 20mV/DIV VS = ±15V TA = 25°C ΔVOUT = 10V 1mV = 0.01% 5V/DIV SETTLING TIME (μs) 1000 10 G = 1000 VS = ±15V RL = 2k CL = 60pF 1 1 10 100 1000 1167 G37 50μs/DIV G = 1000 VS = ±15V RL = 2k CL = 60pF 50μs/DIV 1167 G38 GAIN (dB) 1167 G30 VS = ±15 G=1 TA = 25°C CL = 30pF RL = 1k 8 OUTPUT STEP (V) 6 4 2 1.8 TO 0.1% 1.6 0V VOUT 0 0V –2 –4 VOUT TO 0.01% –6 –8 –10 + VS VS = ±15V VOUT = ±10V G=1 TO 0.01% SLEW RATE (V/μs) 10 Output Voltage Swing vs Load Current Slew Rate vs Temperature OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGE) Settling Time vs Step Size 1.4 + SLEW 1.2 – SLEW 1.0 TO 0.1% 2 3 4 5 6 7 8 9 SETTLING TIME (μs) 10 11 12 1167 G33 0.8 – 50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 1167 G36 85°C 25°C – 40°C VS = ±15V + VS – 0.5 + VS – 1.0 + VS – 1.5 SOURCE + VS – 2.0 – VS + 2.0 – VS + 1.5 SINK – VS + 1.0 – VS + 0.5 – VS 0.01 0.1 1 10 OUTPUT CURRENT (mA) 100 1167 G39 1167fc 11 LT1167 BLOCK DIAGRAM V+ VB R5 10k + R6 10k 6 OUTPUT A1 – R3 400Ω –IN C1 2 Q1 R1 24.7k V – – + A3 RG 1 RG 8 V V– VB + R7 10k + R8 10k 5 REF A2 – R4 400Ω +IN 3 C2 V– Q2 R2 24.7k 7 V+ 4 V– V– PREAMP STAGE DIFFERENCE AMPLIFIER STAGE 1167 F01 Figure 1. Block Diagram THEORY OF OPERATION The LT1167 is a modified version of the three op amp instrumentation amplifier. Laser trimming and monolithic construction allow tight matching and tracking of circuit parameters over the specified temperature range. Refer to the block diagram (Figure 1) to understand the following circuit description. The collector currents in Q1 and Q2 are trimmed to minimize offset voltage drift, thus assuring a high level of performance. R1 and R2 are trimmed to an absolute value of 24.7k to assure that the gain can be set accurately (0.05% at G = 100) with only one external resistor RG. The value of RG determines the transconductance of the preamp stage. As RG is reduced for larger programmed gains, the transconductance of the input preamp stage increases to that of the input transistors Q1 and Q2. This increases the open-loop gain when the programmed gain is increased, reducing the input referred gain related errors and noise. The input voltage noise at gains greater than 50 is determined only by Q1 and Q2. At lower gains the noise of the difference amplifier and preamp gain setting resistors increase the noise. The gain bandwidth product is determined by C1, C2 and the preamp transconductance which increases 12 with programmed gain. Therefore, the bandwidth does not drop proportionally to gain. The input transistors Q1 and Q2 offer excellent matching, which is inherent in NPN bipolar transistors, as well as picoampere input bias current due to superbeta processing. The collector currents in Q1 and Q2 are held constant due to the feedback through the Q1-A1-R1 loop and Q2-A2-R2 loop which in turn impresses the differential input voltage across the external gain set resistor RG. Since the current that flows through RG also flows through R1 and R2, the ratios provide a gained-up differential voltage, G = (R1 + R2)/RG, to the unity-gain difference amplifier A3. The common mode voltage is removed by A3, resulting in a single-ended output voltage referenced to the voltage on the REF pin. The resulting gain equation is: VOUT – VREF = G(VIN+ – VIN–) where: G = (49.4kΩ / RG) + 1 solving for the gain set resistor gives: RG = 49.4kΩ /(G – 1) 1167fc LT1167 THEORY OF OPERATION Input and Output Offset Voltage Output Offset Trimming The offset voltage of the LT1167 has two components: the output offset and the input offset. The total offset voltage referred to the input (RTI) is found by dividing the output offset by the programmed gain (G) and adding it to the input offset. At high gains the input offset voltage dominates, whereas at low gains the output offset voltage dominates. The total offset voltage is: The LT1167 is laser trimmed for low offset voltage so that no external offset trimming is required for most applications. In the event that the offset needs to be adjusted, the circuit in Figure 2 is an example of an optional offset adjust circuit. The op amp buffer provides a low impedance to the REF pin where resistance must be kept to minimum for best CMRR and lowest gain error. 2 –IN – 1 Total output offset voltage (RTO) = (input offset • G) + output offset RG 3 + V+ 5 – The reference terminal is one end of one of the four 10k resistors around the difference amplifier. The output voltage of the LT1167 (Pin 6) is referenced to the voltage on the reference terminal (Pin 5). Resistance in series with the REF pin must be minimized for best common mode rejection. For example, a 2Ω resistance from the REF pin to ground will not only increase the gain error by 0.02% but will lower the CMRR to 80dB. +IN OUTPUT REF 8 Reference Terminal 6 LT1167 1 ±10mV ADJUSTMENT RANGE 1/2 LT1112 + Total input offset voltage (RTI) = input offset + (output offset/G) 2 10mV 100Ω 3 10k 100Ω –10mV V– 1167 F02 Figure 2. Optional Trimming of Output Offset Voltage Single Supply Operation Input Bias Current Return Path For single supply operation, the REF pin can be at the same potential as the negative supply (Pin 4) provided the output of the instrumentation amplifier remains inside the specified operating range and that one of the inputs is at least 2.5V above ground. The barometer application on the front page of this data sheet is an example that satisfies these conditions. The resistance Rb from the bridge transducer to ground sets the operating current for the bridge and also has the effect of raising the input common mode voltage. The output of the LT1167 is always inside the specified range since the barometric pressure rarely goes low enough to cause the output to rail (30.00 inches of Hg corresponds to 3.000V). For applications that require the output to swing at or below the REF potential, the voltage on the REF pin can be level shifted. An op amp is used to buffer the voltage on the REF pin since a parasitic series resistance will degrade the CMRR. The application in the back of this data sheet, Four Digit Pressure Sensor, is an example. The low input bias current of the LT1167 (350pA) and the high input impedance (200GΩ) allow the use of high impedance sources without introducing additional offset voltage errors, even when the full common mode range is required. However, a path must be provided for the input bias currents of both inputs when a purely differential signal is being amplified. Without this path the inputs will float to either rail and exceed the input common mode range of the LT1167, resulting in a saturated input stage. Figure 3 shows three examples of an input bias current path. The first example is of a purely differential signal source with a 10kΩ input current path to ground. Since the impedance of the signal source is low, only one resistor is needed. Two matching resistors are needed for higher impedance signal sources as shown in the second example. Balancing the input impedance improves both common mode rejection and DC offset. The need for input resistors is eliminated if a center tap is present as shown in the third example. 1167fc 13 LT1167 THEORY OF OPERATION – THERMOCOUPLE RG – LT1167 MICROPHONE, HYDROPHONE, ETC RG – RG LT1167 + + 200k 10k LT1167 + 200k CENTER-TAP PROVIDES BIAS CURRENT RETURN 1167 F03 Figure 3. Providing an Input Common Mode Current Path APPLICATIONS INFORMATION The LT1167 is a low power precision instrumentation amplifier that requires only one external resistor to accurately set the gain anywhere from 1 to 1000. The output can handle capacitive loads up to 1000pF in any gain configuration and the inputs are protected against ESD strikes up to 13kV (human body). resistors are needed, a clamp diode from the positive supply to each input will maintain the IEC 1000-4-2 specification to level 4 for both air and contact discharge. A 2N4393 drain/source to gate is a good low leakage diode for use with 1k resistors, see Figure 4. The input resistors should be carbon and not metal film or carbon film. Input Current at High Common Mode Voltage When operating within the specified input common mode range, both the LT1167 and LT1167-1 operate as shown in the Input Bias Current vs Common Mode Input Voltage graph shown in the Typical Performance Characteristics. If however the inputs are within approximately 0.8V of the positive supply, the LT1167 input current will increase to approximately –1μA to –3μA. If the impedance of the circuit driving the LT1167 inputs is sufficiently high (e.g., 10MΩ when +VS = 15V), this increased input current can pull the input voltage sufficiently high to keep the elevated input current flowing. The LT1167-1 has been modified so that the input current is typically two orders of magnitude lower under similar conditions. The LT1167-1 is recommended for new designs where input impedance is high. Input Protection The LT1167 can safely handle up to ± 20mA of input current in an overload condition. Adding an external 5k input resistor in series with each input allows DC input fault voltages up to ±100V and improves the ESD immunity to 8kV (contact) and 15kV (air discharge), which is the IEC 1000-4-2 level 4 specification. If lower value input VCC VCC J1 2N4393 J2 2N4393 RIN OPTIONAL FOR HIGHEST ESD PROTECTION + RG RIN VCC LT1167 OUT REF – VEE 1167 F04 Figure 4. Input Protection RFI Reduction In many industrial and data acquisition applications, instrumentation amplifiers are used to accurately amplify small signals in the presence of large common mode voltages or high levels of noise. Typically, the sources of these very small signals (on the order of microvolts or millivolts) are sensors that can be a significant distance from the signal conditioning circuit. Although these sensors may be connected to signal conditioning circuitry, using shielded or unshielded twisted-pair cabling, the cabling may act as antennae, conveying very high frequency interference directly into the input stage of the LT1167. 1167fc 14 LT1167 APPLICATIONS INFORMATION The amplitude and frequency of the interference can have an adverse effect on an instrumentation amplifier’s input stage by causing an unwanted DC shift in the amplifier’s input offset voltage. This well known effect is called RFI rectification and is produced when out-of-band interference is coupled (inductively, capacitively or via radiation) and rectified by the instrumentation amplifier’s input transistors. These transistors act as high frequency signal detectors, in the same way diodes were used as RF envelope detectors in early radio designs. Regardless of the type of interference or the method by which it is coupled into the circuit, an out-of-band error signal appears in series with the instrumentation amplifier’s inputs. To significantly reduce the effect of these out-of-band signals on the input offset voltage of instrumentation amplifiers, simple lowpass filters can be used at the inputs. These filters should be located very close to the input pins of the circuit. An effective filter configuration is illustrated in Figure 5, where three capacitors have been added to the inputs of the LT1167. Capacitors CXCM1 and CXCM2 form lowpass filters with the external series resistors RS1, 2 to any out-of-band signal appearing on each of the input traces. Capacitor CXD forms a filter to reduce any unwanted signal that would appear across the input traces. An added benefit to using CXD is that the circuit’s AC common mode rejection is not degraded due to common mode capacitive IN + CXD 0.1μF IN – V+ RS1 CXCM1 1.6k 0.001μF RS2 1.6k + RG LT1167 VOUT – CXCM2 0.001μF V– f– 3dB ≈ 500Hz 1167 F05 EXTERNAL RFI FILTER Figure 5. Adding a Simple RC Filter at the Inputs to an Instrumentation Amplifier Is Effective in Reducing Rectification of High Frequency Out-of-Band Signals imbalance. The differential mode and common mode time constants associated with the capacitors are: tDM(LPF) = (2)(RS)(CXD) tCM(LPF) = (RS1, 2)(CXCM1, 2) Setting the time constants requires a knowledge of the frequency, or frequencies of the interference. Once this frequency is known, the common mode time constants can be set followed by the differential mode time constant. To avoid any possibility of inadvertently affecting the signal to be processed, set the common mode time constant an order of magnitude (or more) larger than the differential mode time constant. Set the common mode time constants such that they do not degrade the LT1167’s inherent AC CMR. Then the differential mode time constant can be set for the bandwidth required for the application. Setting the differential mode time constant close to the sensor’s BW also minimizes any noise pickup along the leads. To avoid any possibility of common mode to differential mode signal conversion, match the common mode time constants to 1% or better. If the sensor is an RTD or a resistive strain gauge, then the series resistors RS1, 2 can be omitted, if the sensor is in proximity to the instrumentation amplifier. “Roll Your Own”—Discrete vs Monolithic LT1167 Error Budget Analysis The LT1167 offers performance superior to that of “roll your own” three op amp discrete designs. A typical application that amplifies and buffers a bridge transducer’s differential output is shown in Figure 6. The amplifier, with its gain set to 100, amplifies a differential, full-scale output voltage of 20mV over the industrial temperature range. To make the comparison challenging, the low cost version of the LT1167 will be compared to a discrete instrumentation amp made with the A grade of one of the best precision quad op amps, the LT1114A. The LT1167C outperforms the discrete amplifier that has lower VOS, lower IB and comparable VOS drift. The error budget comparison in Table 1 shows how various errors are calculated and how each error affects the total error budget. The table shows the greatest differences between the discrete solution and 1167fc 15 LT1167 APPLICATIONS INFORMATION + + 10V 350Ω – 10k** – 10k** + 350Ω RG 499Ω 350Ω 10k* 10k* 1/4 LT1114A LT1167C 202Ω** REF 350Ω – PRECISION BRIDGE TRANSDUCER 1/4 LT1114A – 1/4 LT1114A 10k* 10k* + LT1167 MONOLITHIC INSTRUMENTATION AMPLIFIER G = 100, RG = ±10ppm TC SUPPLY CURRENT = 1.3mA MAX “ROLL YOUR OWN” INST AMP, G = 100 * 0.02% RESISTOR MATCH, 3ppm/°C TRACKING ** DISCRETE 1% RESISTOR, ±100ppm/°C TC 100ppm TRACKING SUPPLY CURRENT = 1.35mA FOR 3 AMPLIFIERS 1167 F06 Figure 6. “Roll Your Own” vs LT1167 Table 1. “Roll Your Own” vs LT1167 Error Budget ERROR SOURCE LT1167C CIRCUIT CALCULATION “ROLL YOUR OWN”’ CIRCUIT CALCULATION Absolute Accuracy at TA = 25°C Input Offset Voltage, μV Output Offset Voltage, μV Input Offset Current, nA CMR, dB 60μV/20mV (300μV/100)/20mV [(450pA)(350/2)Ω]/20mV 110dB→[(3.16ppm)(5V)]/20mV Drift to 85°C Gain Drift, ppm/°C Input Offset Voltage Drift, μV/°C Output Offset Voltage Drift, μV/°C Resolution Gain Nonlinearity, ppm of Full Scale Typ 0.1Hz to 10Hz Voltage Noise, μVP-P (50ppm + 10ppm)(60°C) [(0.4μV/°C)(60°C)]/20mV [(6μV/°C)(60°C)]/100/20mV 15ppm 0.28μVP-P/20mV ERROR, ppm OF FULL SCALE LT1167C “ROLL YOUR OWN” 100μV/20mV [(60μV)(2)/100]/20mV [(450pA)(350Ω)/2]/20mV [(0.02% Match)(5V)]/20mV 3000 150 4 790 5000 60 4 500 Total Absolute Error 3944 5564 (100ppm/°C Track)(60°C) [(1.6μV/°C)(60°C)]/20mV [(1.1μV/°C)(2)(60°C)]/100/20mV 3600 1200 180 6000 4800 66 Total Drift Error 4980 10866 10ppm (0.3μVP-P)(√2)/20mV 15 14 10 21 Total Resolution Error Grand Total Error 29 8953 31 16461 G = 100, VS = ±15V All errors are min/max and referred to input. the LT1167 are input offset voltage and CMRR. Note that for the discrete solution, the noise voltage specification is multiplied by √2 which is the RMS sum of the uncorelated noise of the two input amplifiers. Each of the amplifier errors is referenced to a full-scale bridge differential voltage of 20mV. The common mode range of the bridge is 5V. The LT1114 data sheet provides offset voltage, offset voltage drift and offset current specifications for the matched op amp pairs used in the error-budget table. Even with an excellent matched op amp like the LT1114, the discrete solution’s total error is significantly higher than the LT1167’s total error. The LT1167 has additional advantages over the discrete design, including lower component cost and smaller size. Current Source Figure 7 shows a simple, accurate, low power programmable current source. The differential voltage across Pins 2 and 3 is mirrored across RG. The voltage across RG is amplified and applied across RX, defining the output current. The 50μA bias current flowing from Pin 5 is buffered by the LT1464 JFET operational amplifier. This 1167fc 16 LT1167 APPLICATIONS INFORMATION RG 7 LT1167 REF 1 2 –IN VX 5 – 4 –V S 1 1/2 LT1464 [(+IN) – (–IN)]G V IL = X = RX RX G= RX 6 + 8 high CMRR ensures that the desired differential signal is amplified and unwanted common mode signals are attenuated. Since the DC portion of the signal is not important, R6 and C2 make up a 0.3Hz highpass filter. The AC signal at LT1112’s Pin 5 is amplified by a gain of 101 set by (R7/R8) +1. The parallel combination of C3 and R7 form a lowpass filter that decreases this gain at frequencies above 1kHz. The ability to operate at ± 3V on 0.9mA of supply current makes the LT1167 ideal for battery-powered applications. Total supply current for this application is 1.7mA. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. VS + – 3 +IN IL 2 3 LOAD 49.4kΩ +1 RG 1167 F07 Figure 7. Precision Voltage-to-Current Converter has the effect of improving the resolution of the current source to 3pA, which is the maximum IB of the LT1464A. Replacing RG with a programmable resistor greatly increases the range of available output currents. Nerve Impulse Amplifier The LT1167’s low current noise makes it ideal for high source impedance EMG monitors. Demonstrating the LT1167’s ability to amplify low level signals, the circuit in Figure 8 takes advantage of the amplifier’s high gain and low noise operation. This circuit amplifies the low level nerve impulse signals received from a patient at Pins 2 and 3. RG and the parallel combination of R3 and R4 set a gain of ten. The potential on LT1112’s Pin 1 creates a ground for the common mode signal. C1 was chosen to maintain the stability of the patient ground. The LT1167’s 3 8 +IN R3 30k R1 12k R2 1M R4 30k – –IN 1 1/2 LT1112 + PATIENT GROUND + 0.3Hz HIGHPASS 7 3V C2 0.47μF RG 6k 6 LT1167 G = 10 1 2 2 The LT1167’s low supply current, low supply voltage operation and low input bias currents optimize it for battery-powered applications. Low overall power dissipation necessitates using higher impedance bridges. The single supply pressure monitor application (Figure 9) shows the LT1167 connected to the differential output of a 3.5k bridge. The bridge’s impedance is almost an order of magnitude higher than that of the bridge used in the error-budget table. The picoampere input bias currents keep the error caused by offset current to a negligible level. The LT1112 level shifts the LT1167’s reference pin and the ADC’s analog ground pins above ground. The LT1167’s and LT1112’s combined power dissipation is still less than the bridge’s. This circuit’s total supply current is just 2.8mA. 3V PATIENT/CIRCUIT PROTECTION/ISOLATION C1 0.01μF Low IB Favors High Impedance Bridges, Lowers Dissipation 5 – 5 R6 1M 4 6 + 8 1/2 LT1112 – 4 –3V –3V 3 AV = 101 POLE AT 1kHz 7 OUTPUT 1V/mV R7 10k R8 100Ω C3 15nF 1167 F08 Figure 8. Nerve Impulse Amplifier 1167fc 17 LT1167 APPLICATIONS INFORMATION BI TECHNOLOGIES 67-8-3 R40KQ (0.02% RATIO MATCH) 5V 1 3 + 8 3.5k 40k 7 3.5k REF G = 200 249Ω 3.5k 3.5k 6 LT1167 1 IN 5 2 – ADC LTC®1286 20k 3 4 + 2 1 1/2 LT1112 40k DIGITAL DATA OUTPUT AGND – 1167 F09 Figure 9. Single Supply Bridge Amplifier TYPICAL APPLICATION AC Coupled Instrumentation Amplifier 2 –IN 1 – RG +IN 6 LT1167 8 REF 3 5 + OUTPUT R1 500k C1 0.3μF – 1 1/2 LT1112 2 3 f –3dB = 1 (2π)(R1)(C1) = 1.06Hz + 1167 TA04 1167fc 18 LT1167 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 t .015* (6.477 t 0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) +.035 .325 –.015 8.255 +0.889 –0.381  .045 – .065 (1.143 – 1.651) .130 t .005 (3.302 t 0.127) .065 (1.651) TYP .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 t .003 (0.457 t 0.076) N8 REV I 0711 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1167fc 19 LT1167 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 p.005 .050 BSC 8 .245 MIN 7 6 5 .160 p.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 p.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 s 45o (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0o– 8o TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .053 – .069 (1.346 – 1.752) .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 2 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 0303 1167fc 20 LT1167 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION B 01/11 Added LT1167-1 to Description, Absolute Maximum Ratings, Order Information, Electrical Characteristics and Applications Information Section PAGE NUMBER C 08/11 Correction to TYP specification for SR from 12 to 1.2 Columns shifted to left in CMRR specification 1-6, 15 4 4, 5 1167fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 21 LT1167 TYPICAL APPLICATION 4-Digit Pressure Sensor 9V R8 392k 3 + 2 2 1 1/4 LT1114 1 LT1634CCZ-1.25 LUCAS NOVA SENOR NPC-1220-015A-3L 4 – 11 – 4 5k R9 1k 2 9V R1 825Ω + RSET 7 6 LT1167 G = 60 R2 12Ω 5k 6 – 1 5k 5k 2 1 8 5 3 3 + 4 10 + 12 0.2% ACCURACY AT ROOM TEMP 1.2% ACCURACY AT 0°C TO 60°C VOLTS 2.800 3.000 3.200 INCHES Hg 28.00 30.00 32.00 13 + – 14 1/4 LT1114 8 1/4 LT1114 5 9 TO 4-DIGIT DVM CALIBRATION ADJUST – R4 100k R5 100k R3 51k R6 50k R7 180k C1 1μF 1167 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1100 Precision Chopper-Stabilized Instrumentation Amplifier Best DC Accuracy LT1101 Precision, Micropower, Single Supply Instrumentation Amplifier Fixed Gain of 10 or 100, IS < 105μA LT1102 High Speed, JFET Instrumentation Amplifier Fixed Gain of 10 or 100, 30V/μs Slew Rate LT1168 Low Power, Single Resistor Programmable Instrumentation Amplifier ISUPPLY = 530μA Max LTC1418 14-Bit, Low Power, 200ksps ADC with Serial and Parallel I/O Single Supply 5V or ±5V Operation, ±1.5LSB INL and ±1LSB DNL Max LT1460 Precision Series Reference Micropower; 2.5V, 5V, 10V Versions; High Precision LT1468 16-Bit Accurate Op Amp, Low Noise Fast Settling 16-Bit Accuracy at Low and High Frequencies, 90MHz GBW, 22V/μs, 900ns Settling LTC1562 Active RC Filter Lowpass, Bandpass, Highpass Responses; Low Noise, Low Distortion, Four 2nd Order Filter Sections LTC1605 16-Bit, 100ksps, Sampling ADC Single 5V Supply, Bipolar Input Range: ±10V, Power Dissipation: 55mW Typ 1167fc 22 Linear Technology Corporation LT 0811 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1998