LT1339
High Power Synchronous
DC/DC Controller
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DESCRIPTION
FEATURES
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The LT ®1339 is a high power synchronous current mode
switching regulator controller. The IC drives dual
N-channel MOSFETs to create a single IC solution for high
power DC/DC converters in applications up to 60V.
High Voltage: Operation Up to 60V
High Current: Dual N-Channel Synchronous Drive
Handles Up to 10,000pF Gate Capacitance
Programmable Average Load Current Limiting
5V Reference Output with 10mA External
Loading Capability
Programmable Fixed Frequency Synchronizable
Current Mode Operation Up to 150kHz
Undervoltage Lockout with Hysteresis
Programmable Start Inhibit for Power Supply
Sequencing and Protection
Adaptive Nonoverlapping Gate Drive Prevents
Shoot-Through
The LT1339 incorporates programmable average current
limiting, allowing accurate limiting of DC load current
independent of inductor ripple current. The IC also incorporates user-adjustable slope compensation for minimization of magnetics at duty cycles up to 90%.
The LT1339 timing oscillator operating frequency is programmable and can be synchronized up to 150kHz. Minimum off-time operation provides main switch protection.
The IC also incorporates a soft start feature that is gated by
both shutdown and undervoltage lockout conditions.
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APPLICATIONS
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An output phase reversal pin allows flexibility in configuration of converter types, including inverting and negative
topologies.
48V Telecom Power Supplies
Personal Computers and Peripherals
Distributed Power Converters
Industrial Control Systems
Lead-Acid Battery Backup Systems
Automotive and Heavy Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
28V to 5V 20A Buck Converter
VBOOST
+
5VREF
+
CBST
1µF
CAVG
CCT
2200pF 2200pF
CT
SL/ADJ
BG
D2
MBR0520
IAVG
CSS, 1µF
CVC, 1nF
+
PHASE
RVC, 10k
VC
CREF
0.1µF
SGND
IRL3103D2
×2
100
CIN
1500µF
63V
×3
L1
10µH
90
RUN/SHDN
SENSE +
70
50
RS
0.005Ω
SENSE –
RFB1
3k
80
60
RRUN
100k
VFB
VREF
RFB2
1k
PGND
SS
+
D1
MBR0520
TS
12VIN
LT1339
12V
C12VIN
47µF
IRL3803
TG
RCT
10k
C5VREF
1µF
+
EFFICIENCY (%)
SYNC
28V to 5V Efficiency
VIN
28V
DBST
IN5819
+
L1 = CTX02-13400-X2
COUT
2200µF
6.3V
×2
VOUT
5V AT 20A
0
10
5
15
OUTPUT CURRENT (A)
20
1339 TA03a
1339 TA03
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LT1339
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RATI GS
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltages
Power Supply Voltage (12VIN)...............– 0.3V to 20V
Topside Supply Voltage (VBOOST)
VTS – 0.3V to VTS + 20V (VMAX = 75V)
Topside Reference Pin Voltage (TS) ......– 0.3V to 60V
Input Voltages
Sense Amplifier Input Common Mode ...– 0.3V to 60V
RUN/SHDN Pin Voltage ...................... – 0.3V to 12VIN
All Other Inputs .......................................– 0.3V to 7V
Maximum Currents
5V Reference Output Current............................ 65mA
Maximum Temperatures
Operating Ambient Temperature Range
LT1339C ............................................ 0°C to 70°C
LT1339I ......................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
SYNC 1
20 VBOOST
5VREF 2
19 TG
CT 3
18 TS
16 BG
IAVG 5
SS 6
15 PGND
VC 7
14 PHASE
13 RUN/SHDN
SGND 8
VFB 9
12 SENSE –
VREF 10
11 SENSE +
N PACKAGE
20-LEAD PDIP
LT1339CN
LT1339CSW
LT1339IN
LT1339ISW
17 12VIN
SL/ADJ 4
SW PACKAGE
20-LEAD PLASTIC SO WIDE
TJMAX = 125°C, θJA = 70°C/W (N)
TJMAX = 125°C, θJA = 85°C/W (SW)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
12VIN = VBOOST = 12V, VC = 2V, TS = 0V, VFB = VREF = 1.25V, CTG = CBG = 3000pF, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
14
150
20
250
mA
µA
Supply and Protection
I12VIN
IBOOST
DC Active Supply Current (Note 2)
DC Standby Supply Current
VRUN/SHDN < 0.5V
DC Active Supply Current (Note 2)
DC Standby Supply Current
VRUN/SHDN < 0.5V
VRUN/SHDN Shutdown Rising Threshold
●
●
2.2
0
●
1.15
1.25
mA
µA
1.35
25
V
VSSHYST
Shutdown Threshold Hysteresis
ISS
Soft Start Charge Current
●
4
8
14
mV
µA
VUVLO
Undervoltage Lockout Threshold - Falling
Undervoltage Lockout Threshold - Rising
Undervoltage Lockout Hysteresis
●
●
●
8.20
9.75
9.95
200
9.00
9.35
350
V
V
mV
4.75
5.00
5.25
3
5
mV/V
10
20
mA
mA
–2
V/A
5V Reference
VREF5
IREF5
5V Reference Voltage
Line, Load and Temperature
●
5V Reference Line Regulation
10V ≤ 12VIN ≤ 15V
●
5V Reference Load Range - DC
Pulse
5V Reference Load Regulation
ISC
5V Reference Short-Circuit Current
●
●
0 ≤ IREF5 ≤ 20mA
●
– 1.25
45
V
mA
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LT1339
ELECTRICAL CHARACTERISTICS
12VIN = VBOOST = 12V, VC = 2V, TS = 0V, VFB = VREF = 1.25V, CTG = CBG = 3000pF, TA = 25°C unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
1.242
1.235
1.250
1.250
1.258
1.265
V
V
●
0.1
0.5
1.0
µA
3200
Error Amplifier
VFB
Error Amplifier Reference Voltage
Measured at Feedback Pin
IFB
Feedback Input Current
gm
Error Amplifier Transconductance
●
1200
2000
AV
Error Amplifier Voltage Gain
●
1500
3000
V/V
IVC
Error Amplifier Source Current
Error Amplifier Sink Current
VFB – VREF = 500mV
●
●
200
280
275
400
µA
µA
VVC
Absolute VC Clamp Voltage
Measured at VC Pin
3.5
V
VSENSE
Peak Current Limit Threshold
Average Current Limit Threshold (Note 4)
Measured at Sense Inputs
Measured at Sense Inputs
Average Current Limit Threshold
Measured at IAVG Pin
2.5
V
15
V/V
VIAVG
VFB = VREF
●
●
170
110
190
120
µmho
mV
mV
130
Current Sense Amplifier
AV
Amplifier DC Gain
Measured at IAVG Pin
VOS
Amplifier Input Offset Voltage
2V < VCMSENSE < 60V,
SENSE+ – SENSE– = 5mV
●
IB
Input Bias Current
Sink (VCMSENSE > 5V)
Source (VCMSENSE = 0V)
●
●
fO ≤ 150kHz
●
●
–5
0.1
mV
45
700
75
1200
µA
µA
150
5
kHz
%
2.75
2.75
mA
mA
V
Oscillator
fO
Operating Frequency, Free Run
Frequency Programming Error (Note 3)
ICT
Timing Capacitor Discharge Current
LT1339C
LT1339I
●
●
2.20
2.10
2.50
2.50
VSYNC
SYNC Input Threshold
Rising Edge
●
0.8
2.0
fSYNC
SYNC Frequency Range
fSYNC ≤ 150kHz
●
fO
1.4fO
12VIN ≤ 8V
VRUN < 0.5V
●
●
Output Drivers
VTG,BG
Undervoltage Output Clamp
Standby Mode Output Clamp
VTG
Top Gate On Voltage
Top Gate Off Voltage
●
●
tTGR
Top Gate Rise Time
●
tTGF
Top Gate Fall Time
●
VBG
Bottom Gate On Voltage
Bottom Gate Off Voltage
●
●
tBGR
Bottom Gate Rise Time
tBGF
Bottom Gate Fall Time
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
11.0
0.4
0.7
0.1
V
V
11.9
0.4
12.0
0.7
V
V
130
200
ns
60
140
ns
11.9
0.4
12.0
0.7
V
V
●
70
200
ns
●
60
140
ns
11.0
Note 2: Supply current specification does not include external FET gate
charge currents. Actual supply currents will be higher and vary with
operating frequency, operating voltages and the type of external FETs
used. See Application Information section.
Note 3: Test condition: RCT = 16.9k, CCT = 1000pF.
Note 4: Test Condition: VCMSENSE = 10V.
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LT1339
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TYPICAL PERFORMANCE CHARACTERISTICS
Boost Supply Current vs
Temperature
12VIN Supply Current vs
Temperature
5V REFERENCE SHORT-CIRCUIT CURRENT (mA)
18
17
3.5
I12VIN SUPPLY CURRENT (mA)
BOOST SUPPLY CURRENT (mA)
4.0
3.0
2.5
2.0
1.5
16
15
14
13
12
11
1.0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
10
–50 –25
125
0
25
50
75
125
55
50
45
40
35
30
–50 –25
180
1.251
160
150
125
5V Reference Voltage vs
Temperature
5.01
5V REFERENCE VOLTAGE (V)
1.252
REFERENCE VOLTAGE (V)
190
100
1339 G03
Reference Voltage vs
Temperature
170
50
25
75
0
TEMPERATURE (°C)
1339 G02
I12VIN Shutdown Current vs
Temperature
I12VIN SHUTDOWN CURRENT (µA)
100
60
TEMPERATURE (°C)
1339 G01
1.250
1.249
1.248
5.00
4.99
1.247
140
130
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1.246
–50 –25
50
25
75
0
TEMPERATURE (°C)
4.0
3.5
3.0
2.5
2.0
1.5
100
125
1339 G07
50
25
75
0
TEMPERATURE (°C)
2.6
2.4
2.2
2.0
1.8
1.6
1.4
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1339 G08
100
125
1339 G06
Error Amplifier Maximum Source
Current vs Temperature
ERROR AMPLIFIER SOURCE CURRENT (µA)
Ω
4.5
50
25
75
0
TEMPERATURE (°C)
4.98
–50 –25
125
Error Amplifier Transconductance
vs Temperature
ERROR AMPLIFIER TRANSCONDUCTANCE (m )
Error Amplifier Voltage Gain vs
Temperature
1.0
–50 –25
100
1339 G05
1339 G04
ERROR AMPLIFIER VOLTAGE GAIN (kV/V)
5V Reference Short-Circuit
Current vs Temperature
350
325
300
275
250
225
200
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1339 G09
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TYPICAL PERFORMANCE CHARACTERISTICS
Soft Start Charge Current
vs Temperature
RUN/SHDN Rising Threshold
vs Temperature
8
7
6
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
26
RUN/SHDN THRESHOLD HYSTERESIS (mV)
1.26
RUN/SHDN RISING THRESHOLD (V)
SOFT START CHARGE CURRENT (µA)
9
1.25
1.24
1.23
1.22
1.21
1.20
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
100
1339 G10
60
FALL TIME
40
20
5000
7500
2500
BOTTOM GATE CAPACITANCE (pF)
50
25
75
0
TEMPERATURE (°C)
10000
100
125
1339 G12
160
FULL OPERATING
TEMPERATURE RANGE
150
250
140
UPPER LIMIT
200
RISE TIME
150
100
FALL TIME
130
TYPICAL
120
LOWER LIMIT
110
100
50
90
80
0
1000
5000
7500
2500
TOP GATE CAPACITANCE (pF)
1339 G13
10000
0
1
2
3
4
5
VSENSE(CM) (V)
1339 G14
12VIN Supply Current vs
Supply Voltage
60
1339 G15
Boost Supply Current vs
12VIN Supply Voltage
30
18
fO = 100kHz
TA = 25°C
28
BOOST SUPPLY CURRENT (mA )
0
1000
21
Average Current Limit Threshold
Sense Voltage Tolerance vs
Common Mode Voltage
VSENSE (mV)
TOP GATE TRANSITION TIMES (ns)
RISE TIME
22
20
–50 –25
TA = 25°C
12VIN SUPPLY CURRENT (mA )
BOTTOM GATE TRANSITION TIMES (ns)
80
23
125
300
TA = 25°C
100
24
Top Gate Transition Times vs
Top Gate Capacitance
160
120
25
1339 G11
Bottom Gate Transition Times vs
Bottom Gate Capacitance
140
RUN/SHDN Threshold Hysteresis
vs Temperature
CBG = 10000pF
26
24
22
CBG = 4700pF
20
18
CBG = 3300pF
16
CBG = 1000pF
fO = 100kHz
TA = 25°C
16
CTG = 10000pF
14
12
10
CTG = 4700pF
8
CTG = 3300pF
6
CTG = 1000pF
4
14
2
10
12
13
14
11
12VIN SUPPLY VOLTAGE (V)
15
1339 G16
10
12
13
14
11
12VIN SUPPLY VOLTAGE (V)
15
1339 G17
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TYPICAL PERFORMANCE CHARACTERISTICS
Sense Amplifier Input Bias
Current (Source) vs Temperature
UVLO Thresholds vs Temperature
10.00
1200
9.75
1100
RISING
FALLING
8.75
900
800
700
8.50
600
8.25
500
25
0
75
50
0
25
50
75
100
600
500
UPPER
LIMIT
300
200
100
0
600
TYPICAL
LOWER
LIMIT
1.0 (1.25) 1.5
2.0
0.5
RUN/SHDN INPUT VOLTAGE (V)
FULL OPERATING
TEMPERATURE
RANGE
450
TYPICAL
LOWER
LIMIT
150
0
2.5
UPPER
LIMIT
300
0
10
2
4
6
8
RUN/SHDN SUPPLY VOLTAGE (V)
12
1339 G23
Operating Frequency (Normalized)
vs Temperature
Maximum Duty Cycle vs RCT
100
IDISCHG = 2.75mA
80
70
60
50
IDISCHG = 2.1mA
40
30
20
FULL OPERATING
TEMPERATURE
RANGE
10
1
2
4
6
10
20
RCT (kΩ)
40 60 100
1339 G21
OPERATING FREQUENCY (NORMALIZED)
1.01
90
MAXIMUM DUTY CYCLE (%)
125
1339 G20
1339 G22
0
100
RUN/SHDN Input Current
vs Pin Voltage
RUN/SHDN INPUT CURRENT (µA)
FULL OPERATING
TEMPERATURE
RANGE
..................................................................
RUN/SHDN INPUT CURRENT (nA )
800
50
25
75
0
TEMPERATURE (°C)
1339 G19
RUN/SHDN Input Current
vs Pin Voltage
0
30
–50 –25
125
TEMPERATURE (°C)
1339 G18
400
45
35
TEMPERATURE (°C)
700
50
40
400
–50 –25
125
100
IB(SINK) (µA)
9.25
9.00
VCMSENSE = 10V
55
1000
IB(SOURCE) (µA)
V12VIN (V)
60
VCMSENSE = 0V
9.50
8.00
–50 –25
Sense Amplifier Input Bias
Current (Sink) vs Temperature
1.00
0.99
0.98
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1339 G24
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LT1339
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PIN FUNCTIONS
SYNC (Pin 1): Oscillator Synchronization Pin with TTLLevel Compatible Input. Input drives internal rising edge
triggered one-shot; sync signal on/off times should be
≥1µs (10% to 90% DC at 100kHz). Does not contain
internal pull-up. Connect to SGND if not used.
5VREF (Pin 2): 5V Output Reference. Allows connection
of external loads up to 10mA DC. (Reference is not
available in shutdown.) Typically bypassed with 1µF
capacitor to SGND.
CT (Pin 3): Oscillator Timing Pin. Connect a capacitor
(CCT) to ground and a pull-up resistor (RCT) to the 5VREF
supply. Typical values are CT = 1000pF and 10k ≤ RCT
≤ 30k.
SL/ADJ (Pin 4): Slope Compensation Adjustment.
Allows increased slope compensation for certain high
duty cycle applications. Resistive loading of the pin
increases effective slope compensation. A resistor
divider from the 5VREF pin can tailor the onset of additional slope compensation to specific regions in each
switch cycle. Pin can be floated or connected to 5VREF if
no additional slope compensation is required. (See
Applications Information section for slope compensation details.)
IAVG (Pin 5): Average Current Limit Integration. Frequency response characteristic is set using the 50kΩ
output impedance and external capacitor to ground.
Averaging roll-off typically set at 1 to 2 orders of magnitude under switching frequency. (Typical capacitor value
~1000pF for fO = 100kHz.) Shorting this pin to SGND will
disable the average current limit function.
SS (Pin 6): Soft Start. Generates ramping threshold for
regulator current limit during start-up and after UVLO
event by sourcing about 8µA into an external capacitor.
VC (Pin 7): Error Amplifier Output. RC load creates
dominant compensation in power supply regulation feedback loop to provide optimum transient response. (See
Applications Information section for compensation details.)
VREF (Pin 10): Bandgap Generated Voltage Reference
Decoupling. Connect a capacitor to signal ground. (Typical capacitor value ~0.1µF.)
SENSE + (Pin 11): Current Sense Amplifier Inverting
Input. Connect to most positive (DC) terminal of current
sense resistor.
SENSE – (Pin 12): Current Sense Amplifier Noninverting
Input. Connect to most negative (DC) terminal of current
sense resistor.
RUN/SHDN (Pin 13): Precision Referenced Shutdown.
Can be used as logic level input for shutdown control or
as an analog monitor for input supply undervoltage
protection, etc. IC is enabled when RUN/SHDN pin rising
edge exceeds 1.25V. About 25mV of hysteresis helps
assure stable mode switching. All internal functions are
disabled in shutdown mode. If this function is not
desired, connect RUN/SHDN to 12VIN (typically through
a 100k resistor). See Applications Information section.
PHASE (Pin 14): Output Driver Phase Control. If Pin 14
is not connected (floating), the topside driver operates
the main switch, with the bottom side driver operating
the synchronous switch. Shorting Pin 14 to ground
reverses the roles of the output drivers. PHASE is typically shorted to ground for inverting and boost configurations. Positive buck configuration requires the PHASE
pin to float. See Applications Information section.
PGND (Pin 15): Power Ground. References the bottom
side output switch and internal driver control circuits.
Connect with low impedance trace to VIN decoupling
capacitor negative (ground) terminal.
BG (Pin 16): Bottom Side Output Driver. Connects to gate
of bottom side external power FET.
12VIN (Pin 17): 12V Power Supply Input. Bypass with at
least 1µF to PGND.
TS (Pin 18): Boost Output Driver Reference. Typically
connects to source of topside external power FET and
inductive switch node.
SGND (Pin 8): Small-Signal Ground. Connect to negative
terminal of COUT.
TG (Pin 19): Topside (Boost) Output Driver. Connects to
gate of topside external power FET.
VFB (Pin 9): Error Amplifier Inverting Input. Used as
voltage feedback input node for regulator loop. Pin
sources about 0.5µA DC bias current to protect from an
open feedback path condition.
VBOOST (Pin 20): Topside Power Supply. Bootstrapped
via 1µF capacitor tied to switch node (Pin 18) and
Schottky diode connected to the 12VIN supply.
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LT1339
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FU CTIO AL BLOCK DIAGRA
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VIN
VBOOST
MAIN
SWITCH
CT
PHASE
12VIN
5VREF
TG
TS
NONOVERLAPPING
SWITCH LOGIC
BG
Q
SYNC
SWITCH
S
UVLO
CIRCUIT
R
OSC
SL/ADJ
ONE SHOT
SENSE +
RSENSE
VOUT
+
× 15
SENSE –
+
SYNC
+
–
IC1
CURRENT
SENSE AMP
0.5µA
–
–
VFB
VC
EA
+
VREF
1.25V
5VREF
2.5V
5V
–
8µA
REFERENCE
50k
SOFT START
+
+
RUN/SHDN
AVERAGE
CURRENT
LIMIT
CIRCUIT
ENABLE
1.25V
–
SGND
PGND
SS
IAVG
1339 • BD
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OPERATION
(Refer to Functional Block Diagram)
Basic Control Loop
The LT1339 uses a constant frequency, current mode
synchronous architecture. The timing of the IC is provided
through an internal oscillator circuit, which can be synchronized to an external clock, programmable to operate
at frequencies up to 150kHz. The oscillator creates a
modified sawtooth wave at its timing node (CT) with a slow
charge, rapid discharge characteristic.
During typical positive buck operation, the main switch
MOSFET is enabled at the start of each oscillator cycle. The
main switch stays enabled until the current through the
switched inductor, sensed via the voltage across a series
sense resistor (RSENSE), is sufficient to trip the current
comparator (IC1) and, in turn, reset the RS latch. When the
RS latch resets, the main switch is disabled, and the
synchronous switch MOSFET is enabled. Shoot-through
prevention logic prohibits enabling of the synchronous
switch until the main switch is fully disabled. If the current
comparator threshold is not obtained throughout the
entire oscillator charge period, the RS latch is bypassed
and the main switch is disabled during the oscillator
discharge time. This “minimum off time” assures adequate charging of the bootstrap supply, protects the main
switch, and is typically about 1µs.
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LT1339
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OPERATION
(Refer to Functional Block Diagram)
The current comparator trip threshold is set on the VC pin,
which is the output of a transconductance amplifier, or
error amplifier (EA). The error amplifier integrates the
difference between a feedback voltage (on the VFB pin)
and an internal bandgap generated reference voltage of
1.25V, forming a signal that represents required load
current. If the supplied current is insufficient for a given
load, the output will droop, thus reducing the feedback
voltage. The error amplifier forces current out of the VC
pin, increasing the current comparator threshold. Thus,
the circuit will servo until the provided current is equal to
the required load and the average output voltage is at the
value programmed by the feedback resistors.
Average Current Limit
The output of the sense amplifier is monitored by a single
pole integrator comprised of an external capacitor on the
IAVG pin and an internal impedance of approximately
50kΩ. If this averaged value signal exceeds a level corresponding to 120mV across the external sense resistor, the
current comparator threshold is clamped and cannot
continue to rise in response to the error amplifier. Thus, if
average load current requirements exceed 120mV/RSENSE,
the supply will current limit and the output voltage will fall
out of regulation. The average current limit circuit monitors the sense amplifier output without slope compensation or ripple current contributions, therefore the average
load current limit threshold is unaffected by duty cycle.
Undervoltage Lockout
The LT1339 employs an undervoltage lockout circuit
(UVLO) that monitors the 12V supply rail. This circuit
disables the output drive capability of the LT1339 if
the 12V supply drops below about 9V. Unstable mode
switching is prevented through 350mV of UVLO threshold
hysteresis.
Adaptive Nonoverlapping Output Stage
The FET driver output stage implements adaptive
nonoverlapping control. This circuitry maintains dead
time independent of the type, size or operating conditions
of the switch elements. The control circuit monitors the
output gate drive signals, insuring that the switch gate
(being disabled) is fully discharged before enabling the
other switch driver.
Shutdown
The LT1339 can be put into low current shutdown mode
by pulling the RUN/SHDN pin low, disabling all circuit
functions. The shutdown threshold is a bandgap referred
voltage of 1.25V typical. Use of a precision threshold on
the shutdown circuit enables use of this pin for undervoltage protection of the VIN supply and/or power supply
sequencing.
Soft Start
The LT1339 incorporates a soft start function that operates by slowly increasing the internal current limit. This
limit is controlled by clamping the VC node to a low voltage
that climbs with time as an external capacitor on the SS pin
is charged with about 8µA. This forces a graceful climb of
output current capability, and thus a graceful increase in
output voltage until steady-state regulation is achieved.
The soft start timing capacitor is clamped to ground
during shutdown and during undervoltage lockout, yielding a graceful output recovery from either condition.
5V Internal Reference
Power for the oscillator timing elements and most other
internal LT1339 circuits is derived from an internal 5V
reference, accessible at the 5VREF pin. This supply pin can be
loaded with up to 10mA DC (20mA pulsed) for convenient
biasing of local elements such as control logic, etc.
Slope Compensation
For duty cycles greater than 50%, slope compensation is
required to prevent current mode duty cycle instability in
the regulator control loop. The LT1339 employs internal
slope compensation that is adequate for most applications. However, if additional slope compensation is
desired, it is available through the SL/ADJ pin. Excessive
slope compensation will cause reduction in maximum
load current capability and therefore is not desirable.
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RSENSE generates a voltage that is proportional to the
inductor current for use by the LT1339 current sense
amplifier. The value of RSENSE is based on the required
load current. The average current limit function has a
typical threshold of 120mV/RSENSE, or:
RSENSE = 120mV/ILIMIT
Operation with VSENSE common mode voltage below 4.5V
may slightly degrade current limit accuracy. See Average
Current Limit Threshold Tolerance vs Common Mode
Voltage curve in the Typical Performance Characteristics
section for more information.
Output Voltage Programming
Output voltage is programmed through a resistor feedback network to VFB (Pin 9) on the LT1339. This pin is the
inverting input of the error amplifier, which is internally
referenced to 1.25V. The divider is ratioed to provide
1.25V at the VFB pin when the output is at its desired value.
The output voltage is thus set following the relation:
VOUT = 1.25(1 + R2/R1)
when an external resistor divider is connected to the
output as shown in Figure 1.
VOUT
R2
LT1339 VFB
SGND
9
R1
8
1339 • F01
Figure 1. Programming LT1339 Output Voltage
If high value feedback resistors are used, the input bias
current of the VFB pin (1µA maximum) could cause a slight
increase in output voltage. A Thevenin resistance at the
VFB pin of 15k yield maximum duty cycles above
90%. Given a timing resistor value, the value of the timing
capacitor (CCT) can then be determined for desired operating frequency (fO) using the relation:
(1/ fO ) − (100) 10−9
CCT ≈
(RCT / 1.85) + −3 1.75
(2.5) 10 − (3.375 / RCT )
A plot of Operating Frequency vs RCT and CCT is shown in
Figure 2. Typical 100kHz operational values are CCT =
1000pF and RCT = 16.9k.
160
OSCILLATOR FREQUENCY (kHz)
RSENSE Selection for Output Current
140
CCT = 1.0nF
120
CCT = 1.5nF
100
80
60
CCT = 3.3nF
40
CCT = 2.2nF
20
0
0
5
10
20
25
15
TIMING RESISTOR (kΩ)
30
LT1339 • F02
Figure 2. Oscillator Frequency vs RCT, CCT
Oscillator Components RCT and CCT
Average Current Limit
The LT1339 oscillator creates a modified sawtooth wave
at its timing node (CT) with a slow charge, rapid discharge
characteristic. The rapid discharge time corresponds to
The average current limit function is implemented using
an external capacitor (CAVG) connected from IAVG to SGND
that forms a single pole integrator with the 50kΩ output
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impedance of the IAVG pin. The integrator corner frequency is typically set 1 to 2 orders of magnitude below the
oscillator frequency and follows the relation:
f–3dB = (3.2)(10– 6)/CAVG
The average current limit function can be disabled by
shorting the IAVG pin directly to SGND.
Soft Start Programming
The current control pin (VC) limits sensed inductor current
to zero at voltages less than a transistor VBE, to full average
current limit at VC = VBE + 1.8V. This generates a 1.8V full
regulation range for average load current. An internal
voltage clamp forces the VC pin to a VBE – 100mV above
the SS pin voltage. This 100mV “dead zone” assures 0%
duty cycle operation at the start of the soft start cycle, or
when the soft start pin is pulled to ground. Given the
typical soft start current of 8µA and a soft start timing
capacitor CSS, the start-up delay time to full available
average current will be:
tSS = (1.5)(105)(CSS)
sourcing capabilities of that supply, causing the system to
lock up in an undervoltage state. Input supply start-up
protection can be achieved by enabling the RUN/SHDN
pin using a resistor divider from the input supply to
ground. Setting the divider output to 1.25V when that
supply is almost fully enabled prevents the LT1339 regulator from drawing large currents until the input supply is
able to provide the required power.
If additional hysteresis is desired for the enable function,
an external feedback resistor can be used from the LT1339
regulator output. If connection to the regulator output is
not desired, the 5VREF internal supply pin can be used.
Figure 3 shows a resistor connection on a 48V to 5V
converter that yields a 40V VIN start-up threshold for
regulator enable and also provides about 10% input
referred hysteresis.
VIN
48V
300k
390k
The diode reverse breakdown voltage must be greater than
VIN + 12VIN. The bootstrap capacitor should be at least 100
times greater than the total input capacitance of the
topside FET. A capacitor in the range of 0.1µF to 1µF is
generally adequate for most applications.
Shutdown Function — Input Undervoltage Detect and
Threshold Hysteresis
The LT1339 RUN/SHDN pin uses a bandgap generated
reference threshold of about 1.25V. This precision threshold allows use of the RUN/SHDN pin for both logic-level
shutdown applications and analog monitoring applications such as power supply sequencing.
Because an LT1339 controlled converter is a power
transfer device, a voltage that is lower than expected on
the input supply could require currents that exceed the
OPTION 1
OPTION 2
2
13
Boost Supply
The VBOOST supply is bootstrapped via an external capacitor. This supply provides gate drive to the topside switch
FET. The bootstrap capacitor is charged from 12VIN through
a diode when the switch node is pulled low.
VOUT
5V
10k
5VREF
LT1339
RUN/SHDN
1339 • F03
Figure 3. Input Supply Sequencing Programming
The shutdown function can be disabled by connecting the
RUN/SHDN pin to the 12VIN rail. This pin is internally
clamped to 2.5V through a 20k series input resistance and
will therefore draw about 0.5mA when tied directly to 12V.
This additional current can be minimized by making the
connection through an external resistor (100k is typically
used).
Operation with Split Supplies and Supply Sequencing
N-channel power MOSFETs can parasitically turn themselves on due to leakage currents or capacitive coupling
onto the MOSFET gate. In shutdown, this is prevented by
active pull-down clamps on the TG and BG driver outputs
of the LT1339. These clamps are active when 12VIN > 0.7V.
The 12VIN power supply for the LT1339 is usually derived
from the converter input supply; however, these supplies
can be independent. If these supplies are independent and
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the converter input supply is enabled with no voltage on
the LT1339 12VIN pin, the LT1339 driver output clamps
will not be activated. To prevent turn-on, an external
current path must be used to bleed off charge on the
switch MOSFET gates. High value bleed resistors (50k to
250k) should be connected between the TG and SW pins
and between BG and PGND. This provides discharge paths
for the switch MOSFET gates, preventing parasitic turn-on
and damage to the MOSFETs.
Oscillator Synchronization
The LT1339 oscillator generates a modified sawtooth
waveform at the CT pin between low and high thresholds
of about 0.8V (vl) and 2.5V (vh) respectively. The oscillator
can be synchronized by driving a TTL level pulse into the
SYNC pin. This inputs to a one-shot circuit that reduces the
oscillator high threshold to 2V for about 200ns. The SYNC
input signal should have minimum high/low times of ≥1µs.
Inductor Selection
The inductor for an LT1339 converter is selected based on
output power, operating frequency and efficiency requirements. Generally, the selection of inductor value can be
reduced to desired maximum ripple current in the inductor
(∆I). For a buck converter, the minimum inductor value for
a desired maximum operating ripple current can be determined using the following relation:
L MIN =
(VOUT )(VIN − VOUT)
(∆I)(fO)(VIN)
where fO = operating frequency. Given an inductor value
(L), the peak inductor current is the sum of the average
inductor current (IAVG)and half the inductor ripple current
(∆I), or:
IPK = IAVG +
(VOUT )(VIN − VOUT)
(2)(L)(fO)(VIN)
The inductor core type is determined by peak current and
efficiency requirements. The inductor core must withstand peak current without saturating, and series winding
resistance and core losses should be kept as small as is
practical to maximize conversion efficiency.
The LT1339 peak current limit threshold is 40% greater than
the average current limit threshold. Slope compensation
effects reduce this margin as duty cycle increases. This
margin must be maintained to prevent peak current limit
from corrupting the programmed value for average current
limit. Programming the peak ripple current to less than 15%
of the desired average current limit value will assure porper
operation of the average current limit feature through 90%
duty cycle (see Slope Compensation section).
12
SYNC
2.5V
(vh)
2V
VCT
0.8V
(vl)
FREE RUN
SYNCHRONIZED
1339 F04
Figure 4. Free Run and Synchronized Oscillator
Waveforms (at CT Pin)
Slope Compensation
Current mode switching regulators that operate with a
duty cycle greater than 50% and have continuous inductor
current can exhibit duty cycle instability. While a regulator
will not be damaged and may even continue to function
acceptably during this type of subharmonic oscillation, an
irritating high-pitched squeal is usually produced.
The criterion for current mode duty cycle instability is met
when the increasing slope of the inductor ripple current is
less than the decreasing slope, which is the case at duty
cycles greater than 50%. This condition is illustrated in
Figure 5a. The inductor ripple current starts at I1, at the
beginning of each oscillator switch cycle. Current
increases at a rate S1 until the current reaches the control
trip level I2. The controller servo loop then disables the
main switch (and enables the synchronous switch) and
inductor current begins to decrease at a rate S2. If the
current switch point (I2) is perturbed slightly and
increased by ∆I, the cycle time ends such that the minimum current point is increased by a factor of (1 + S2/S1)
to start the next cycle. On each successive cycle, this error
is multiplied by a factor of S2/S1. Therefore, if S2/S1 is
≥ 1, the system is unstable.
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Subharmonic oscillations can be eliminated by augmenting the increasing ripple current slope (S1) in the control
loop. This is accomplished by adding an artificial ramp on
the inductor current waveform internal to the IC (with a
slope SX) as shown in Figure 5b. If the sum of the slopes
S1 + SX is greater than S2, the condition for subharmonic
oscillation no longer exists.
For a buck converter, the required additional current waveform slope, or “Slope Compensation,” follows the relation:
V
SX ≥ IN 2DC − 1
L
(
)
For duty cycles less than 50% (DC < 0.5), SX is negative
and is not required. For duty cycles greater than 50%, SX
takes on values dependent on S1 and duty cycle. This leads
to a minimum inductance requirement for a given VIN and
duty cycle of:
V
L MIN = IN 2DC− 1
SX
(
)
The LT1339 contains an internal SX slope compensation
ramp that has an equivalent current referred value of:
Amp/s
where fO is oscillator frequency. This yields a minimum
inductance requirement of:
(VIN)(RSENSE)(2DC− 1)
(0.084)(fO)
I1
S1 + SX
0
S1
S2
Amp/s
where REQ is the effective resistance of the resistor divider.
Actual compensation will be somewhat greater due to internal curvature correction circuitry that imposes an exponential increase in the slope compensation waveform,
1.40
1.35
PEAK/AVG
T1
I2
(2500)( fO )
(REQ )(RSENSE )
1.45
A down side of slope compensation is that, since the IC servo
loop senses an increase in perceived inductor current, the
∆I
If an inductor smaller than the minimum required for
internal slope compensation (calculated above as LMIN) is
desired, additional slope compensation is required. The
LT1339 provides this capability through the SL/ADJ pin.
This feature is implemented by referencing this pin via a
resistor divider from the 5VREF pin to ground. The additional slope compensation will be affected at the point in
the oscillator waveform (at pin CT) corresponding to the
voltage set by the resistor divider. Additional slope compensation can be calculated using the relation:
SXADD =
fO
0.084
RSENSE
L MIN ≥
internal current limit functions are affected such that the
maximum current capability of a regulator is reduced by the
same amount as the effective current referred slope compensation. The LT1339, however, uses a current limit
scheme that is independent of slope compensation effects
(average current limit). This provides operation at any duty
cycle with no reduction in current sourcing capability,
provided ripple current peak amplitude is less than 15% of
the current limit value. For example, if the supply is set up
to current limit at 10A, as long as the peak inductor current
is less than 11.5A, duty cycles up to 90% can be achieved
without compromising the average current limit value.
1.30
1.25
1.20
S1
1.15
S2
1.10
OSCILLATOR
PERIOD
0
0
a
TIME
Figure 5. Inductor Current at DC > 50% and
Slope Compensation Adjusted Signal
b
1339 • F05
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE (DC)
LT1339 • F06
Figure 6. Maximum Ripple Current (Normalized)
vs Duty Cycle for Average Current Limit
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2
further increasing the effective compensation slope up to
20% for a given setting.
Design Example:
VIN = 20V
VOUT = 15V (DC = 0.75)
RSENSE = 0.01Ω
fO = 100kHz
L = 5µH
) ()
1339 • F07a
2V
0.8V
DC = 0.75
(0.084 + 0.139)(fO)
RSENSE
(0.084)(fO)
RSENSE
Amp/s
Subtracting the internally generated slope compensation
and solving for the required effective resistance at SL/ADJ
yields:
REQ ≤
SL/ADJ
2.5V
Since L = 5µH is less than LMIN, additional slope compensation is necessary. The total slope compensation
required is:
(
LT1339
4
Figure 7a. External Slope Compensation Resistors
(20V)(0.01Ω)(1.5 − 1) = 11.9µH
(0.084)(100000)
20V
1.5 − 1 = 2 106
SX ≥
5µH
5VREF
RSL2
30k
The minimum inductor usable with no additional slope
compensation is:
LMIN ≥
RSL1
45k
(2500)(fO)
= 21.5k
6
(2)10 (RSENSE) − (0.084)(fO)
Setting the resistor divider reference voltage at 2V assures
that the additional compensation waveform will be
enabled at 75% duty cycle. As shown in Figure 7a, using
RSL1 = 45k and RSL2 = 30k sets the desired reference
voltage and has a REQ of 18k, which meets both design
requirements. Figure 7b shows the slope compensation
effective waveforms both with and without the SL/ADJ
external resistors.
1339 • F07b
Figure 7b. Slope Compensation Waveforms
Selection criteria for the power MOSFETs include the “ON”
resistance (RDS(ON)), reverse transfer capacitance (CRSS),
maximum drain-source voltage (VDSS) and maximum
output current.
The power FETs selected must have a maximum operating
VDSS exceeding the maximum VIN. VGS voltage maximum
must exceed the 12VIN supply voltage.
Once voltage requirements have been determined, RDS(ON)
can be selected based on allowable power dissipation and
required output current.
In an LT1339 buck converter, the average inductor current
is equal to the DC load current. The average currents
through the main and synchronous switches are:
Power MOSFET and Catch Diode Selection
IMAIN = (ILOAD)(DC)
External N-channel MOSFET switches are used with the
LT1339. The positive gate-source drive voltage of the
LT1339 for both switches is roughly equivalent to the
12VIN supply voltage, so standard threshold MOSFETs
can be used.
ISYNC = (ILOAD)(1 – DC)
The RDS(ON) required for a given conduction loss can be
calculated using the relation:
PLOSS = (ISWITCH)2(RDS(ON))
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In high voltage applications (VIN > 20V), the topside switch
is required to slew very large voltages. As VIN increases,
transition losses increase through a square relation, until
it becomes the dominant power loss term in the main
switch. This transition loss takes the form:
PTR ≈ (k)(VIN)2(IMAX)(CRSS)(fO)
where k is a constant inversely related to the gate drive
current, approximated by k = 2 in LT1339 applications.
The maximum power loss terms for the switches are thus:
2000 hours (three months) lifetime; it is advisable to
derate either the ESR or temperature rating of the capacitor for increased MTBF of the regulator.
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-topeak ripple current is equal to that in the inductor (∆IL),
typically a fraction of the load current. COUT is selected to
reduce output voltage ripple to a desirable value given an
expected output ripple current. Output ripple (∆VOUT) is
approximated by:
∆VOUT ≈ ∆IL{ESR + [(4)(fO) • COUT]–1}
PMAIN = (DC)(IMAX)2(1 + δ)(RDS(ON)) +
2(VIN)2(IMAX)(CRSS)(fO)
where fO = operating frequency.
PSYNC = (1 – DC)(IMAX)2(1 + δ)(RDS(ON))
Efficiency Considerations and Heat Dissipation
The (1 + δ) term in the above relations is the temperature
dependency of RDS(ON), typically given in the form of a
normalized RDS(ON) vs Temperature curve in a MOSFET
data sheet.
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT1339, causing a negative voltage in
excess of the Absolute Maximum Rating to be imposed on
that pin. Connection of a catch Schottky (rated to about 1A
is typically sufficient) from this pin to ground will eliminate
this effect.
CIN and COUT Supply Decoupling Capacitor Selection
The large currents typical of LT1339 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
operation, the source current of the main switch MOSFET
is a square wave of duty cycle VOUT/VIN. Most of this
current is provided by the input bypass capacitor. To
prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
(IMAX )(VOUT (VIN – VOUT ))
1/ 2
IRMS ≈
VIN
which peaks at a 50% duty cycle, when IRMS = IMAX/2.
Capacitor ripple current ratings are often based on only
High output power applications have inherent concerns
regarding power dissipation in converter components.
Although high efficiencies are achieved using the LT1339,
the power dissipated in the converter climbs to relatively
high values when the load draws large amounts of power.
Even at 90% efficiency, an application that provides 500W
to the load has conversion loss of 55W.
I2R dissipation through the switches, sense resistor and
inductor series resistance create substantial losses under
high currents. Generally, the dominant I2R loss is evident
in the FET switches. Loss in each switch is proportional to
the conduction time of that switch. For example, in a 48V
to 5V converter the synchronous FET conducts load current for almost 90% of the cycle time and thus, requires
greater consideration for dissipating I2R power.
Gate charge/discharge current creates additional current
drain on the 12V supply. If powered from a high voltage
input through a linear regulator, the losses in that regulator device can become significant. A supply solution
bootstrapped from the output would draw current from a
lower voltage source and reduce this loss component.
Transition losses are significant in the topside switch FET
when high VIN voltages are used. Transition losses can be
estimated as:
PTLOSS ≈ 2(VIN)2(IMAX)(CRSS)(fO)
Since the conduction time in the main switch of a 48V to
5V converter is small, the I2R loss in the main switch FET
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is also small. However, since the FET gate must switch up
past the 48V input voltage, transition loss can become a
significant factor. In such a case, it is often prudent to take
the increased I2R loss of a smaller FET in order to reduce
CRSS and thus, the associated transition losses.
Gate Drive Buffers
The LT1339 is designed to drive relatively large capacitive
loads. However, in certain applications, efficiency improvements can be realized by adding an external buffer
stage to drive the gates of the FET switches. When the
switch gates load the driver outputs such that rise/fall
times exceed about 100ns, buffers can sometimes result
in efficiency gains. Buffers also reduce the effect of back
injection into the bottom side driver output due to coupling
of switch node transitions through the switch FET CMILLER.
Paying the Physicists
In high power synchronous buck configurations, certain
physical characteristics of the external MOSFET switches
can impact conversion efficiency. As the input voltage
approaches about 30V, the bottom MOSFETs will begin to
exhibit “phantom turn-on.” This phenomenon is caused
by coupling of the instantaneous voltage step on the
bottom side switch drain through CMILLER to the device
gate, yielding internal localized gate-source voltages above
the turn-on threshold of the FET. This generates a shootthrough blip that ultimately eats away at efficiency numbers. In Figure 8 a negative prebias circuit is added to the
bottom side gate. The addition of this ∼3V of negative
offset to the bottom gate drive provides additional offstate voltage range to prevent phantom turn-on.
TS
1µF
LT1339
BG
ZTX749
As currents increase beyond the 10A to 15A range, the
bottom side FET body diode experiences hard turn-on
during switch dead time due to local current loop inductance preventing the timely transfer of charge to the
Schottky catch diode. The charge current required to
commutate this body diode creates a high dV/dt Schottky
avalanche when the diode charge is finally exhausted (due
to an effective inductor current discontinuity at the
moment the body diode no longer requires charge). This
generates an increased turn-on power burst in the topside
switch, causing additional conversion efficiency loss. This
effect of this parasitic inductance can be reduced by using
FETKEY TM MOSFETs, which have parallel catch Schottky
diodes internal to their packages. FETKEY MOSFETs are
not available for high voltages, so as input voltage continues to increase, they can no longer be used. Because this
necessitates the use of discrete FETs and Schottkys,
interdigitation of a number of smaller devices is required
to minimize parasitic inductances. This technique is also
used in the 48V to 5V, 50A converter shown in the Typical
Applications section.
Optimizing Transient Response—Compensation
Component Values
The dominant compensation point for an LT1339 converter is the VC pin (Pin 7), or error amplifier output. This
pin is connected to a series RC network, RVC and CVC. The
infinite permutations of input/output filtering, capacitor
ESR, input voltage, load current, etc. make for an empirical
method of optimizing loop response for a specific set of
conditions.
Loop response can be observed by injecting a step change
in load current. This can be achieved by using a switchable
load. With the load switching, the transient response of the
output voltage can be observed with an oscilloscope.
Iterating through RC combinations will yield optimized
response. Refer to LTC Application Note 19 in 1990 Linear
Applications Handbook, Volume 1 for more information.
3.3V
12VIN
ZTX649
This type of prebias circuit is used in the 48V to 5V, 50A
converter pictured in the Typical Applications section.
10k
D1N914
FETKEY is a trademark of International Rectifier Corporation.
PGND
1339 F08
Figure 8. Bottom Side Driver Negative Prebias Circuit
sn1339 1339fas
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C11
0.1µF
+
+
C12
100pF
+
C10
0.1µF
C9
1800pF
5%
NPO
+
+
+
+
C14
3300pF
R9
12k
C1: SANYO 63MV680GX
C2: WIMA SMD4036/1.5/63/20/TR
C6: KEMET T510X477M006AS (X8)
L1: GOWANDA 50-318
T1: GOWANDA 50-319
+
R5
2.49k
1%
12V
VIN
48V
10
7
6
5
3
4
2
1
17
C15
0.1µF
8
SGND
VREF
VC
SS
IAVG
CT
11
18
19
20
15
PGND
12
SENSE –
16
BG
14
PHASE
13
RUN/SHDN
9
VFB
SENSE +
TS
TG
5VREF
SL/ADJ
VBOOST
SYNC
D2
MURS120
C2
1.5µF
63V
12VIN
+
U1
LT1339
C5
1µF
C1
680µF
63V
R6, 100Ω
D5
BAT54
R10
10k
1%
R8
301k
1%
R7
100Ω
4
3
2
1
4
3
2
1
VCC1
OUT1
VCC2
GND1
IN2
OUT2
VCC1
IN1
U3, LTC1693-2
GND2
5
6
7
8
5
6
7
8
C7
1µF
VCC2
OUT2
GND2
OUT1
IN2
GND1
IN1
U2, LTC1693-2
+
+
C13
1µF
+
D4
MBR0530T1
C8
1µF
D3
MURS120
Q1
MTD20N06HD
R1
0.04Ω
Q3
MTD20N06HD
13:2
T1
D1
MURS120
48V to 1.8V 2-Transistor Synchronous Forward Converter
3 2 1
8 7 6 5
R2
5.1Ω
+
Q4
Si4420
X2
4
C3
4700pF
25V
3 2 1
8 7 6 5
L1
1.5µH
+
Q2
Si4420
X2
4
C6
470µF
6.3V
X8
1339 TA05
+
C4
0.1µF
R4
1.24k
1%
R3
549Ω
1%
VOUT
1,8V
20A
LT1339
TYPICAL APPLICATIONS
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C1
1.2µF
100V
CER
68µF
20V
AVX
TSPE
10k
P
+
100k
0.1µF
P
3.9k
GND1
IN1
PHASE
JP3
W2
T1
2
W3
2
7
5
6
18
1
RUN/SHDN
12VIN
20
2.2µF
19
OUT1
VCC1
470Ω
OUT2
IN2
VCC2
LTC1693-1
GND2
JP2
100k
14
13
17
1
8
3
4
12V
5VOUT SHORT JP3, OPEN JP2
3.3VOUT, SHORT JP2, OPEN JP3
BAS21
BAS21
BAS21
13k
MMBD914LT1
C2
1.2µF
100V
CER
COILCRAFT
DO1608-105
36k
+VIN
–VIN
INPUT
36V TO
75V
+VIN
+VIN
BAT54
10Ω
5
10
P
W4, 7T 6 x 26AWG
W5, 10T 2 x 26AWG
W1, 10T 32AWG,
W2, 15T 32AWG
W1, 10T 2 x 26AWG
T2
T2
T1
8 15
W4
W4
4.7nF
7
VFB
BG
4.7k
4.7k
9
2MIL
POLY
FILM
2MIL
POLY
FILM
2.4k
1µF
BAT54
+
OUT1
IN1
T2
P
2
7
5
6
85
90
95
100k
+
C5
330µF
6.3V
0
1
1
2
8
3 4 5 6 7
OUTPUT CURRENT
48VIN
36VIN
8
9
10
4.42k
1%
–VOUT
9.31k
1%
72VIN
5 7
LT1431CS8
REF
BAS21
10Ω
SEC HV
1339 TA06
SHORT JP1
FOR 5VOUT
0.01µF
1k
0.47µF
50V
3.01k
1%
+VOUT
MMFT3904
6
COLL
–VOUT
OUTPUT
5V/10A
+VOUT
2k
3.1V
2 4
0.22µF
1µF
4.7µF
25V
1k
–VOUT
FZT600
+
+VOUT
3
C3, C4, C5:
SANYO OS-CON
C4
330µF
6.3V
470Ω
GND1
OUT2
IN2
GND2
VCC2
LTC1693-1
VCC1
CNY17-3
4
1
3
8
SUD30N04-10
W1
470Ω
BAT54
1nF
C3
330µF
6.3V
4.8µH
PANASONIC ETQP AF4R8H
10Ω
470Ω
16 3.3Ω
T1 PHILIPS EFD20-3F3 CORE
LP = 720µH (AI = 1800)
T2 ER11/5 CORE
AI = 960µH
6
10Ω
SEC HV
SUD30N04-10
1nF
4.7nF
4.7nF
W3
LT1339
W5
W1
0.1µF
W3, 10T 32AWG,
W4, 10T 32AWG
2.2nF
2.2nF
4
12
0.025Ω
1/2W
W1, 18T BIFILAR 31AWG
W3, 6T BIFILAR 31AWG
1µF
4.53k
3
11
10Ω
P
IRF1310NS
MURS120
FMMT718
FMMT718
TS
2.2µF
SGND
470Ω
SENSE +
CT
W2
SL/ADJ
T2
PGND
47Ω
SS
MMBD914LT1
TG
SYNC
SENSE –
IAVG
VBOOST
5VREF
MURS120
VREF
IRF1310NS
VC
10Ω
EFFICIENCY
0.1µF
V+
GND-F
RTOP
+VIN
COMP
GND-S
18
RMID
48V to 5V Isolated Synchronous Forward DC/DC Converter
LT1339
TYPICAL APPLICATIONS
sn1339 1339fas
U
LT1339
U
TYPICAL APPLICATIONS
5V to 28V DC/DC Synchronous Boost Converter Limits Input Current at 60A (DC)
12V
+
DBST
MBR0530
VBOOST
SYNC
+ C5VREF
Q2
FMMT720
TG
CT
TS
12VIN
SL/ADJ
CCT
CAVG
2200pF 2200pF
12L
+
CVC, 1500pF
VFB
CREF, 0.1µF
RR1
100k
PHASE
RUN/SHDN
SENSE –
VREF
RFB2, 1.2k
D2
MBR0520
L1
40µH
PGND
SGND
RFB1, 27k
Q4
FMMT720
BG
VC
RVC, 7.5k
IRF3205
×4
1µF
SS
D1
IR30BQ060
×8
Q3
FMMT619
+C
IAVG LT1339
CSS, 10µF
IRF3205
×2
1µF
RCT
10k
1µF
+
C12VIN
47µF
Q1
FMMT619
+ CBST
5VREF
VOUT
28V
COUT
2200µF
35V
×6
RSS1
100Ω
RS
0.002Ω
RSS2, 100Ω
SENSE +
CIN
2200µF
6.3V
×4
L1 = 12T 4X12 ON 77439-A7
VIN
5V AT 60A
+
1339 TA04
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
20-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
0.020
(0.508)
MIN
+0.035
0.325 –0.015
+0.889
8.255
–0.381
1.040*
(26.416)
MAX
0.045 – 0.065
(1.143 – 1.651)
)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
0.255 ± 0.015*
(6.477 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
N20 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.093 – 0.104
(2.362 – 2.642)
0.496 – 0.512*
(12.598 – 13.005)
0.037 – 0.045
(0.940 – 1.143)
20
19
18
17
16
15
14
13
12
11
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
1
2
3
4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5
6
7
8
9
10
S20 (WIDE) 0396
sn1339 1339fas
19
LT1339
U
TYPICAL APPLICATION
48V to 5V 50A DC/DC Converter with Input Supply Start-Up Protection
12V
RCT
10k
5VREF
VBOOST
VIN
48V
+
DBST
IN5819
LT1339
SYNC
50mA
C12VIN
47µF
Q1
+ CBST
CT
+ CCT
TG
CAVG, 2200pF
CSS, 10µF
CVC, 2200pF
D3
MMSZ4684
12VIN
CBG, 1µF
IAVG
SS
PGND
RFB2
1k
RFB1
3k
RR1
22k
RR3
51k
PHASE
SGND
RUN/SHDN
VFB
VREF
D2
MBR0520
Q4
RVC, 4.7k
CREF
0.1µF
D1
Q3
BG
VC
IRFZ44
×2
Q2
SL/ADJ
2200pF
+
1µF
TS
C5VREF
1µF
CIN
1500µF
63V, × 6
RBG
10k
D4
IN914
IRFZ44
×4
L1
40µH
RR2
1.2k
RS
0.002Ω
SENSE –
SENSE +
D1 = IR30BQ060 × 8
Q1, Q3 = FMMT619; Q2, Q4 = FMMT720
L1 = Kool Mµ®, 12T 4X12 ON 77439-A7
Kool Mµ IS A REGISTERED TRADEMARK OF MAGNETICS, INC.
COUT
2200µF
6.3V, × 4
+
VOUT
5V AT 50A
1339 TA01
48V to 5V Efficiency
100
95
EFFICIENCY (%)
90
85
80
75
70
65
60
55
50
0
10
30
40
20
OUTPUT CURRENT (AMPS)
50
LT1339 • TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1158
Half-Bridge N-Channel MOSFET Driver
Current Limit Protection, 100% of Duty Cycle
LT1160
Half-Bridge N-Channel MOSFET Driver
Up to 60V Input Supply, No Shoot-Through
LT1162
Dual Half-Bridge N-Channel MOSFET Driver
VIN to 60V, Good for Full-Bridge Applications
LT1336
Half-Bridge N-Channel MOSFET Driver
Smooth Operation at High Duty Cycle (95% to 100%)
LTC ® 1530
High Power Step-Down Switching Regulator Controller
Excellent for 5V to 3.xV Up to 50A
LTC1435A
High Efficiency, Low Noise Current Mode Step-Down DC/DC Converter
Drives Synchronous N-Channel MOSFETs
LTC1438
Dual High Efficiency, Low Noise Synchronous Step-Down Controller
Tight 1% Reference
LT1680
High Power DC/DC Current Mode Step-Up Controller
High Side Current Sense, Up to 60V Input
sn1339 1339fas
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LT/TP 0299 2K REV A • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 1997
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湘ICP备2023018690号
