LT1424CS8-5#TRPBF

LT1424-5 Isolated Flyback Switching Regulator with 5V Output U FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT ®1424-5 is a monolithic high power switching regulator specifically designed for the isolated flyback topology. No “third winding” or optoisolator is required; the integrated circuit senses the isolated output voltage directly from the primary side flyback waveform. A high current, high efficiency switch is included on the die along with all oscillator, control and protection circuitry. No Transformer “Third Winding” or Optoisolator Required Designed for Use with 1:1 Ratio Transformers Fixed, Application Specific 5V Output Voltage Regulation Maintained Well into Discontinuous Mode (Light Load) Load Compensation Provides Excellent Load Regulation Available in 8-Pin PDIP and SO Packages Operating Frequency: 285kHz The LT1424-5 operates with input supply voltages from 3V to 20V and draws only 7mA quiescent current. It can deliver up to 400mA at 5V with no external power devices. By utilizing current mode switching techniques, it provides excellent AC and DC line regulation. U APPLICATIO S ■ ■ ■ The LT1424-5 has a number of features not found on other switching regulator ICs. Its unique control circuitry can maintain regulation well into discontinuous mode. Load compensation circuitry allows for improved load regulation. An externally activated shutdown mode reduces total supply current to 20µA typical for standby operation. Isolated Communication Supplies Industrial Automation Instrumentation Systems , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO 5V Output Isolated Power Supply Load Regulation 5.25 330pF 47Ω ISOLATION BARRIER T1 + C1 100µF 10V 1000pF INPUT COM 0.1µF 1 2 3 4 1N5248 8 SHDN RCCOMP 7 VC VIN LT1424-5 6 SYNC VSW 5 SGND PGND 47Ω 6 • 3 5V 400mA 4 330pF MBR0540T4 7 • 1 • 2 + C2 100µF 10V 1.8k 1424-5 TA01 0.1µF C1, C2: AVX TPS D107M010R0080 T1: DALE LPE-4841-A307 OUTPUT VOLTAGE (V) MBRS130LT3 5V 5.00 OUT COM 4.75 0 100 200 300 OUTPUT CURRENT (mA) 400 1424-5 TA02 sn14245 14245fs 1 LT1424-5 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Supply Voltage (VIN) ................................................ 20V Switch Voltage (VSW) .............................................. 35V SHDN, SYNC Pin Voltage ........................................... 7V Operating Junction Temperature Range Commercial .......................................... 0°C to 125°C Industrial ......................................... – 40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW SHDN 1 8 RCCOMP VC 2 SYNC 3 6 VSW SGND 4 5 PGND N8 PACKAGE 8-LEAD PDIP LT1424CN8-5 LT1424CS8-5 LT1424IN8-5 LT1424IS8-5 7 VIN S8 PACKAGE 8-LEAD PLASTIC SO S8 PART MARKING TJMAX = 145°C, θJA = 130°C/ W (N) TJMAX = 145°C, θJA = 110°C/ W (S) 14245 1424I5 Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSW Open, VC = 1.4V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VIN(MIN) Minimum Operating Voltage ● 2.8 3.1 V ICC Supply Current ● 7.0 9.5 mA Shutdown Mode Supply Current ● 15 40 µA SHDN Pin Threshold ● 0.3 0.9 1.3 V ● 5.23 5.18 5.30 5.30 5.37 5.42 V V ● 400 1000 1600 µmho ● 30 50 80 Feedback Amplifier VREF gm Reference Voltage Feedback Amplifier Transconductance Measured at VSW Pin (Note 2) ∆IC = ±10µA (Note 3) ISOURCE, ISINK Feedback Amplifier Source or Sink Current VCL Feedback Amplifier Clamp Voltage 1.9 µA V Reference Voltage/Current Line Regulation 5V ≤ VIN ≤ 18V Voltage Gain (Note 4) BV Output Switch Breakdown Voltage IC = 5mA ● V(VSW) Output Switch ON Voltage ISW = 1A ● 0.55 0.85 V ILIM Switch Current Limit Duty Cycle = 50%, 0°C ≤ TJ ≤ 125°C Duty Cycle = 50%, – 40°C ≤ TJ ≤ 125°C Duty Cycle = 80% ● ● 1.35 1.20 1.6 1.6 1.3 1.95 1.95 A A A ● 0.95 0.85 1.2 1.2 1.3 1.4 V V 0.01 ● 0.04 %/V 500 V/V 50 V Output Switch 35 Current Amplifier Control Pin Threshold Control Voltage to Switch Transconductance Duty Cycle = Minimum 2 A/V sn14245 14245fs 2 LT1424-5 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSW Open, VC = 1.4V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 260 240 285 285 300 320 kHz kHz 170 200 260 ns Timing f Switching Frequency ● tON Minimum Switch ON Time tED Flyback Enable Delay Time 150 ns tEN Minimum Flyback Enable Time 180 ns 90 % 0.9 Ω Maximum Switch Duty Cycle ● 85 Load Compensation ∆VREF/∆ISW SYNC Function Minimum SYNC Amplitude ● Synchronization Range ● SYNC Pin Input Resistance Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be imparied. Note 2: VREF is a parameter which is measured at the VSW pin. It differs from the output voltage because it accounts for output diode drop, transformer leakage inductance, etc. Nominal output voltage is 5V in the intended application circuit. 1.5 330 2.2 V 450 kHz 40 kΩ Note 3: Feedback amplifier transconductance is RREF referred. Note 4: Voltage gain is RREF referred. sn14245 14245fs 3 LT1424-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Switch Saturation Voltage vs Switch Current Switch Current Limit vs Duty Cycle Minimum Input Voltage vs Temperature 2.0 1.2 3.1 3.0 125°C 0.8 25°C 0.6 –55°C 0.4 1.5 INPUT VOLTAGE (V) 1.0 SWITCH CURRENT LIMIT (A) SWITCH SATURATION VOLTAGE (V) TA = 25°C 1.0 0.5 0.2 0 0 0.2 0.4 0.6 0.8 1.0 SWITCH CURRENT (A) 1.2 0 1.4 2.7 2.6 0 5.32 5.30 4.28 4.26 50 25 75 0 TEMPERATURE (°C) 100 125 60 40 0 –20 –40 –60 1.50 280 275 270 100 125 1424-5 G07 VC THRESHOLD 1.25 1.00 –80 4.50 4.75 5.00 5.25 5.50 5.75 FLYBACK VOLTAGE (V) 6.00 0.75 –50 –25 6.25 50 25 75 0 TEMPERATURE (°C) 100 SHDN Pin Input Current vs Voltage 2.50 1 TA = 25°C 2.25 2.00 1.75 1.50 1.25 1.00 0.75 –50 –25 125 1424-5 G06 SHDN PIN INPUT CURRENT (µA) 285 50 25 75 0 TEMPERATURE (°C) 1.75 1424-5 G05 MINIMUM SYNCHRONIZATION VOLTAGE (VP-P) 290 VC HIGH CLAMP 2.00 Minimum Synchronization Voltage vs Temperature 295 265 – 50 – 25 2.25 20 Switching Frequency vs Temperature 125 2.50 25°C 125°C –55°C 1424-5 G04 300 100 VC Pin Threshold and High Clamp Voltage vs Temperature VC PIN VOLTAGE (V) FEEDBACK AMPLIFIER OUTPUT CURRENT (µA) 5.34 50 25 75 0 TEMPERATURE (°C) 1424-5 G03 Feedback Amplifier Output Current vs Flyback Voltage 5.36 4.24 – 50 – 25 2.4 –50 –25 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 1424-5 G02 Reference Voltage vs Temperature REFERENCE VOLTAGE (V) 2.8 2.5 1424-5 G01 SWITCHING FREQUENCY (kHz) 2.9 50 25 75 0 TEMPERATURE (°C) 100 125 1424-5 G08 0 –1 –2 –3 –4 0 1 3 4 2 SHDN PIN VOLTAGE (V) 5 1424-5 G09 sn14245 14245fs 4 LT1424-5 U W TYPICAL PERFOR A CE CHARACTERISTICS Flyback Enable Delay Time vs Temperature Minimum Flyback Enable Time vs Temperature 250 275 250 225 250 200 225 225 200 175 150 125 ENABLE TIME (ns) 275 ENABLE DELAY TIME (ns) SWITCH ON TIME (ns) Minimum Switch On Time vs Temperature 175 150 125 100 100 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 75 – 50 – 25 200 175 150 125 50 25 75 0 TEMPERATURE (°C) 1424-5 G10 100 125 1424-5 G11 100 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 1424-5 G12 U U U PIN FUNCTIONS SHDN (Pin 1): Shutdown. This pin is used to turn off the regulator and reduce VIN input current to a few tens of microamperes. The SHDN pin can be left floating when unused. PGND (Pin 5): Power Ground. This pin is the emitter of the power switch device and has large currents flowing through it. It should be connected directly to a good quality ground plane. VC (Pin 2): Control Voltage. This pin is the output of the feedback amplifier and the input of the current comparator. Frequency compensation of the overall loop is effected by placing a capacitor between this node and ground. VSW (Pin 6): This is the collector node of the output switch and has large currents flowing through it. Keep the traces to the switching components as short as possible to minimize electromagnetic radiation and voltage spikes. SYNC (Pin 3): Pin to synchronize internal oscillator to external frequency reference. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. If unused, this pin should be tied to ground. VIN (Pin 7): Supply Voltage. Bypass input supply pin with 10µF or more. The part goes into undervoltage lockout when VIN drops below 2.8V. Undervoltage lockout stops switching and pulls the VC pin low. SGND (Pin 4): Signal Ground. This pin is a clean ground. The internal reference and feedback amplifier are referred to it. Keep the ground path connection to the VC compensation capacitor free of large ground currents. RCCOMP (Pin 8): Pin for the External Filter Capacitor for Load Compensation Function. A common 0.1µF ceramic capacitor will suffice. sn14245 14245fs 5 LT1424-5 W BLOCK DIAGRAM VIN RFB 2.6V REGULATOR SHDN RREF VSW FLYBACK ERROR AMPLIFIER 285kHz OSCILLATOR SYNC LOGIC DRIVER RCCOMP LOAD COMPENSATION COMP ROCOMP SGND VC + CURRENT AMPLIFIER GND IS OMITTED FOR CLARITY – RSENSE PGND 1424-5 BD W W FLYBACK ERROR A PLIFIER DIAGRA D1 VIN T1 + • VSW + ISOLATED VOUT C1 • – VIN D2 Q4 RFB IM IFXD VC Q1 ENABLE Q2 Q3 CEXT VBG RREF I IM 1424-5 EA sn14245 14245fs 6 LT1424-5 WU W TI I G DIAGRA VSW VOLTAGE COLLAPSE DETECT VFLBK 0.80× VFLBK VIN GND SWITCH STATE OFF OFF ON MINIMUM tON FLYBACK AMP STATE ON ENABLE DELAY DISABLED MINIMUM ENABLE TIME ENABLED DISABLED 1424-5 TD sn14245 14245fs 7 LT1424-5 U OPERATION The LT1424-5 is a current mode switching regulator IC that has been designed specifically for the isolated flyback topology. The special problem normally encountered in such circuits is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated to the primary side in order to maintain regulation. Historically, this has been done with optoisolators or extra transformer windings. Optoisolator circuits waste output power and the extra components they require increase the cost and physical volume of the power supply. Optoisolators can also exhibit trouble due to limited dynamic response (temporal), nonlinearity, unit-to-unit variation and aging over life. Circuits employing extra transformer windings also exhibit deficiencies. The extra winding adds to the transformer’s physical size and cost. Dynamic response is often mediocre. There is usually no method for maintaining load regulation versus load. The LT1424-5 derives its information about the isolated output voltage by examining the primary side flyback pulse waveform. In this manner no optoisolator nor extra transformer winding is required. This IC is a quantum improvement over previous approaches because: target output voltage is programmed by resistor ratio, regulation is maintained well into discontinuous mode and optional load compensation is available. The Block Diagram shows an overall view of the system. Many of the blocks are similar to those found in traditional designs including: internal bias regulator, oscillator, logic, current amplifier and comparator, driver and output switch. The novel sections include a special flyback error amplifier and a load compensation mechanism. Also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs. The RREF, RFB and ROCOMP resistors in the Block Diagram are application-specific thin-film resistors internal to the LT1424-5. The capacitor connected to the RCCOMP pin is external. The LT1424-5 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier which derives its feedback information from the flyback pulse. Due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. A good source of information on these topics is LTC’s Application Note 19. ERROR AMPLIFIER—PSEUDO DC THEORY Please refer to the simplified diagram of the Flyback Error Amplifier. Operation is as follows: when output switch Q4 turns off, its collector voltage rises above the VIN rail. The amplitude of this flyback pulse, i.e., the difference between it and VIN, is given as: + VF + (ISEC)(ESR) V VFLBK = OUT NSP VF = D1 forward voltage ISEC = Transformer secondary current ESR = Total impedance of secondary circuit NSP = Transformer effective secondary-to-primary turns ratio The flyback voltage is then converted to a current by the action of RFB and Q1. Nearly all of this current flows through resistor RREF to form a ground-referred voltage. This is then compared to the internal bandgap reference by the differential transistor pair Q2/Q3. The collector current from Q2 is mirrored around and subtracted from fixed current source IFXD at the VC pin. An external capacitor integrates this net current to provide the control voltage to set the current mode trip point. The relatively high gain in the overall loop will then cause the voltage at the RREF resistor to be nearly equal to the bandgap reference VBG. The relationship between VFLBK and VBG may then be expressed as: V V α FLBK = BG or, RFB RREF VFLBK = VBG ) )) ) RFB RREF 1 α α = Ratio of Q1 IC to IE VBG = Internal bandgap reference sn14245 14245fs 8 LT1424-5 U OPERATION Combination with the previous VFLBK expression yields an expression for VOUT, in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: VOUT = VBG ) )) ) RFB RREF NSP α – VF – ISEC (ESR) Additionally, it includes the effect of nonzero secondary output impedance. See Load Compensation for details. The practical aspects of applying this equation for VOUT are found in the Applications Information section. So far, this has been a pseudo-DC treatment of flyback error amplifier operation. But the flyback signal is a pulse, not a DC level. Provision must be made to enable the flyback amplifier only when the flyback pulse is present. This is accomplished by the dashed line connections to the block labeled “ENABLE”. Timing signals are then required to enable and disable the flyback amplifier. ERROR AMPLIFIER—DYNAMIC THEORY There are several timing signals that are required for proper LT1424-5 operation. Please refer to the Timing Diagram. Minimum Output Switch ON Time The LT1424-5 effects output voltage regulation via flyback pulse action. If the output switch is not turned on at all, there will be no flyback pulse, and output voltage information is no longer available. This would cause irregular loop response and start-up/latchup problems. The solution chosen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. This in turn establishes a minimum load requirement to maintain regulation. See Applications Information section for further details. Enable Delay When the output switch shuts off, the flyback pulse appears. However, it takes a finite time until the transformer primary side voltage waveform approximately rep- resents the output voltage. This is partly due to rise time on the VSW node, but more importantly due to transformer leakage inductance. The latter causes a voltage spike on the primary side not directly related to output voltage. (Some time is also required for internal settling of the feedback amplifier circuitry.) In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay”. In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information section for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, that compares the flyback voltage (RREF referred) to a fixed reference, nominally 80% of VBG. When the flyback waveform drops below this level, the feedback amplifier is disabled. This action accommodates both continuous and discontinuous mode operation. Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed “minimum enable time”. This prevents lock-up, especially when the output voltage is abnormally low, e.g., during start-up. The minimum enable time period ensures that the VC node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. The “minimum enable time” often determines the low load level at which output voltage regulation is lost. See Applications Information section for details. Effects of Variable Enable Period It should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. This can vary from the fixed “minimum enable time” described to a maximum of roughly the OFF switch time minus the enable delay sn14245 14245fs 9 LT1424-5 U OPERATION time. Certain parameters of flyback amp behavior will then be directly affected by the variable enable period. These include effective transconductance and VC node slew rate. LOAD COMPENSATION THEORY The LT1424-5 uses the flyback pulse to obtain information about the isolated output voltage. A potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. This has been represented previously by the expression (ISEC)(ESR). However, it is generally more useful to convert this expression to an effective output impedance. Because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle. That is, ROUT = ESR ) ) 1 where, DC OFF ROUT = Effective supply output impedance ESR = Lumped secondary impedance DC OFF = OFF duty cycle Expressing this in terms of the ON duty cycle, remembering DC OFF = 1 – DC, ROUT = ESR ) ) 1 1 – DC DC = ON duty cycle In less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external RFB resistor value adjusted to compensate for nominal expected error. In more demanding applications, output impedance error may be minimized by the use of the load compensation function. To implement the load compensation function, a voltage is developed that is proportional to average output switch current. This voltage is then impressed across the internal ROCOMP resistor and the resulting current is then subtracted from the RFB node. As output loading increases, average switch current increases to maintain rough output voltage regulation. This causes an increase in ROCOMP resistor current subtracted from the RFB node, through which feedback loop action causes a corresponding increase in target output voltage. Assuming a relatively fixed power supply efficiency, Eff Power Out = (Eff)(Power In) (VOUT)(IOUT) = (Eff)(VIN)(IIN) Average primary side current may be expressed in terms of output current as follows: IIN = ) ) VOUT I (VIN)(Eff) OUT combining the efficiency and voltage terms in a single variable, IIN = K1(IOUT) where, K1 = ) VOUT (VIN)(Eff) ) Switch current is converted to voltage by a sense resistor and amplified by the current sense amplifier with associated gain G. This voltage is then impressed across the internal ROCOMP resistor to form a current that is subtracted from the RFB node. So the effective change in VOUT target is: ∆VOUT = K1(∆IOUT) ) ) (RSENSE)(G) RFB and, ROCOMP ) RFB ∆VOUT = K1(RSENSE)(G) ROCOMP ∆IOUT ) Nominal output impedance cancellation is obtained by equating this expression with ROUT. For simplicity, the data sheet refers to ∆VREF/∆ISW. This is given as: ) RFB ∆VREF = (RSENSE)(G) ROCOMP ∆ISW ) sn14245 14245fs 10 LT1424-5 U W U U APPLICATIONS INFORMATION The LT1424-X is an application-specific 8-pin part which implements an isolated flyback switcher/controller. Three on-chip thin-film resistors are used to “program” the part for a specific application including mainly desired output voltage, transformer turns ratio and secondary circuit ESR behavior. As of Initial Release, two versions of the LT1424 are available. The LT1424-5, described herein, implements an isolated 5V output power supply using off-theshelf 1:1 transformers as shown in the Typical Applications. The LT1424-9, described in a separate data sheet, implements an isolated – 9V output LAN supply with PCMCIA Type II height compatible components. Potential users with a high volume requirement for other applications are advised as follows: general experimentation/breadboarding may be done with the LT1425. This is a general purpose 16-pin part whose functionality is similar to the LT1424-X, with the exception that the three application resistors are external user-supplied components. Application information relating to the proper selection of these resistor values is contained within the LT1425 data sheet. Once technical feasibility is demonstrated, the potential user may discuss the possibility of an additional LT1424-X version with the factory. OUTPUT VOLTAGE ERROR SOURCES Conventional nonisolated switching power supply ICs typically have only two substantial sources of output voltage error— the internal or external resistor divider network that connects to VOUT and the internal IC reference. The LT1424-5, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. Some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. Here is a list of possible error sources and their effective contribution: Internal Voltage Reference The internal bandgap voltage reference is, of course, imperfect. Its error, both at 25°C and over temperature is already included in the specifications for Reference Voltage. Schottky Diode Drop The LT1424-5 senses the output voltage from the transformer primary side during the flyback portion of the cycle. This sensed voltage therefore includes the forward drop, VF, of the rectifier (usually a Schottky diode). Lot-to-lot and ambient temperature variations will show up as output voltage shift/drift. Secondary Leakage Inductance Leakage inductance on the transformer secondary reduces the effective primary-to-secondary turns ratio (NP/NS) from its ideal value. This increases the output voltage target by a similar percentage and has been nominally taken into account in the design of the LT1424-5. To the extent that secondary leakage inductance varies from part-topart, the output voltage will be affected. Output Impedance Error The LT1424-5 contains a load compensation function to provide a nominal, first-order cancellation of the effects of secondary circuit ESR. Unit-to-unit variation plus some inherent nonlinearity in the cancellation results in some residual VOUT variation with load. MINIMUM LOAD CONSIDERATIONS The LT1424-5 generally provides better low load performance than previous generation switcher/controllers utilizing indirect output voltage sensing techniques. Specifically, it contains circuitry to detect flyback pulse “collapse,” thereby supporting operation well into discontinuous mode. In general, there are two possible constraints to ultimate low load operation, minimum switch ON time which sets a minimum level of delivered power, and minimum flyback enable time, which deals with the ability of the feedback system to derive valid output voltage information from the flyback pulse. In the application for which the LT1424-5 is designed, the minimum flyback enable time is more restrictive. The LT1424-5 derives its output voltage information from the flyback pulse. If the internal minimum enable time sn14245 14245fs 11 LT1424-5 U U W U APPLICATIONS INFORMATION pulse extends beyond the flyback pulse, loss of regulation will occur. The onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, tED, plus the minimum enable time, tEN. Minimum power delivered to the load is then: ) )) ) 1 f [V • (t + t )]2 2 LSEC OUT EN ED = (VOUT)(IOUT) Min Power = Which yields a minimum output constraint: IOUT(MIN) = ) )) ) 1 f(VOUT) (tED + tEN)2, where LSEC 2 f = Switching frequency (nominally 285kHz) LSEC = Transformer secondary side inductance VOUT = Output voltage tED = Enable delay time tEN = Minimum enable time In reality, the previously derived expression is a conservative one, as it assumes perfectly “square” waveforms, which is not the case at light load. Furthermore, the equation was set up to yield just the onset of control error. In other words, while the equation suggests a minimum load current of perhaps 3mA, laboratory observations suggest operation down to 1mA to 2mA before significant output voltage rise is observed. Nevertheless, this situation is addressed in the application by the use of a fixed 1.8k load resistor, which preloads the supply with a nominal 2.8mA. MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS The LT1424-5 is a current mode controller. It uses the VC node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 1.9V, then acts as an output switch peak current limit. This action becomes the switch current limit specification. The maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. Short-circuit conditions are handled by the same mechanism. The output switch turns on, peak current is quickly reached and the switch is turned off. Because the output switch is only on for a small fraction of the available period, internal power dissipation is controlled. (The LT1424-5 contains an internal overtemperature shutdown circuit, that disables switch action, just in case.) THERMAL CONSIDERATIONS Care should be taken to ensure that the worst-case input voltage and load current conditions do not cause excessive die temperatures. The packages are rated at 110°C/W for SO-8 and 130°C/W for N8. Average supply current (including driver current) is: ) ) I IIN = 7mA + DC SW where, 35 ISW = Switch current DC = On switch duty cycle Switch power dissipation is given by: PSW = (ISW)2(RSW)(DC) RSW = Output switch ON resistance Total power dissipation of the die is the sum of supply current times supply voltage plus switch power: PD(TOTAL) = (IIN • VIN) + PSW FREQUENCY COMPENSATION Loop frequency compensation is performed by connecting a capacitor from the output of the error amplifier (VC pin) to ground. An additional series resistor, often required in traditional current mode switcher controllers is usually not required; and can even prove detrimental. The phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a “zero” to the loop response. sn14245 14245fs 12 LT1424-5 U W U U APPLICATIONS INFORMATION power paths (primary and secondary). B field (magnetic) radiation is minimized by keeping output diode, switch pin and output bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected to the switch pin. A ground plane should always be used under the switcher circuitry to prevent interplane coupling. In further contrast to traditional current mode switchers, VC pin ripple is generally not an issue with the LT1424-5. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VC voltage changes during the flyback pulse, but is then “held” during the subsequent “switch ON” portion of the next cycle. This action naturally holds the VC voltage stable during the current comparator sense action (current mode switching). The high speed switching current paths are shown schematically in Figure 1. Minimum lead length in these paths are essential to ensure clean switching and minimal EMI. The path containing the input capacitor, transformer primary, output switch, the path containing the transformer secondary, output diode and output capacitor are the only ones containing nanosecond rise and fall times. Keep these paths as short as possible. PCB LAYOUT CONSIDERATIONS For maximum efficiency, switch rise and fall times are made as short as practical. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the VOUT • VIN HIGH FREQUENCY CIRCULATING PATH • HIGH FREQUENCY CIRCULATING PATH ISOLATED LOAD F 1424-5 F01 Figure 1 sn14245 14245fs 13 LT1424-5 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) sn14245 14245fs 14 LT1424-5 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 0996 sn14245 14245fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1424-5 U TYPICAL APPLICATION Triple Isolated 5V Supply MBR0530 5V T1 + 22µF 35V 6 0.1µF 1 2 1nF 3 4 8 SHDN RCCOMP 7 VC VIN LT1424-5 6 VSW SYNC 5 PGND SGND • • 12 3 + 9 100µF 10V 1k 1N752A 5V 0.12A MBR0530 0.1µF INPUT COM 5 • • 10 2 T1: COILTRONICS CTX02-13835 ER11/5 N = 1:1:1:1:1:1 LP = 27.4µH + 7 100µF 10V 1k 1N752A 5V 0.12A MBR0530 4 1 • + 8 • 11 100µF 10V 1k 1N752A 5V 0.12A 1424-5 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1105 Off-Line Switching Regulator Built-In Isolated Regulation Without Optoisolator LTC 1145/46 Isolated Digital Data Transceivers Up to 200kbps Data Rate, UL Listed LT1170/71/72 5A/3A/1.25A Flyback Regulators Isolated Flyback Mode for Higher Currents LT1370/71 6A/3A Flyback Regulators Uses Small Magnetics LT1372/77 500kHz/1MHz Boost/Flyback Regulators Uses Ultrasmall Magnetics LT1424-9 Isolated Flyback Switching Regulator with 9V Output Implements – 9V PCMCIA Type II LAN Supply LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistors ® sn14245 14245fs 16 Linear Technology Corporation LT/TP 0599 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1998