LT1795
Dual 500mA/50MHz
Current Feedback Line Driver
Amplifier
DESCRIPTIO
U
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
The LT®1795 is a dual current feedback amplifier with high
output current and excellent large signal characteristics.
The combination of high slew rate, 500mA output drive
and up to ±15V operation enables the device to deliver
significant power at frequencies in the 1MHz to 2MHz
range. Short-circuit protection and thermal shutdown
insure the device’s ruggedness. The LT1795 is stable with
large capacitive loads and can easily supply the large
currents required by the capacitive loading. A shutdown
feature switches the device into a high impedance, low
current mode, reducing power dissipation when the device is not in use. For lower bandwidth applications, the
supply current can be reduced with a single external
resistor.
500mA Output Drive Current
50MHz Bandwidth, AV = 2, RL = 25Ω
900V/µs Slew Rate, AV = 2, RL = 25Ω
Low Distortion: –75dBc at 1MHz
High Input Impedance, 10MΩ
Wide Supply Range, ±5V to ±15V
Full Rate, Downstream ADSL Supported
Low Power Shutdown Mode
Power Saving Adjustable Supply Current
Stable with CL = 10,000pF
Power Enhanced Small Footprint Packages
TSSOP-20, S0-20 Wide
Available in a 20-Lead TSSOP Package
U
APPLICATIO S
■
■
■
■
The LT1795 comes in the very small, thermally enhanced,
20-lead TSSOP package for maximum port density in line
driver applications.
ADSL HDSL2, G.lite Drivers
Buffers
Test Equipment Amplifiers
Video Amplifiers
Cable Drivers
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
■
TYPICAL APPLICATION
Low Loss, High Power Central Office ADSL Line Driver
V+
+IN
+
1/2
LT1795
12.5Ω
–
1k
1:2*
165Ω
100Ω
1k
–
1/2
LT1795
–IN
12.5Ω
+
V–
* MIDCOM 50215 OR EQUIVALENT
1795 TA01
1795fa
1
LT1795
W W
U
W
ABSOLUTE
AXI U RATI GS
(Note 1)
Supply Voltage ...................................................... ±18V
Input Current ...................................................... ±15mA
Output Short-Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range ................ – 40°C to 85°C
Specified Temperature Range (Note 3) ... – 40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V–
1
20
V–
NC 2
19 NC
–IN 3
18 OUT
+IN 4
17
ORDER PART
NUMBER
V+
LT1795CFE
LT1795IFE
COMP 1
V+ 2
OUT 3
V–
4
20 COMP
19 V +
LT1795CSW
LT1795ISW
18 OUT
17
V–
SHDN 5
16 COMP
V– 5
16 V –
SHDNREF 6
15 COMP
V–
6
15 V –
+IN 7
14 V +
V–
7
14 V –
–IN 8
13 OUT
–IN 8
13 –IN
NC 9
12 NC
+IN 9
12 +IN
V – 10
11 V –
SHDN 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
ORDER PART
NUMBER
TOP VIEW
11 SHDNREF
S PACKAGE
20-LEAD PLASTIC SW
TJMAX = 150° C, θJA ≈ 40°C/W (Note 4)
TJMAX = 150° C, θJA = 40°C/W (Note 4)
UNDERSIDE METAL INTERNALLY CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, ±5V ≤ VS ≤ ±15V, pulse tested, VSHDN = 2.5V, VSHDNREF = 0V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
VOS
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
●
±3
±4.5
±13
±17
mV
mV
●
±1
±1.5
±3.5
±5.0
mV
mV
●
10
●
±2
±8
±5
±20
µA
µA
●
±0.5
±1.5
±2
±7
µA
µA
●
±10
±20
±70
±100
µA
µA
●
±10
±20
±30
±50
µA
µA
Input Offset Voltage Matching
Input Offset Voltage Drift
IIN
+
Noninverting Input Current
Noninverting Input Current Matching
IIN–
Inverting Input Current
Inverting Input Current Matching
µV/°C
en
Input Noise Voltage Density
f = 10kHz, RF =1k, RG = 10Ω, RS = 0Ω
3.6
nV/√Hz
+ in
Input Noise Current Density
f = 10kHz, RF =1k, RG = 10Ω, RS = 10kΩ
2
pA/√Hz
– in
Input Noise Current Density
f = 10kHz, RF =1k, RG = 10Ω, RS = 10kΩ
30
pA/√Hz
1795fa
2
LT1795
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, ±5V ≤ VS ≤ ±15V, pulse tested, VSHDN = 2.5V, VSHDNREF = 0V unless otherwise noted. (Note 3)
SYMBOL
RIN
+
PARAMETER
CONDITIONS
Input Resistance
VIN = ±12V, VS = ±15V
V = ±2V, VS = ±5V
MIN
TYP
MAX
UNITS
●
●
1.5
0.5
10
5
MΩ
MΩ
Input Capacitance
VIN = ±15V
2
pF
Input Voltage Range (Note 5)
VS = ±15V
VS = ±5V
●
●
±12
±2
±13.5
±3.5
V
V
Common Mode Rejection Ratio
VS = ±15V, VCM = ±12V
VS = ±5V, VCM = ±2V
●
●
55
50
62
60
dB
dB
Inverting Input Current
Common Mode Rejection
VS = ±15V, VCM = ±12V
VS = ±5V, VCM = ±2V
●
●
Power Supply Rejection Ratio
VS = ±5V to ±15V
●
Noninverting Input Current
Power Supply Rejection
VS = ±5V to ±15V
●
30
500
nA/V
Inverting Input Current
Power Supply Rejection
VS = ±5V to ±15V
●
1
5
µA/V
AV
Large-Signal Voltage Gain
VS = ±15V, VOUT = ±10V, RL = 25Ω
VS = ±5V, VOUT = ±2V, RL = 12Ω
●
●
55
55
68
68
dB
dB
ROL
Transresistance, ∆VOUT/∆IIN –
VS = ±15V, VOUT = ±10V, RL = 25Ω
VS = ±5V, VOUT = ±2V, RL = 12Ω
●
●
75
75
200
200
kΩ
kΩ
VOUT
Maximum Output Voltage Swing
VS = ±15V, RL = 25Ω
●
±11.5
±10.0
±12.5
±11.5
V
V
●
±2.5
±2.0
±3
±3
V
V
●
0.5
CIN+
CMRR
PSRR
VS = ±5V, RL = 12Ω
IOUT
Maximum Output Current
VS = ±15V, RL = 1Ω
IS
Supply Current Per Amplifier
VS = ±15V, VSHDN = 2.5V
Supply Current Per Amplifier,
RSHDN = 51k, (Note 6)
VS = ±15V
1
1
60
77
VS = ±15V, VSHDN = 0.4V
VS = ±15V, VSHDN = 0.4V
●
dB
1
A
34
42
mA
mA
15
20
25
mA
mA
●
Output Leakage Current, Shutdown
µA/V
µA/V
29
●
Positive Supply Current, Shutdown
10
10
1
200
µA
1
200
µA
Channel Separation
VS = ±15V, VOUT = ±10V, RL = 25Ω
HD2, HD3
2nd and 3rd Harmonic Distortion
Differential Mode
f = 1MHz, VO = 20VP-P, RL = 50, AV = 2
SR
Slew Rate (Note 7)
AV = 4, RL = 400Ω
Slew Rate
AV = 4, RL = 25Ω
900
V/µs
Small-Signal BW
AV = 2, VS = ±15V, Peaking ≤ 1.5dB
RF = RG = 910Ω, RL = 100Ω
65
MHz
AV = 2, VS = ±15V, Peaking ≤ 1.5dB
RF = RG = 820Ω, RL = 25Ω
50
MHz
BW
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Applies to short-circuits to ground only. A short-circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.
Note 3: The LT1795C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at – 40°C and 85°C. The
LT1795I is guaranteed to meet the extended temperature limits.
80
400
110
dB
–75
dBc
900
V/µs
Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Note 5: Guaranteed by the CMRR tests.
Note 6: RSHDN is connected between the SHDN pin and V +.
Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±15V supplies with RF = 1k, RG = 333Ω (AV = +4) and
RL = 400Ω.
1795fa
3
LT1795
W
SMALL-SIGNAL BANDWIDTH
U
U
RSD = 0Ω, IS = 30mA per Amplifer, VS = ±15V,
Peaking ≤ 1dB, RL = 25Ω
RSD = 51kΩ, IS = 15mA per Amplifer, VS = ±15V,
Peaking ≤ 1dB, RL = 25Ω
AV
RF
RG
–3dB BW
(MHz)
AV
RF
RG
–3dB BW
(MHz)
–1
976
976
44
–1
976
976
30
1
1.15k
—
53
1
1.15k
—
32
2
976
976
48
2
976
976
32
10
649
72
46
10
649
72
27
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V+
35
OUTPUT SATURATION VOLTAGE (V)
VS = ±15V
AV = 1
RL = ∞
RSD = 0Ω
30
25
20
15
RSD = 51kΩ
10
5
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
VS = ±15V
–1
2.0
RL = 2k
–2
RL = 25Ω
–3
–4
4
3
RL = 25Ω
2
1
RL = 2k
V–
–50 –25
125
25 50
0
75
TEMPERATURE (°C)
LT1795 G01
DISTORTION (dBc)
CURRENT INTO SHDN PIN (mA)
–50
0.3
0.2
SOURCING
1.2
SINKING
1.0
0.8
1
2
3
4
VOLTAGE APPLIED AT SHDN PIN (V)
50
25
75
0
TEMPERATURE (°C)
100
–60
5
1795 G04
125
LT1795 G03
Third Harmonic Distortion vs
Frequency
–40
AV = 2 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50Ω
IQ PER AMPLIFIER
–50
IQ = 5mA
–70
IQ = 10mA
–80
–90
0.1
0
1.4
0.6
–50 –25
125
–40
0.4
0
1.6
Second Harmonic Distortion vs
Frequency
VS = ±15V
VSHDNREF = 0V
0.5
100
VS = ±15V
1.8
LT1795 G02
SHDN Pin Current vs Voltage
0.6
Output Short-Circuit Current vs
Junction Temperature
DISTORTION (dBc)
40
SUPPLY CURRENT PER AMPLIFIER (mA)
Output Saturation Voltage vs
Junction Temperature
OUTPUT SHORT-CIRCUIT CURRENT (A)
Supply Current vs Ambient
Temperature
–100
10k
IQ = 15mA
–70
–80
IQ = 5mA
IQ = 10mA
IQ = 20mA
–90
IQ = 20mA
100k
FREQUENCY (Hz)
–60
AV = 2 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50Ω
IQ PER AMPLIFIER
1M
LT1795 G05
IQ = 15mA
–100
10k
100k
FREQUENCY (Hz)
1M
LT1795 G06
1795fa
4
LT1795
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Second Harmonic Distortion vs
Frequency
Third Harmonic Distortion vs
Frequency
–40
–60
AV = 10 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50Ω
IQ PER AMPLIFIER
–70
IQ = 5mA
–50
IQ = 20mA
–70
–80
IQ = 10mA
–50
DISTORTION (dBc)
–60
–40
–40
AV = 10 DIFFERENTIAL
VOUT = 20VP-P
VS = ±15V
RLOAD = 50Ω
IQ PER AMPLIFIER
DISTORTION (dBc)
DISTORTION (dBc)
–50
Second Harmonic Distortion vs
Frequency
IQ = 10mA
–80
IQ = 15mA
–90
IQ = 5mA
IQ = 20mA
–90
–60
AV = 2 DIFFERENTIAL
VOUT = 20VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 5mA
–70
IQ = 10mA
–80
IQ = 15mA
–90
IQ = 15mA
–100
10k
100k
FREQUENCY (Hz)
–100
10k
1M
100k
FREQUENCY (Hz)
1M
LT1795 G07
Third Harmonic Distortion vs
Frequency
–40
–40
IQ = 5mA
–70
IQ = 20mA
–80
–60
AV = 10 DIFFERENTIAL
VOUT = 20VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
–70
AV = 10 DIFFERENTIAL
VOUT = 20VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
–50
IQ = 20mA
–80
IQ = 10mA
DISTORTION (dBc)
–50
DISTORTION (dBc)
DISTORTION (dBc)
–60
–60
IQ = 5mA
–70
–80
IQ = 15mA
–90
–90
IQ = 15mA
IQ = 10mA
–90
IQ = 5mA
IQ = 10mA
–100
10k
100k
FREQUENCY (Hz)
–100
10k
1M
100k
FREQUENCY (Hz)
LT1795 G10
IQ = 5mA
–80
–90
–40
IQ = 10mA
IQ = 20mA
IQ = 15mA
–60
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
–50
IQ = 5mA
DISTORTION (dBc)
–50
–70
1M
Second Harmonic Distortion vs
Frequency
–40
DISTORTION (dBc)
DISTORTION (dBc)
–60
100k
FREQUENCY (Hz)
LT1795 G12
Third Harmonic Distortion vs
Frequency
–40
–50
IQ = 15mA
–100
10k
1M
IQ = 20mA
LT1795 G11
Second Harmonic Distortion vs
Frequency
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
1M
LT1795 G09
Second Harmonic Distortion vs
Frequency
–40
–50
100k
FREQUENCY (Hz)
LT1795 G08
Third Harmonic Distortion vs
Frequency
AV = 2 DIFFERENTIAL
VOUT = 20VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 20mA
–100
10k
IQ = 10mA
–70
–80
IQ = 15mA
–90
–60
AV = 10 DIFFERENTIAL
VOUT = 4VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 10mA
–70
–80
–90
IQ = 5mA
IQ = 15mA
IQ = 20mA
IQ = 20mA
–100
10k
100k
FREQUENCY (Hz)
1M
LT1795 G13
–100
10k
100k
FREQUENCY (Hz)
1M
LT1795 G14
–100
10k
100k
FREQUENCY (Hz)
1M
LT1795 G15
1795fa
5
LT1795
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Third Harmonic Distortion vs
Frequency
–40
IQ = 5mA
IQ = 10mA
–70
IQ = 15mA
–80
–90
–60
IQ = 5mA
IQ = 10mA
–80
IQ = 20mA
IQ = 20mA
–90
100k
FREQUENCY (Hz)
1M
–50
–70
–100
–110
10k
–40
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50Ω
IQ PER AMPLIFIER
–50
DISTORTION (dBc)
DISTORTION (dBc)
–60
AV = 10 DIFFERENTIAL
VOUT = 4VP-P
VS = ±12V
RLOAD = 50Ω
IQ PER AMPLIFIER
–100
10k
100k
FREQUENCY (Hz)
1M
–70
–50
IQ = 15mA
IQ = 10mA
–80
IQ = 5mA
–90
–100
10k
–100
10k
–60
1M
AV = 10 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 5mA
IQ = 10mA
–70
IQ = 15mA
–80
–90
100k
FREQUENCY (Hz)
IQ = 20mA
–100
10k
1M
100k
FREQUENCY (Hz)
1M
LT1795 G20
–3dB Bandwidth vs
Supply Current
Slew Rate vs Supply Current
50
1200
1000
800
FALLING
600
VS = ±15V
TA =25°C
AV = 4
RLOAD = 25Ω
RF = 1k
25
15
7.5 10
20
30
SUPPLY CURRENT PER AMPLIFIER (mA)
1795 • G21
–3dB BANDWIDTH (MHz)
45
RISING
SLEW RATE (V/µs)
100k
FREQUENCY (Hz)
LT1795 G18
LT1795 G19
0
IQ = 20mA
–40
AV = 10 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 20mA
200
IQ = 15mA
–80
Third Harmonic Distortion vs
Frequency
DISTORTION (dBc)
DISTORTION (dBc)
IQ = 10mA
–70
LT1795 G17
–40
400
IQ = 5mA
–90
Second Harmonic Distortion vs
Frequency
–60
–60
AV = 2 DIFFERENTIAL
VOUT = 4VP-P
VS = ±5V
RLOAD = 50Ω
IQ PER AMPLIFIER
IQ = 15mA
LT1795 G16
–50
DISTORTION (dBc)
–40
–50
Third Harmonic Distortion vs
Frequency
Second Harmonic Distortion vs
Frequency
40
35
30
VS = ±15V
TA =25°C
AV = 4
RLOAD = 25Ω
RF = 1k
25
25
15
20
30
7.5 10
SUPPLY CURRENT PER AMPLIFIER (mA)
1795 • G22
1795fa
6
LT1795
U
U
W
U
APPLICATIO S I FOR ATIO
The LT1795 is a dual current feedback amplifier with high
output current drive capability. The amplifier is designed
to drive low impedance loads such as twisted-pair transmission lines with excellent linearity.
When VSHDN = VSHDNREF, the device is shut down. The
device will interface directly with 3V or 5V CMOS logic
when SHDNREF is grounded and the control signal is
applied to the SHDN pin. Switching time between the
active and shutdown states is about 1.5µs.
SHUTDOWN/CURRENT SET
Figures 1 to 4 illustrate how the SHDN and SHDNREF pins
can be used to reduce the amplifier quiescent current. In
both cases, an external resistor is used to set the current.
The two approaches are equivalent, however the required
resistor values are different. The quiescent current will be
approximately 115 times the current in the SHDN pin and
230 times the current in the SHDNREF pin. The voltage
across the resistor in either condition is V + – 1.5V. For
example, a 50k resistor between V + and SHDN will set the
If the shutdown/current set feature is not used, connect
SHDN to V + and SHDNREF to ground.
The SHDN and SHDNREF pins control the biasing of the
two amplifiers. The pins can be used to either turn off the
amplifiers completely, reducing the quiescent current to
less then 200µA, or to control the quiescent current in
normal operation.
V+
V+
10 SHDN
RSHDN
11 SHDNREF
10 SHDN
RSHDNREF
11 SHDNREF
1795 F03
1795 F01
Figure 1. RSHDN Connected Between V + and SHDN (Pin 10);
SHDNREF (Pin 11) = GND. See Figure 2
Figure 3. RSHDNREF Connected Between SHDNREF (Pin 11)
and GND; SHDN (Pin 10) = V +. See Figure 4
80
80
TA = 25°C
VS = ±15V
70
AMPLIFIER SUPPLY CURRENT,
ISY – mA (BOTH AMPLIFIERS)
AMPLIFIER SUPPLY CURRENT,
ISY – mA (BOTH AMPLIFIERS)
70
60
50
40
30
20
10
TA = 25°C
VS = ±15V
60
50
40
30
20
10
0
0
0
25
50
75 100 125 150 175 200 225
RSHDN (kΩ)
1795 F02
Figure 2. LT1795 Amplifier Supply Current vs RSHDN. RSHDN
Connected Between V+ and SHDN, SHDNREF = GND (See
Figure 1)
50 100 150 200 250 300 350 400 450 500
RSHDNREF (kΩ)
1795 F04
Figure 4. LT1795 Amplifier Supply Current vs RSHDNREF.
RSHDNREF Connected Between SHDNREF and GND,
SHDN = V+ (See Figure 3)
1795fa
7
LT1795
U
U
W
U
APPLICATIO S I FOR ATIO
quiescent current to 33mA with VS = ±15V. If ON/OFF
control is desired in addition to reduced quiescent current,
then the circuits in Figures 5 to 7 can be employed.
Figure 8 illustrates a partial shutdown with direct logic
control. By keeping the output stage slightly biased on, the
output impedance remains low, preserving the line termination. The design equations are:
V+
R1 =
RSHDN
RB
10k
OFF
10 SHDN
Q1
ON
INTERNAL
LOGIC THRESHOLD
~1.4V
11 SHDNREF
115 • VH
(IS )ON – (IS )OFF
(0V)
(
(3.3V/5V)
Q1: 2N3904 OR EQUIVALENT
R2 =
1795 F05
Figure 5. Setting Amplifier Supply Current
Level with ON/OFF Control, Version 1
RPULLUP
>500k
RSHDN2
OFF
(0V)
(3.3V/5V)
Q1A
Q1B
OFF
(0V)
(3.3V/5V)
VCC
R2
1795 F06
Q1A, Q1B: ROHM IMX1 or FMG4A (W/INTERNAL RB)
R1
10
SHDN
INTERNAL
LOGIC THRESHOLD
ISY
~ 1.4V
CONTROL
11
SHDNREF
1795 F08
Figure 8. Partial Shutdown
REXT
OFF
(0V)
IPROG
(3.3V/5V)
IPROG ≅ 0.5mA
FOR REXT = 0Ω
(SEE SHDN PIN
CURRENT vs
VOLTAGE
CHARACTERISTIC)
ON
OFF
(0V)
(3.3V/5V)
Figure 6. Setting Multiple Amplifier Supply
Current Levels with ON/OFF Control, Version 2
ON
VSHDN = Shutdown Pin Voltage ≈1.4V
VCC = Positive Supply Voltage
RB2
10k
ON
(IS)ON = Supply Current Fully On
(IS)OFF = Supply Current Partially On
11 SHDNREF
RB1
10k
(VSHDN / VH ) • (IS )ON – (IS )OFF + (IS )OFF
VH = Logic High Level
10 SHDN
ON
)
where
V+
RSHDN1
115 • VCC – VSHDN
SHDN
10
ISY
CONTROL
INTERNAL
LOGIC THRESHOLD
~ 1.4V
SHDNREF
11
1795 F07
Figure 7. Setting Amplifier Supply Current Level
with ON/OFF Control, Version 3
THERMAL CONSIDERATIONS
The LT1795 contains a thermal shutdown feature that
protects against excessive internal (junction) temperature.
If the junction temperature of the device exceeds the
protection threshold, the device will begin cycling between
normal operation and an off state. The cycling is not
harmful to the part. The thermal cycling occurs at a slow
rate, typically 10ms to several seconds, which depends on
the power dissipation and the thermal time constants of the
package and heat sinking. Raising the ambient tempera1795fa
8
LT1795
U
W
U
U
APPLICATIO S I FOR ATIO
ture until the device begins thermal shutdown gives a
good indication of how much margin there is in the
thermal design.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. For the TSSOP package, power is
dissipated through the exposed heatsink. For the SO
package, power is dissipated from the package primarily
through the V – pins (4 to 7 and 14 to 17). These pins
should have a good thermal connection to a copper plane,
either by direct contact or by plated through holes. The
copper plane may be an internal or external layer. The
thermal resistance, junction-to-ambient will depend on
the total copper area connected to the device. For example,
the thermal resistance of the LT1795 connected to a 2 × 2
inch, double sided 2 oz copper plane is 40°C/W.
ing 0.5A current peaks into the load, a 1Ω power supply
impedance will cause a droop of 0.5V, reducing the
available output swing by that amount. Surface mount
tantalum and ceramic capacitors make excellent low ESR
bypass elements when placed close to the chip. For
frequencies above 100kHz, use 1µF and 100nF ceramic
capacitors. If significant power must be delivered below
100kHz, capacitive reactance becomes the limiting factor.
Larger ceramic or tantalum capacitors, such as 4.7µF, are
recommended in place of the 1µF unit mentioned above.
Inadequate bypassing is evidenced by reduced output
swing and “distorted” clipping effects when the output is
driven to the rails. If this is observed, check the supply pins
of the device for ripple directly related to the output
waveform. Significant supply modulation indicates poor
bypassing.
CALCULATING JUNCTION TEMPERATURE
Capacitance on the Inverting Input
The junction temperature can be calculated from the
equation:
Current feedback amplifiers require resistive feedback
from the output to the inverting input for stable operation.
Take care to minimize the stray capacitance between the
output and the inverting input. Capacitance on the inverting input to ground will cause peaking in the frequency
response (and overshoot in the transient response), but it
does not degrade the stability of the amplifier.
TJ = (PD)(θJA) + TA
where
TJ = Junction Temperature
TA = Ambient Temperature
PD = Device Dissipation
θJA = Thermal Resistance (Junction-to-Ambient)
Differential Input Signal Swing
The differential input swing is limited to about ±5V by an
ESD protection device connected between the inputs. In
normal operation, the differential voltage between the
input pins is small, so this clamp has no effect. However,
in the shutdown mode, the differential swing can be the
same as the input swing. The clamp voltage will then set
the maximum allowable input voltage.
Feedback Resistor Selection
The optimum value for the feedback resistors is a function
of the operating conditions of the device, the load impedance and the desired flatness of response. The Typical AC
Performance tables give the values which result in less
than 1dB of peaking for various resistive loads and operating conditions. If this level of flatness is not required, a
higher bandwidth can be obtained by use of a lower
feedback resistor.
For resistive loads, the COMP pin should be left open (see
Capacitive Loads section).
Capacitive Loads
POWER SUPPLY BYPASSING
To obtain the maximum output and the minimum distortion from the LT1795, the power supply rails should be
well bypassed. For example, with the output stage supply-
The LT1795 includes an optional compensation network
for driving capacitive loads. This network eliminates most
of the output stage peaking associated with capacitive
loads, allowing the frequency response to be flattened.
1795fa
9
LT1795
U
U
W
U
APPLICATIONS INFORMATION
Figure 9 shows the effect of the network on a 200pF load.
Without the optional compensation, there is a 6dB peak at
85MHz caused by the effect of the capacitance on the
output stage. Adding a 0.01µF bypass capacitor between
the output and the COMP pins connects the compensation
14
VS = ±15V
CL = 200pF
12
RF = 3.4k
NO
COMPENSATION
VOLTAGE GAIN (dB)
10
RF = 1k
COMPENSATION
8
6
4
2
and greatly reduces the peaking. A lower value feedback
resistor can now be used, resulting in a response which is
flat to ±1dB to 45MHz. The network has the greatest effect
for CL in the range of 0pF to 1000pF.
Although the optional compensation works well with
capacitive loads, it simply reduces the bandwidth when it
is connected with resistive loads. For instance, with a 25Ω
load, the bandwidth drops from 48MHz to 32MHz when
the compensation is connected. Hence, the compensation
was made optional. To disconnect the optional compensation, leave the COMP pin open.
0
–2
–6
DEMO BOARD
RF = 3.4k
COMPENSATION
–4
1
10
FREQUENCY (MHz)
A demo board (DC261A) is available for evaluating the
performence of the LT1795. The board is configured as a
differential line driver/receiver suitable for xDSL applications. For details, consult your local sales representative.
100
1795 F09
Figure 9
U
PACKAGE DESCRIPTIO
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.496 – .512
(12.598 – 13.005)
NOTE 4
N
20
18
17
16
15
14
13
12
11
N
.325 ±.005
.420
MIN
19
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
NOTE:
1. DIMENSIONS IN
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
1
2
3
4
5
6
7
8
.093 – .104
(2.362 – 2.642)
9
10
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
NOTE 3
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.356 – 0.482)
TYP
.004 – .012
(0.102 – 0.305)
S20 (WIDE) 0502
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1795fa
10
LT1795
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
2.74 6.40
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.09 – 0.20
(.0036 – .0079)
0.45 – 0.75
(.018 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
1795fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1795
W
W
SI PLIFIED SCHEMATIC
SHDN
TO ALL
CURRENT
SOURCES
SHDNREF
V+
Q5
Q10
Q2
D1
Q6
Q1
Q11
Q15
Q9
V–
+IN
CC
–IN
V–
50Ω
COMP
RC
OUTPUT
V+
V+
Q12
Q3
Q8
Q16
Q14
D2
Q4
Q7
Q13
V–
1795 SS
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1497
Dual 125mA, 50MHz Current Feedback Amplifier
900V/µs Slew Rate
LT1207
Dual 250mA, 60MHz Current Feedback Amplifier
Shutdown/Current Set Function
LT1886
Dual 200mA, 700MHz Voltage Feedback Amplifier
Low Distortion: –72dBc at 200kHz
1795fa
12 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT/TP 0603 1K REVA • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
工商网监
湘ICP备2023018690号
