LT3023EDD

LT3023 Dual 100mA, Low Dropout, Low Noise, Micropower Regulator FEATURES DESCRIPTION n The LT®3023 is a dual, micropower, low noise, low dropout regulator. With an external 0.01μF bypass capacitor, output noise drops to 20μVRMS over a 10Hz to 100kHz bandwidth. Designed for use in battery-powered systems, the low 20μA quiescent current per channel makes it an ideal choice. In shutdown, quiescent current drops to less than 0.1μA. Shutdown control is independent for each channel, allowing for flexibility in power management. The device is capable of operating over an input voltage from 1.8V to 20V, and can supply 100mA of output current from each channel with a dropout voltage of 300mV. Quiescent current is well controlled in dropout. n n n n n n n n n n n n n Low Noise: 20μVRMS (10Hz to 100kHz) Low Quiescent Current: 20μA/Channel Wide Input Voltage Range: 1.8V to 20V Output Current: 100mA/Channel Very Low Shutdown Current: 3300pF 1.5 1.0 0.5 1 3 2 4 5 6 7 8 9 10 OUTPUT CAPACITANCE (μF) 3023 F02 Figure 2. Stability 4 14 8 6 10 12 DC BIAS VOLTAGE (V) 16 X5R 0 –20 –40 Y5V –60 –80 0 2 Figure 3. Ceramic Capacitor DC Bias Characteristics 3.5 STABLE REGION 0 3023 F03 40 2.5 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 0 4.0 3.0 ESR (Ω) and temperature coefficients as shown in Figures 3 and 4. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component CHANGE IN VALUE (%) Output Capacitance and Transient Response BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF –100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3023 F04 Figure 4. Ceramic Capacitor Temperature Characteristics 3023fa 10 LT3023 APPLICATIONS INFORMATION case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 5’s trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as COUT = 10μF CBYP = 0.01μF ILOAD = 100mA Characteristics section. Power dissipation will be equal to the sum of the two components listed above. Power dissipation from both channels must be considered during thermal analysis. The LT3023 regulator has internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions, the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. VOUT 500μV/DIV Table 1. MSE Package, 10-Lead MSOP COPPER AREA 100ms/DIV 3023 F05 Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor increased output voltage noise. Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125°C). The power dissipated by the device will be made up of two components (for each channel): THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) TOPSIDE* BACKSIDE 2500mm2 2500mm2 2500mm2 40°C/W 1000mm2 2500mm2 2500mm2 45°C/W 225mm2 2500mm2 2500mm2 50°C/W 100mm2 2500mm2 2500mm2 62°C/W *Device is mounted on topside. Table 2. DD Package, 10-Lead DFN COPPER AREA TOPSIDE* BACKSIDE THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 40°C/W 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN – VOUT), and 1000mm2 2500mm2 2500mm2 45°C/W 225mm2 2500mm2 2500mm2 50°C/W 2. GND pin current multiplied by the input voltage: (IGND)(VIN). 100mm2 2500mm2 2500mm2 62°C/W *Device is mounted on topside. The ground pin current can be found by examining the GND Pin Current curves in the Typical Performance The thermal resistance juncton-to-case (θJC), measured at the Exposed Pad on the back of the die is 10°C/W. 3023fa 11 LT3023 APPLICATIONS INFORMATION Calculating Junction Temperature Example: Given an output voltage on the first channel of 3.3V, an output voltage of 2.5V on the second channel, an input voltage range of 4V to 6V, output current ranges of 0mA to 100mA for the first channel and 0mA to 50mA for the second channel, with a maximum ambient temperature of 50°C, what will the maximum junction temperature be? The power dissipated by each channel of the device will be equal to: IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX)) where (for the first channel): IOUT(MAX) = 100mA VIN(MAX) = 6V IGND at (IOUT = 100mA, VIN = 6V) = 2mA so: P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W and (for the second channel): IOUT(MAX) = 50mA VIN(MAX) = 6V IGND at (IOUT = 50mA, VIN = 6V) = 1mA so: P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W The thermal resistance will be in the range of 40°C/W to 60°C/W depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: (0.28W + 018W)(60°C/W) = 27.8°C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50°C + 27.8°C = 77.8°C Protection Features The LT3023 regulator incorporates several protection features which makes it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages, reverse output voltages and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C. The input of the device will withstand reverse voltages of 20V. Current flow into the device will be limited to less than 1mA (typically less than 100μA) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries which can be plugged in backward. The output of the LT3023 can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20V. The output will act like an open circuit; no current will flow out of the pin. If the input is powered by a voltage source, the output will source the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN1/SHDN2 pins will turn off the device and stop the output from sourcing the shortcircuit current. The ADJ1 and ADJ2 pins can be pulled above or below ground by as much as 7V without damaging the device. If the input is left open circuit or grounded, the ADJ1 and ADJ2 pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. In situations where the ADJ1 and ADJ2 pins are connected to a resistor divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ1/ADJ2 pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ1/ADJ2 pin is at 7V. The 13V difference between output and ADJ1/ADJ2 pin divided by the 5mA maximum current into the ADJ1/ADJ2 pin yields a minimum top resistor value of 2.6k. 3023fa 12 LT3023 APPLICATIONS INFORMATION In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. Current flow back into the output will follow the curve shown in Figure 6. REVERSE OUTPUT CURRENT (μA) 100 When the IN pin of the LT3023 is forced below the OUT1 or OUT2 pins or the OUT1/OUT2 pins are pulled above the IN pin, input current will typically drop to less than 2μA. This can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN1/SHDN2 pins will have no effect on the reverse output current when the output is pulled above the input. TA = 25°C 90 VIN = 0V = VADJ V 80 OUT CURRENT FLOWS 760 INTO OUTPUT PIN 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 OUTPUT VOLTAGE (V) 9 10 3023 F06 Figure 6. Reverse Output Current TYPICAL APPLICATIONS Noise Bypassing Slows Startup, Allows Outputs to Track VSHDN1/SHDN2 1V/DIV VIN 3.7V TO 20V VOUT1 1V/DIV VOUT2 1V/DIV OUT1 IN 0.01μF 1μF 10μF 3.3V AT 100mA 422k BYP1 3023 TA02b 2ms/DIV ADJ1 249k LT3023 SHDN1 OUT2 0.01μF SHDN2 BYP2 GND 10μF 2.5V AT 100mA 100 261k ADJ2 249k 3023 TA02a STARTUP TIME (ms) OFF ON Startup Time 10 1 0.1 10 100 1000 10000 CBYP (pF) 3023 TA02c 3023fa 13 LT3023 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.38 ± 0.10 10 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN 1103 5 0.25 ± 0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) 1 0.75 ±0.05 0.00 – 0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3023fa 14 LT3023 PACKAGE DESCRIPTION MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev B) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 ± 0.102 (.110 ± .004) 5.23 (.206) MIN 0.889 ± 0.127 (.035 ± .005) 1 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136) 10 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0.254 (.010) DETAIL “A” 0° – 6° TYP 1 2 3 4 5 GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) 0.497 ± 0.076 (.0196 ± .003) REF SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) MSOP (MSE) 0307 REV B NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3023fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT3023 TYPICAL APPLICATION Startup Sequencing Turn-On Waveforms VIN 3.7V TO 20V VSHDN1 1V/DIV 10μF 0.01μF LT3023 1μF 3.3V AT 100mA OUT1 IN BYP1 422k 35.7k 249k 28k VOUT1 1V/DIV VOUT2 1V/DIV ADJ1 OFF ON SHDN1 OUT2 SHDN2 BYP2 10μF 0.01μF GND 0.47μF 2.5V AT 100mA 2ms/DIV 3023 TA03b Turn-Off Waveforms 261k ADJ2 249k VSHDN1 1V/DIV 3023 TA03a VOUT1 1V/DIV VOUT2 1V/DIV 2ms/DIV 3023 TA03c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1129 700mA, Micropower, LDO VIN: 4.2V to 30V, VOUT(MIN) = 3.75V, IQ = 50μA, ISD = 16μA, DD, SOT-223, S8,TO220, TSSOP20 Packages LT1175 500mA, Micropower Negative LDO Guaranteed Voltage Tolerance and Line/Load Regulation, VIN: –20V to –4.3V, VOUT(MIN) = –3.8V, IQ = 45μA, ISD = 10μA, DD,SOT-223, S8 Packages LT1185 3A, Negative LDO Accurate Programmable Current Limit, Remote Sense, VIN: –35V to –4.2V, VOUT(MIN) = –2.40V, IQ = 2.5mA, ISD