LT3024
Dual 100mA/500mA
Low Dropout, Low Noise,
Micropower Regulator
FEATURES
DESCRIPTION
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The LT®3024 is a dual, micropower, low noise, low dropout
regulator. With an external 0.01μF bypass capacitor, output
noise drops to 20μVRMS over a 10Hz to 100kHz bandwidth.
Designed for use in battery-powered systems, the low 30μA
quiescent current per output makes it an ideal choice. In
shutdown, quiescent current drops to less than 0.1μA.
Shutdown control is independent for each output, allowing
for flexibility in power management. The device is capable
of operating over an input voltage range of 1.8V to 20V. The
device can supply 100mA of output current from Output
2 with a dropout voltage of 300mV. Output 1 can supply
500mA of output current with a dropout voltage of 300mV.
Quiescent current is well controlled in dropout.
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Low Noise: 20μVRMS (10Hz to 100kHz)
Low Quiescent Current: 30μA/Output
Wide Input Voltage Range: 1.8V to 20V
Output Current: 100mA/500mA
Very Low Shutdown Current: 3300pF
1.5
1.0
0.5
2.0
CBYP = 0
CBYP = 100pF
1.5
CBYP = 330pF
CBYP ≥ 1000pF
1.0
0.5
0
0
1
3
2
4 5 6 7 8 9 10
OUTPUT CAPACITANCE (μF)
1
3
2
4 5 6 7 8 9 10
OUTPUT CAPACITANCE (μF)
3024 F02
Figure 2. Output 2 Stability
3024 F03
Figure 3. Output 1 Stability
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14
LT3024
APPLICATIONS INFORMATION
20
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
20
X5R
CHANGE IN VALUE (%)
CHANGE IN VALUE (%)
0
–20
–40
–60
Y5V
–80
–100
X5R
0
–20
–40
Y5V
–60
–80
0
2
4
8
6
10 12
DC BIAS VOLTAGE (V)
14
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
50
25
75
–50 –25
0
TEMPERATURE (°C)
3024 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress can
be induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 6’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
COUT = 10μF
CBYP = 0.01μF
ILOAD = 100mA
100
125
3024 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components for each output:
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation will be equal to the
sum of the two components listed above.
The LT3024 regulator has internal thermal limiting designed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
VOUT
500μV/DIV
100ms/DIV
3024 F06
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
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15
LT3024
APPLICATIONS INFORMATION
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat generated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
TOPSIDE*
BACKSIDE
2500mm2
2500mm2
2500mm2
38°C/W
1000mm2
2500mm2
2500mm2
43°C/W
225mm2
2500mm2
2500mm2
48°C/W
100mm2
2500mm2
2500mm2
60°C/W
*Device is mounted on topside.
Where for Output 1:
IOUT(MAX) = 500mA
VIN(MAX) = 5V
IGND at (IOUT = 500mA, VIN = 5V) = 9mA
IOUT(MAX) = 100mA
VIN(MAX) = 5V
IGND at (IOUT = 100mA, VIN = 5V) = 2mA
So for Output 1:
P = 500mA (5V – 3.3V) + 9mA (5V) = 0.90W
For Output 2:
P = 100mA (5V – 2.5V) + 2mA (5V) = 0.26W
Table 2. UE Package, 12-Lead DFN
COPPER AREA
IOUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX))
For Output 2:
Table 1. FE Package, 16-Lead TSSOP
COPPER AREA
The power dissipated by each output will be equal to:
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
TOPSIDE*
BACKSIDE
2500mm2
2500mm2
2500mm2
40°C/W
1000mm2
2500mm2
2500mm2
45°C/W
225mm2
2500mm2
2500mm2
50°C/W
100mm2
2500mm2
2500mm2
62°C/W
*Device is mounted on topside.
The thermal resistance junction-to-case (θJC), measured
at the Exposed Pad on the back of the die is 10°C/W for
the DFN package and 8°C/W for the TSSOP package.
The thermal resistance will be in the range of 35°C/W to
55°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
(0.90W + 0.26W) 50°C/W = 57.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 57.8°C = 107.8°C
Calculating Junction Temperature
Protection Features
Example: Given Output 1 set for an output voltage of
3.3V, Output 2 set for an output voltage of 2.5V, an input
voltage range of 3.8V to 5V, an output current range of
0mA to 500mA for Output 1, an output current range of
0mA to 100mA for Output 2 and a maximum ambient
temperature of 50°C, what will the maximum junction
temperature be?
The LT3024 regulator incorporates several protection features which make it ideal for use in battery-powered circuits.
In addition to the normal protection features associated
with monolithic regulators, such as current limiting and
thermal limiting, the device is protected against reverse
input voltages, reverse output voltages and reverse voltages
from output to input. The two regulators have common
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LT3024
APPLICATIONS INFORMATION
Current limit protection and thermal overload protection
are intended to protect the device against current overload
conditions at the output of the device. For normal operation,
the junction temperature should not exceed 125°C.
The input of the device will withstand reverse voltages
of 20V. Current flow into the device will be limited to less
than 1mA (typically less than 100μA) and no negative
voltage will appear at the output. The device will protect
both itself and the load. This provides protection against
batteries which can be plugged in backward.
The output of the LT3024 can be pulled below ground
without damaging the device. If the input is left open circuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In
this case, grounding the SHDN1/SHDN2 pins will turn off
the device and stop the output from sourcing the shortcircuit current.
The ADJ pins can be pulled above or below ground by as
much as 7V without damaging the device. If the input is
left open circuit or grounded, the ADJ pins will act like an
open circuit when pulled below ground and like a large
resistor (typically 100k) in series with a diode when pulled
above ground.
In situations where the ADJ pins are connected to a resistor
divider that would pull the pins above their 7V clamp voltage if the output is pulled high, the ADJ pin input current
must be limited to less than 5mA. For example, a resistor
divider is used to provide a regulated 1.5V output from the
1.22V reference when the output is forced to 20V. The top
resistor of the resistor divider must be chosen to limit the
current into the ADJ pin to less than 5mA when the ADJ
pin is at 7V. The 13V difference between output and ADJ
pin divided by the 5mA maximum current into the ADJ pin
yields a minimum top resistor value of 2.6k.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage or is left
open circuit. Current flow back into the output will follow
the curve shown in Figure 7.
When the IN pin of the LT3024 is forced below either OUT
pin or either OUT pin is pulled above the IN pin, input current for the corresponding regulator will typically drop to
less than 2μA. This can happen if the input of the device
is connected to a discharged (low voltage) battery and the
output is held up by either a backup battery or a second
regulator circuit. The state of the SHDN1/SHDN2 pin will
have no effect on the reverse output current when the
output is pulled above the input.
100
REVERSE OUTPUT CURRENT (μA)
VIN and GND pins and are thermally coupled, however, the
two outputs of the LT3024 operate independently. They
can be shut down independently and a fault condition on
one output will not affect the other output electrically.
TA = 25°C
90 VIN = 0V
= VADJ
V
80 OUT
CURRENT FLOWS
70 INTO OUTPUT PIN
60
50
40
30
20
10
0
0
1
2
3 4 5 6 7 8
OUTPUT VOLTAGE (V)
9
10
3024 F07
Figure 7. Reverse Output Current
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LT3024
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 ±0.05
3.60 ±0.05
2.20 ±0.05
3.30 ±0.05
1.70 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
7
R = 0.115
TYP
0.40 ± 0.10
12
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 ±0.10
(2 SIDES)
0.75 ±0.05
3.30 ±0.10
1.70 ± 0.10
6
0.25 ± 0.05
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
1
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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LT3024
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
6.60 ±0.10
9
2.94
(.116)
4.50 ±0.10
2.94 6.40
(.116) (.252)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3024
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