LT3473/LT3473A
Micropower 1A Boost
Converter with Schottky
and Output Disconnect
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FEATURES
DESCRIPTIO
■
The LT®3473/LT3473A are micropower step-up DC/DC
converters with integrated Schottky diode and output
disconnect circuitry in low profile DFN packages. The
small package size, high level of integration and the use of
tiny SMT components yield a solution size of less than
50mm2. The internal 1A switch allows the device to deliver
25V at up to 80mA from a Li-Ion cell, while automatic Burst
Mode operation maintains efficiency at light load. An
auxiliary reference input (CTRL) allows the user to override the internal 1.25V feedback reference with any lower
value, allowing full control of the output voltage during
operation. A PGOOD pin sinks current when the output
voltage reaches 90% of final value.
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■
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APPLICATIO S
■
The rugged 36V switch and output disconnect circuitry
allow outputs up to 34V to be easily generated in a simple
boost topology.
OLED Bias
CCD Bias
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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■
The LT3473A includes two NPN transistors for generating
intermediate bias voltages from the output and is offered
in a 12-lead (4mm × 3mm) DFN package. The LT3473
does not include these NPNs and is offered in an 8-lead
(3mm × 3mm) package.
TYPICAL APPLICATIO
Conversion Efficiency and Power Loss vs Output Current
80
PGOOD
CTRL
VIN
3V TO 4.2V
6.8µH
LT3473
SW
CAP
VIN
2M
GND
75
400
70
300
65
200
60
100
0.47µF
FB
SHDN
4.7µF
500
VIN = 3.6V
VOUT = 15V
POWER LOSS (mW)
VOUT
25V
2.2µF 80mA
OUT
EFFICIENCY (%)
■
Tiny Solution Size
Low Quiescent Current:
150µA in Active Mode (VIN = 3.6V, VOUT = 15V,
No Load)
1µA in Shutdown Mode
Internal 1A, 36V Switch
Integrated Schottky Diode
Integrated PNP Output Disconnect
Internal Reference Override Pin
PGOOD Pin
25V at 80mA from 3.6V Input
Auxiliary NPNs for Intermediate
Bias Voltages (LT3473A)
Automatic Burst Mode® Operation at Light Load
Constant Switching Frequency: 1.2MHz
Thermal Shutdown
Input Range: 2.2V to 16V
Low Profile (3mm × 3mm) DFN Package (LT3473)
Low Profile (4mm × 3mm) DFN Package (LT3473A)
100k
3473 TA01a
55
0.1
10
1
OUTPUT CURRENT (mA)
0
100
3473 TA01b
3473f
1
LT3473/LT3473A
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AXI U
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ABSOLUTE
RATI GS (Note 1)
VIN Voltage ............................................................. 16V
SHDN Voltage .......................................................... 16V
SW Voltage ............................................................. 36V
PGOOD Voltage ...................................................... 36V
CAP Voltage ............................................................ 36V
OUT Voltage ........................................................... 36V
FB Voltage .............................................................. 10V
CTRL Voltage .......................................................... 10V
NB1, NB2 Voltage ................................................... 36V
NE1, NE2 Voltage ................................................... 36V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 125°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
ORDER PART
NUMBER
TOP VIEW
CAP
1
12 SW
CAP 1
8
SW
OUT
2
11 VIN
OUT 2
7
VIN
NB1
3
10 SHDN
6
SHDN
NE1
4
9
PGOOD
5
PGOOD
NB2
5
8
CTRL
NE2
6
7
FB
CTRL 3
9
FB 4
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/ W
EXPOSED PAD (PIN 9) IS GND
MUST BE SOLDERED TO PCB (NOTE 3)
LT3473EDD
DD PART MARKING
LBJJ
13
LT3473AEDE
DE PART MARKING
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
3473A
TJMAX = 125°C, θJA = 43°C/ W
EXPOSED PAD (PIN 13) IS GND
MUST BE SOLDERED TO PCB (NOTE 3)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3V, SHDN = 3V, CTRL = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
Minimum Operation Voltage
TYP
SHDN = 3V, Not Switching
SHDN = 0V
100
0.1
SHDN Voltage to Enable Chip
●
SHDN Voltage to Disable Chip
●
16
V
1
µA
µA
1.4
V
0.2
SHDN Pin Bias Current
2
●
FB Voltage
1.235
UNITS
V
Maximum Operation Voltage
Supply Current
MAX
2.2
1.25
V
µA
1.26
V
FB Voltage Line Regulation
3V < VIN < 16V
FB Pin Bias Current
FB = 1.27V
CTRL to FB Offset
CTRL = 0.5V
5
CTRL Pin Bias Current
CTRL = 1V
50
nA
FB Threshold for PGOOD
CTRL = 2V
CTRL = 0.5V
1.15
0.40
V
V
PGOOD Current Capacity
●
100
0.01
%/V
20
nA
20
mV
µA
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LT3473/LT3473A
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3V, SHDN = 3V, CTRL = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
Switching Frequency
MIN
TYP
MAX
UNITS
0.9
1.2
1.4
MHz
92
Maximum Duty Cycle
●
88
Switch Current Limit
●
1.2
%
A
Switch VCESAT
ISW = 100mA
45
Switch Leakage Current
VSW = 5V
0.1
Schottky Forward Drop
ID = 100mA
0.45
Schottky Leakage Current
CAP = 36V, SW = 0V
Disconnect PNP Voltage Drop
IOUT = 100µA, CAP = 20V
IOUT = 50mA, CAP = 20V
mV
5
µA
4
µA
V
80
250
Disconnect PNP Quiescent Current
CAP = 20V
1.2
Disconnect PNP Leakage Current
SHDN = OUT = 0V, CAP = 20V
0.01
mV
mV
µA
0.1
µA
LTC3473A Only
NPN1 Voltage Drop
INE1 = 1mA
NPN1 Beta
INE1 = 1mA
NPN2 Voltage Drop
INE2 = 1mA
NPN2 Beta
INE2 = 1mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3473EDD and LT3473AEDE are guaranteed to meet
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
FEEDBACK VOLTAGE (V)
VOLTAGE (V)
CAP
19.80
OUT
19.60
19.40
19.20
PGOOD Threshold Voltage
1.4
1.4
1.2
1.2
PGOOD THRESHOLD VOLTAGE (V)
20.00
1.0
0.8
0.6
0.4
0.2
19.00
0
20
40
60
80
LOAD CURRENT (mA)
100
3473 G01
V
TA = 25°C unless otherwise noted.
Feedback Voltage
VIN = 3.6V
0.8
Note 3: Failure to correctly solder the Exposed Pad of the package to the
PC board will result in a thermal resistance much higher than 40°C.
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20.20
V
60
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation (Feedback Taken
from CAP)
0.8
60
1.0
0.8
0.6
0.4
0.2
0
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
CTRL VOLTAGE (V)
2
3473 G02
0
0.5
1
1.5
2
CTRL VOLTAGE (V)
3473 G03
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LT3473/LT3473A
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TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Sleep Mode Quiescent Current
(Not Switching)
Sleep Mode Quiescent Current
100
95
2.5
SHDN = 3V
VIN = 3V
100
SHDN = 3V
98
96
94
92
SHDN = 1.5V
0
50
TEMPERATURE (°C)
4
6
8
10
12
INPUT VOLTAGE, VIN (V)
2
0
100
350
300
250
200
150
100
50
400
600
800 1000
SWITCH CURRENT (mA)
Schottky I-V Characteristic
ISW = 100mA
48
47
46
45
44
43
0
50
900
800
700
600
500
400
300
200
100
0
100
0
TEMPERATURE (°C)
1.4
90°C
350
25°C
500
VOLTAGE DROP (mV)
Switching Frequency
300
SWITCHING FREQUENCY (MHz)
ID = 100mA
–45°C
250
200
150
100
350
0
3473 G10
1.2
1.0
0.8
0.6
0.4
0.2
50
100
1000
3473 G09
Output Disconnect Voltage Drop
400
400
200
600
800
400
SCHOTTKY FORWARD DROP (mV)
3473 G08
3473 G07
Schottky Forward Voltage
100
1000
49
42
–50
1200
450
50
0
TEMPERATURE (°C)
3473 G06
SCHOTTKY FORWARD CURRENT (mA)
SWITCH SATURATION VOLTAGE (mV)
SWITCH SATURATION VOLTAGE (mV)
50
400
0
SCHOTTKY FORWARD VOLTAGE (mV)
0
–50
16
Switch Saturation Voltage
Switch VCE(SAT)
50
0
TEMPERATURE (°C)
1.0
3473 G5
450
300
–50
1.5
0.5
14
3473 G04
200
2.0
90
88
90
–50
0
SHDN PIN CURRENT (µA)
SHDN = 3V
VIN = 3V
550
SHDN Pin Current
102
SLEEP MODE QUIESCENT CURRENT (µA)
SLEEP MODE QUIESCENT CURRENT (µA)
105
0
20
40
60
80
COLLECTOR CURRENT (mA)
100
0
0
5
10
15
INPUT VOLTAGE, VIN (V)
3473 G11
3473 G12
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LT3473/LT3473A
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TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
SHDN Voltage to Turn-On
Disconnect PNP
Auxiliary NPN VBE
0.9
1.2
1.0
0.8
0.6
0.4
1.00
0.8
0.95
0.7
0.90
0.6
0.85
NPN VBE (V)
1.4
SHDN VOLTAGE (V)
DISCONNECT PNP QUIESCENT CURRENT (µA)
Disconnect PNP Quiescent Current
0.80
0.5
0.75
0.4
0.70
0.3
0.65
0.2
0.2
0.60
0.1
0
5
10
15
20
25
30
35
40
CAP VOLTAGE (V)
IE = 100µA
0.55
0
0
IE = 1mA
0
80
20
60
40
OUTPUT CURRENT (mA)
3473 G13
100
0.50
–50
3473 G14
50
0
TEMPERATURE (°C)
100
3473 G15
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PI FU CTIO S (LT3473/LT3473A)
CAP (Pin 1/Pin 1): Internal Output Voltage. This pin is the
Schottky cathode and disconnect PNP emitter. Connect
output capacitor here.
SHDN (Pin 6/Pin 10): Shutdown Pin. Connect to 1.4V or
higher to enable device; 0.2V or less to disable device. Also
functions as soft-start. Use RC filter as shown in Figure 4.
OUT (Pin 2/Pin 2): Output of Disconnect Circuit. Bypass
this pin with capacitor to ground.
VIN (Pin 7/Pin 11): Input Supply Pin. Must be locally
bypassed with a X5R or X7R type ceramic capacitor.
CTRL (Pin 3/Pin 8): External Reference Pin. This pin sets
the FB voltage externally between 0V and 1.25V. Tie this
pin 1.5V or higher to use the internal 1.25V reference.
SW (Pin 8/Pin 12): Switch Pin. Connect inductor here.
Minimize the metal trace area connected to the pin to
minimize EMI.
FB (Pin 4/Pin 7): Feedback Pin. Pin voltage is regulated to
1.25V if internal reference is used or to the CTRL pin
voltage if the CTRL pin voltage is between 0V and 1.25V.
Connect the feedback resistor divider to this pin. The
output voltage is regulated to:
Exposed Pad (Pin 9/Pin 13): Ground. Solder directly to
PCB ground plane through multiple vias under the package for optimum thermal performance.
LT3473A Only
NB1 (Pin 3): NPN1 Base.
⎛ R2 ⎞
VOUT = VREF • ⎜ + 1⎟
⎝ R1 ⎠
PGOOD (Pin 5/Pin 9): Power Good Output. Open collector
logic output that starts to sink current when FB reaches
within 100mV of the reference voltage.
NE1 (Pin 4): NPN1 Emitter.
NB2 (Pin 5): NPN2 Base.
NE2 (Pin 6): NPN2 Emitter.
3473f
5
LT3473/LT3473A
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BLOCK DIAGRA
4
3
–
+
+
FB
CTRL
ERROR
AMPLIFIER
7
6
VIN
SHDN
VC
gm
VREF
1.25V
CAP
+
1
Q2
ENABLE
OUT
PNP
DRIVER
–
2
POWER SECTION
+
+ – –
A4
5
SW
A1
BTH
100mV
8
–
PGOOD
+
R
A2
S
Q
Q1
DRIVER
Q5
–
GND
Σ
A3
RAMP
GENERATOR
+
9
COMPARATOR
1.2MHz
OSCILLATOR
3437 F01
Figure 1. LT3473 Block Diagram
7
8
–
+
+
FB
CTRL
ERROR
AMPLIFIER
11
10
VIN
SHDN
VC
gm
+
VREF
1.25V
OUT
PNP
DRIVER
–
2
POWER SECTION
Q3
+
A4
–
PGOOD
+
Q5
R
A2
S
Q
Q1
COMPARATOR
–
Σ
Q4
NB2
NE2
GND
3
4
5
6
A3
1.2MHz
OSCILLATOR
+
RAMP
GENERATOR
NB1
NE1
DRIVER
13
1
Q2
ENABLE
A1
+ – –
9
SW
CAP
BTH
100mV
12
3437 F02
Figure 2. LT3473A Block Diagram
3473f
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LT3473/LT3473A
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APPLICATIO S I FOR ATIO
Operation
The LT3473 combines a current mode, fixed frequency
PWM architecture with Burst Mode micropower operation
to maintain high efficiency at light loads. Operation can
best be understood by referring to the Block Diagram.
The reference of the part is determined by the lower of the
internal 1.25V bandgap reference and the voltage at the
CTRL pin. The error amplifier compares voltage at the FB
pin with the reference and generates an error signal VC.
When VC is below the Burst Mode threshold voltage, BTH,
the hysteretic comparator, A1, shuts off the power section
leaving only the low power circuitry running. Total current
consumption in this state is minimized. As output loading
Switching Waveforms
causes the FB voltage to decrease, VC increases causing A1
to enable the power section circuitry. The chip starts switching. If the load is light, the output voltage (and FB voltage)
will increase until A1 turns off the power section. The output
voltage starts to fall again. This cycle repeats and generates low frequency ripple at the output. This Burst Mode
operation keeps the output regulated and reduces average
current into the IC, resulting in high efficiency at light load.
If the output load increases sufficiently, A1’s output remains
high, resulting in continuous operation.
At the start of each oscillator cycle, the SR latch is set,
turning on the power switch Q1. A voltage proportional to
the switch current is added to a stabilizing ramp and the
Switching Waveforms
Transient Response
VOUT
200mV/DIV
IL
200mA/DIV
IL
200mA/DIV
IL
200mA/DIV
VSW
10V/DIV
VSW
10V/DIV
VIN = 3.6V
VOUT = 20V
ILOAD = 50mA
0.5µs/DIV
3473 AI01
ILOAD
VIN = 3.6V
VOUT = 20V
ILOAD = 8mA
Transient Response
VOUT
500mV/DIV
IL
500mA/DIV
IL
500mA/DIV
51mA
ILOAD
1mA
VIN = 3.6V
VOUT = 20V
500µs/DIV
1mA
3473 AI02
0.5µs/DIV
VIN = 3.6V
VOUT = 20V
Transient Response
VOUT
500mV/DIV
ILOAD
11mA
3473 AI03
Transient Response
VOUT
500mV/DIV
IL
500mA/DIV
55mA
ILOAD
5mA
3473 AI04
500µs/DIV
VIN = 3.6V
VOUT = 20V
500µs/DIV
Shutdown Waveforms
3473 AI05
75mA
25mA
VIN = 3.6V
VOUT = 20V
200µs/DIV
3473 AI06
Start-Up Waveforms
VOUT
10V/DIV
VOUT
10V/DIV
CAP
0.5V/DIV
IL
500mA/DIV
SHDN
5V/DIV
SHDN
2V/DIV
VIN = 3.6V
VOUT = 20V
ILOAD = 60mA
100µs/DIV
3473 AI07
500µs/DIV
VIN = 3.6V
VOUT = 20V
ILOAD = 30mA
SHDN 20k, 100nF
3473 AI08
3473f
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LT3473/LT3473A
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APPLICATIO S I FOR ATIO
The LT3473 includes an internal power Schottky diode and
a PNP transistor, Q2, for output disconnect. Q2 disconnects the load from the input during shutdown. The part
also has a power good indication pin, PGOOD. When the
FB voltage reaches within 100mV of the reference voltage,
the comparator A4 turns on Q5, sinking current from
PGOOD pin.
The LT3473 has thermal shutdown feature with threshold
at about 145°C.
Inductor Selection
A 6.8µH inductor is recommended for the LT3473. The
minimum inductor size that may be used in a given application depends on required efficiency and output current.
Inductors with low core losses and small DCR (copper
wire resistance) at 1.2MHz are good choices for LT3473
applications. Some inductors in this category with small
size are listed in Table 1. The efficiency comparison of
different inductors is shown in Figure 3.
80
VIN = 3.6V
VOUT = 20V
75
EFFICIENCY (%)
resulting sum is fed into the positive terminal of the PWM
comparator A2. When this voltage exceeds the level of the
error signal VC, the SR latch is reset, turning off the power
switch Q1. The error amplifier sets the peak current level
to keep the output in regulation. If the error amplifier’s
output increases, more current is delivered to the output;
if it decreases, less current is delivered.
70
65
TOKO A915AY-6R8M
SUMIDA CDRH4D28-6R8
SUMIDA CDRH5D18-6R2
COILCRAFT ME3220-682
COILCRAFT MSS5131-682
60
55
0
20
60
80
40
LEAD CURRENT lO (mA)
100
3473 F03
Figure 3. Efficiency Comparison of Different Inductors
Capacitor Selection
The small package of ceramic capacitors makes them
suitable for LT3473 applications. X5R and X7R types of
ceramic capacitors are recommended because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. A 4.7µF input
capacitor, a 0.47µF output capacitor and a 2.2µF capacitor
bypassing output disconnect PNP are sufficient for most
LT3473 applications.
Table 2. Recommended Ceramic Capacitor Manufacturers
MANUFACTURER
Taiyo Yuden
AVX
Murata
Kemet
TELEPHONE
408-573-4150
843-448-9411
814-237-1431
408-986-0424
URL
www.t-yuden.com
www.avxcorp.com
www.murata.com
www.kemet.com
Table 1. Recommended Inductors
DCR
(mΩ)
CURRENT
RATING (A)
DIMENSION
(mm)
DO1605T-682
ME3220-682
MSS6122-682
MSS5131-682
200
270
100
60
1.1
1.0
1.45
1.05
5.4 × 4.2 × 1.8
3.2 × 2.5 × 2.0
6.1 × 6.1 × 2.2
5.1 × 5.1 × 3.1
Coilcraft
800-322-2645
www.coilcraft.com
LQH55DN6R8
74
2.0
5.7 × 5.0 × 4.7
Murata
814-237-1431
www.murata.com
CDRH5D18-6R2
CDRH4D28-6R8
CDRH5D28-6R2
CRD53-4R7
71
81
33
74
1.4
1.12
1.8
1.68
5.7 × 5.7 × 2.0
4.7 × 4.7 × 3.0
5.7 × 5.7 × 3.0
6.0 × 5.2 × 3.2
Sumida
847-956-0666
www.sumida.com
A918CY-6R2M
(TYPE D62LCB)
A915AY-6R8M
(TYPE D53LC)
62
1.49
6.0 × 6.0 × 2.0
68
1.51
5.0 × 5.0 × 3.0
Toko
408-432-8281
www.tokoam.com
PART
MANUFACTURER
3473f
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LT3473/LT3473A
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APPLICATIO S I FOR ATIO
Inrush Current
Setting the Output Voltages
The LT3473 has an integrated Schottky power diode.
When supply voltage is abruptly applied to the VIN pin
while the output capacitor is discharged, the voltage
difference between VIN and CAP generates inrush current
flowing from the input through the inductor and the
internal Schottky diode to charge the output capacitor at
the CAP pin. The maximum current the LT3473’s Schottky
can sustain is 2A. The selection of inductor and capacitor
values should ensure that the peak inrush current is less
than 2A. Peak inrush current can be calculated as follows:
The LT3473 has both an internal 1.25V reference and an
external reference input. This allows the user to select
between using the built-in reference and supplying an
external reference voltage. The voltage at the CTRL pin can
be adjusted while the device is operating to alter the output
voltage for purposes such as display dimming or contrast
adjustment. To use the internal 1.25V reference, the CTRL
pin must be held higher than 1.5V. When the CTRL pin is
held between 0V and 1.2V, the LT3473 will regulate the
output such that the FB pin voltage is equal to the CTRL pin
voltage.
IP =
⎛
⎛ α
VIN – 0.6
⎛ ω ⎞⎞
⎛ ω ⎞⎞
• exp ⎜ – • arctan ⎜ ⎟⎟ • sin ⎜ arctan ⎜ ⎟⎟
⎝ α ⎠⎠
⎝ α ⎠⎠
L•ω
⎝
⎝ ω
α=
r + 1.5
2•L
⎛ R2 ⎞
VINT = VREF • ⎜ 1 + ⎟
⎝ R1⎠
1
r
–
L • C 4 • L2
ω=
where L is the inductance, r is the resistance of the
inductor and C is the output capacitance. For a low DCR
inductor, which is usually the case for this application, the
peak inrush current can be simplified as follows:
IP =
The CAP pin should be used as the feedback node. To set
the output voltage, select the values of R1 and R2 according to the following equation.
VIN – 0.6
⎛ α π⎞
• exp⎜ – • ⎟
⎝ ω 2⎠
L•ω
A large abrupt voltage step at VIN and/or a large capacitor
at the CAP pin generate larger inrush current. Table 3 gives
inrush peak currents for some component selections. An
inductor with low saturation current could generate very
large inrush current. For this case, inrush current should
be measured to ensure safe operation. Note that inrush
current is not a concern if the input voltage rises slowly.
Table 3. Inrush Peak Current
VIN (V)
R (Ω)
L (µH)
C (µF)
IP (A)
5
0.05
6.8
0.47
0.86
10
0.05
6.8
0.47
1.83
3.6
0.05
6.8
0.47
0.58
3.6
0.05
4.7
0.47
0.67
where VREF = 1.25V if the internal reference is used, or
VREF = VCTRL if VCTRL is between 0V and 1.2V.
To maintain output voltage accuracy, 1% resistors are
recommended.
Soft-Start
The SHDN pin also functions as soft-start. Use an RC filter
at the SHDN pin to limit the start-up current. The small bias
current of the SHDN pin allows using a small capacitor for
a large RC time constant.
LT3473
20k
ON/OFF
SHDN
100nF
3473 F04
Figure 4. Soft-Start Circuitry
Output Disconnect Considerations
The LT3473 has an output disconnect PNP that isolates
the load from the input during shutdown. The drive circuit
maintains the PNP at the edge of saturation, adaptively
according to the load, thus yielding the best compromise
between VCESAT and quiescent current to minimize power
loss. To remain stable, it requires a bypass capacitor
connected between the OUT pin and the CAP pin or
3473f
9
LT3473/LT3473A
U
W
U U
APPLICATIO S I FOR ATIO
between the OUT pin and ground. A ceramic capacitor with
a value of 1µF is a good choice. The voltage drop (PNP
VCESAT) can be accounted for by setting the output voltage
according to the following formula:
⎛ R2 ⎞
VOUT = VINT – VCESAT = VREF • ⎜ 1 + ⎟ – VCESAT
⎝ R1⎠
connected to the two bases as shown in Figure 5 to
generate buffered voltage at the emitters. When sourcing
high current at low voltage, keep in mind that the NPNs
will be dissipating a fair amount of power, which must be
supplied by the DC/DC converter.
Thermal Shutdown
Auxiliary NPN Devices (LT3473A Only)
The LT3473A has two auxiliary NPNs as shown in the
Block Diagram that can provide intermediate outputs less
than OUT. The collectors of the NPNs are connected to the
OUT pin internally. Each NPN can dissipate 100mW safely
and has a minimum beta of 60. A resistor string can be
The LT3473 has thermal shutdown circuitry that shuts down
the part when the junction temperature reaches approximately 145°C to protect the part from abnormal operation
with high power dissipation, such as an output short circuit or excessive power dissipation in the auxiliary NPNs.
The part will turn back on when the junction cools down to
approximately 125°C. If the abnormal condition remains,
the part will turn on and off while maintaining the junction
temperature within the window between 125°C and 145°C.
2 OUT
Board Layout Consideration
REXT1
3 NB1
4
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interference (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
pin has sharp rise and fall edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. Recommended component placement is shown in Figure 6.
REXT2
NE1
5 NB2
REXT3
6
NE2
3473 F05
Figure 5. Auxiliary NPN Transistors in LT3473A. REXT1, REXT2
and REXT3 Set Intermediate Voltage at NE1 and NE2
OUT
1
12
2
11
3
OUT
10
1
13
4
9
5
8
6
7
8
2
3
4
3473 F06a
7
9
6
5
3473 F06b
Figure 6. Recommended Component Placement
3473f
10
LT3473/LT3473A
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ± 0.10
(2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
4
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708)
4.00 ±0.10
(2 SIDES)
7
PACKAGE
OUTLINE
PIN 1
TOP MARK
(NOTE 6)
3.30 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
(2 SIDES)
PIN 1
NOTCH
(UE12/DE12) DFN 0603
0.200 REF
0.25 ± 0.05
0.38 ± 0.10
12
R = 0.20
TYP
0.65 ±0.05
3.50 ±0.05
1.70 ±0.05
2.20 ±0.05 (2 SIDES)
R = 0.115
TYP
0.75 ±0.05
0.50
BSC
0.00 – 0.05
3.30 ±0.10
(2 SIDES)
1
0.50
BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
6
0.25 ± 0.05
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3473f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT3473/LT3473A
U
TYPICAL APPLICATIO
Efficiency
OLED Bias
100k
PGOOD
OUT
COUT
2.2µF
CTRL
L1 6.8µH
SW
CAP
VIN
2M
20k
100nF
CINT
0.47µF
FB
SHDN
CIN
4.7µF
VIN = 3.6V
75
100k
GND
3473 TA02a
VOUT = 15V
VOUT = 25V
LT3473
EFFICIENCY (%)
VIN
3V TO 4.2V
80
VOUT
25V
80mA
VOUT = 20V
70
65
60
CIN: TAIYO YUDEN JMK107BJ475
CINT: TAIYO YUDEN GMK212BJ474
COUT: TAIYO YUDEN GMK325BJ225
L1: TOKO A915AY-6R8M (TYPE D53LC)
55
0
20
60
80
40
LOAD CURRENT IO (mA)
100
3473 TA02b
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3473f
12
Linear Technology Corporation
LT/TP 0205 1K • PRINTED IN THE USA
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