Features
Wide Input Range: 4V to 36V
n One 2.4A and Two 1.5A Output Switching
Regulators with Internal Power Switches
n Low Dropout Linear Regulator with External
Transistor
n Antiphase Switching Reduces Ripple
n Independent Run, Tracking/Soft-Start, and Power
Good Indicators Ease Supply Sequencing
n Uses Small Inductors and Ceramic Capacitors
n Adjustable, 250kHz to 2.5MHz Switching Frequency,
Synchronizable Over the Full Range
n User Programmable Overvoltage and Undervoltage
Lockouts
n Thermally Enhanced, 38-Lead 5mm × 7mm QFN
Package
n
Applications
DSL and Cable Modems
Distributed Power Regulation
n DSP Power
n Automotive
n
n
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
LT3507
Triple Monolithic Step-Down
Regulator with LDO
Description
The LT®3507 is a triple, current mode, DC/DC converter
with internal power switches and a low dropout regulator.
The switching converters are step-down converters capable
of generating one 2.4A output and two 1.5A outputs. All
three converters are synchronized to a single oscillator.
The 2.4A output runs with opposite phase to the other two
converters, reducing input ripple current. Each regulator
has independent shutdown and soft-start circuits, and
generates a power good signal when its output is in regulation, easing power supply sequencing and interfacing
with microcontrollers and DSPs.
The switching frequency is set with a single resistor yielding
a range of 250kHz to 2.5MHz. The high switching frequency
allows the use of small inductors and capacitors resulting
in a very small triple output supply. The constant switching
frequency, combined with low impedance ceramic capacitors, results in low, predictable output ripple. With its wide
input voltage range of 4V to 36V, the LT3507 regulates
a broad array of power sources including 5V logic rails,
unregulated wall transformers, lead acid batteries and
distributed power supplies.
Typical Application
5V, 3.3V, 2.5V and 1.8V Step-Down Regulator
Start-Up Waveforms—Coincident Tracking
VIN
6V TO 36V
22µF
VIN1
VIN2
BOOST1
VOUT3
BOOST2
0.22µF
4.7µH
VOUT1
1.8V
2.4A
VIN3
SW1
0.22µF
18.7k
100µF
15k
18.7k
VOUT2
VOUT3
5V
1.5A
VC1
1000pF
VC2
53.6k
10.2k
24.3k
22µF
FB2
SW3
22µF
35.7k
LT3507
VOUT4
VOUT1
VOUT2
3.3V
1.3A
680pF
0.22µF BOOST3
15µH
10µH
SW2
FB1
VOUT2
1V/DIV
FB3
BIAS
VC3
DRIVE
16.2k
1ms/DIV
11.5k
3507 TA01b
680pF
107k
RT/SYNC
FB4
GND
24.3k
11.5k
2.2µF
VOUT4
2.5V
0.2A
fSW = 450kHz
3507 TA01a
For more information www.linear.com/LT3507
3507fb
1
LT3507
SW3
SW3
VIN3
TOP VIEW
VIN3
VIN Pins....................................................... –0.3V to 36V
BOOST Pins...............................................................55V
BOOST Above SW......................................................25V
PGOOD Pins...............................................................36V
BIAS Pin.....................................................................16V
TRK/SS, VC, FB, RT/SYNC Pins....................................6V
RUN, OVLO, UVLO Pins............................................ VIN1
DRIVE Pin....................................................................5V
Operating Junction Temperature Range (Notes 2, 5)
LT3507E, LT3507I............................... –40°C to 125°C
LT3507H............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
BOOST3
pIN CONFIGURATION
SW1
(Note 1)
SW1
Absolute Maximum Ratings
38 37 36 35 34 33 32
BOOST1 1
31 VIN2
VIN1 2
30 VIN2
VIN1 3
29 SW2
VINSW 4
28 SW2
OVLO 5
27 BOOST2
UVLO 6
26 TRK/SS4
39
VC1 7
25 FB4
TRK/SS1 8
24 DRIVE
FB1 9
23 VC2
PGOOD1 10
22 FB2
PGOOD2 11
21 TRK/SS2
PGOOD3 12
20 FB3
VC3
TRK/SS3
BIAS
RUN3
RUN2
RUN1
RT/SYNC
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3507EUHF#PBF
LT3507IUHF#PBF
LT3507HUHF#PBF
LT3507EUHF#TRPBF
LT3507IUHF#TRPBF
LT3507HUHF#TRPBF
3507
3507
3507
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
Minimum Operating Voltage
Internal UVLO on VIN1
MIN
l
TYP
MAX
3.8
4
UNITS
V
Input Quiescent Current
Not Switching, VBIAS = 3.3V
2
3.5
mA
Bias Quiescent Current
Not Switching, VBIAS = 3.3V
5
7.5
mA
Shutdown Current
VRUN1,2,3 = 0V
1
µA
Reference Voltage Line Regulation
5V < VIN1 < 36V
0.01
%/V
3507fb
2
For more information www.linear.com/LT3507
LT3507
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
VC Source Current
VC = 0.6V
20
µA
VC Sink Current
VC = 0.6V
30
µA
1.7
V
VC Clamp Voltage
TYP
RT = 40.2k
Switching Phase
SW1 to SW2,3, RT = 40.2k
180
Deg
Foldback Frequency
VFB = 0V, RT = 40.2k
120
kHz
0.4
V
Frequency Shift Threshold on FB
RUN Threshold
1.1
UNITS
Switching Frequency
l
0.9
MAX
1
1.5
MHz
V
PGOOD Output Voltage Low
IPGOOD = 200µA
0.2
0.4
V
PGOOD Pin Leakage
VPGOOD = 2V
10
400
nA
PGOOD Threshold Offset
VFB Rising
58
80
105
mV
788
800
812
mV
–50
–500
nA
Feedback Pin Voltage
l
Feedback Pin Bias Current
l
Error Amplifier Transconductance
330
µS
Error Amplifier Voltage Gain
500
V/V
VC Switching Threshold
0.9
V
Switch Leakage Current
0.01
10
µA
Minimum Boost Voltage Above Switch (Note 4)
1.8
2.5
V
Converter 1
VC1 to Switch Current Gain
5
4.3
6
ISW1 = 2A
400
600
mV
ISW1 = 2A
40
60
mA
Switch 1 Current Limit (Note 3)
Duty Cycle = 15%
Switch 1 VCESAT
BOOST1 Operating Current
l
3
A/V
A
Converter 2
VC2 to Switch Current Gain
3.6
2.9
4
ISW2 = 1.5A
350
500
mV
ISW2 = 1.5A
40
60
mA
Switch 2 Current Limit (Note 3)
Duty Cycle = 15%
Switch 2 VCESAT
BOOST2 Operating Current
l
2
A/V
A
Converter 3
VC3 to Switch Current Gain
3.6
2.9
4
ISW3 = 1.5A
350
500
mV
ISW3 = 1.5A
40
60
mA
800
812
mV
Feedback Pin Bias Current
–150
–500
nA
Error Amplifier Voltage Gain
1100
V/V
0.05
%/V
Switch 3 Current Limit (Note 3)
Duty Cycle = 15%
Switch 3 VCESAT
BOOST3 Operating Current
l
2
A/V
A
LDO Regulator
Feedback Pin Voltage
Line Regulation
l
VIN from 5V to 36V
788
3507fb
For more information www.linear.com/LT3507
3
LT3507
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted (Note 2)
PARAMETER
CONDITIONS
MIN
Load Regulation
IDRIVE from 0.1mA to 10mA
TYP
MAX
0.005
%/mA
15
22.5
mA
Dropout Voltage, VIN1 to DRIVE
IDRIVE = 10mA, VIN1 = 5V
1.7
2.0
V
Dropout Voltage, BIAS to DRIVE
IDRIVE = 10mA, VIN1 = 5V
0.5
0.8
V
1.15
1.20
1.25
V
DRIVE Output Current Limit
l
10
UNITS
Over/Undervoltage Lockout
Undervoltage Lockout Threshold
Overvoltage Lockout Threshold
1.15
1.20
1.25
V
Undervoltage Lockout Hysteresis Current
V(UVLO) < 1.2V
7
10
13
µA
Overvoltage Lockout Hysteresis Current
V(OVLO) > 1.2V
–7
–10
–13
µA
Input Bias Current (OVLO and UVLO)
V(OVLO) = 1.0V, V(UVLO) = 1.5V
–100
–200
nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3507E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3507I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT3507H is guaranteed over the full
–40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 6: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum specifications refer to absolute values.
3507fb
4
For more information www.linear.com/LT3507
LT3507
Typical Performance Characteristics
VIN = 12V
VIN = 36V
60
50
0
0.5
1
1.5
IOUT (A)
2
50
0.1
0
1.5
0
3507 G02
VFB vs Temperature
0.5
1
1.5
ISW (A)
2
2.5
3
3507 G03
Frequency vs RT
2.5
TA = 25°C
804
50
CHANNEL 1
40
801
800
799
30
798
20
797
10
796
0
0.5
1
1.5
ISW (A)
2
2.5
FREQUENCY (MHz)
802
CHANNELS 2 & 3
60
VFB (mV)
IBOOST (mA)
1.2
803
70
795
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
3
3507 G04
0.25
Frequency vs VFB (Foldback)
1200
FRERQUENCY (kHz)
–0.5
–1.0
–1.5
3507 G07
3507 G06
ITRK/SS vs Temperature
1.28
800
600
1.26
1.24
400
1.22
200
–2.0
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
100
1.30
RT = 40.2k
TA = 25°C
1000
0.0
10
RT (kΩ)
3507 G05
Frequency vs Temperature
0.5
FREQUENCY DEVIATION (%)
0.6
0.9
IOUT (A)
805
80
0
0.3
CHANNEL 1
0.3
0.2
3507 G01
TA = 25°C
90
VIN = 36V
0
CHANNELS 2 & 3
0.4
60
BOOST Pin Current vs Switch
Current, Channels 1, 2 and 3
100
VIN = 12V
70
TA = 25°C
0.5
VIN = 6V
80
40
2.5
0.6
ITRK/SS (µA)
40
Switch VCESAT vs Switch Current,
Channels 1, 2 and 3
TA = 25°C
fSW = 450kHz
90
VIN = 6V
70
Efficiency vs Load Current,
Channels 2 and 3, VOUT = 3.3V
VSW (V)
80
EFFICIENCY (%)
100
TA = 25°C
fSW = 450kHz
EFFICIENCY (%)
90
Efficiency vs Load Current,
Channel 1, VOUT = 1.8V
0
0
0.2
0.4
0.6
VFB (V)
0.8
1
3507 G08
1.20
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
3507 G09
3507fb
For more information www.linear.com/LT3507
5
LT3507
Typical Performance Characteristics
RUN Threshold vs Temperature
VIN1-VINSW Voltage Drop vs IVINSW
0.40
1.2
TA = 25°C
0.4
3.0
0.25
ILIM (A)
VIN–VINSW (V)
0.6
0.20
0.15
0.00
0.5
0
0.2
3507 G10
250
0.4
0.6
IVINSW (mA)
Minimum On-Time vs ISW
25°C
–40°C
50
0
MINIMUM OFF-TIME (ns)
MINIMUM ON-TIME (ns)
150°C
100
0
1
2
ISW (A)
0.8
3
0.0
1.0
0
20
60
40
DUTY CYCLE (%)
3507 G11
200
200
150
CHANNELS 2 & 3
2.0
1.0
0.05
0.0
–50 –30 –10 30 50 70 90 110 130 150
TEMPERATURE (°C)
2.5
1.5
0.10
0.2
CHANNEL 1
3.5
0.30
0.8
TA = 25°C
4.0
0.35
1.0
RUN THRESHOLD (V)
Current Limit vs Duty Cycle
4.5
80
100
3507 G12
Minimum Off-Time vs ISW
–40°C
150
25°C
150°C
100
50
0
0
0.5
3507 G13
1
1.5
ISW (A)
2
2.5
3
3507 G14
3507fb
6
For more information www.linear.com/LT3507
LT3507
Pin Functions
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST
pins are used to provide drive voltages, higher than the
input voltage, to the internal bipolar NPN power switches.
These pins must be tied through a diode from VOUT, VIN
or another supply greater than 2.5V.
VIN1 (Pins 2, 3): The VIN1 pins supply power to the internal
switch of the 2.4A regulator and to the LT3507’s internal
reference and start-up circuitry. VIN1 must be above the
internal UVLO threshold of 3.8V (typical) for any of the
four channels to operate. These pins must be locally
bypassed (Note 6).
VINSW (Pin 4): The VINSW pin is a switched VIN1 for the
user programmable undervoltage and overvoltage detection. It is connected to VIN1 when any of the RUN pins
are pulled high, and high impedance when all RUN pins
are low or open.
OVLO (Pin 5): The LT3507 goes into overvoltage shutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
UVLO (Pin 6): The LT3507 goes into undervoltage shutdown when this pin drops below 1.2V. If unused, the UVLO
pin should be tied to VINSW.
VC1, VC2, VC3 (Pins 7, 23, 19): The VC pins are the outputs
of the internal error amps. The voltages on these pins
control the peak switch currents. These pins are normally
used to compensate the control loops. Each switching
regulator can be shut down by pulling its respective VC
pin to ground with an NMOS or NPN transistor.
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18,
26): The TRK/SS pins allow a regulator to track the output
of another regulator. When the TRK/SS pin is below 0.8V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the negative inputs of the error amplifiers. The LT3507 regulates
each feedback pin to the lesser of 0.8V or the TRK/SS
pin voltage. Connect the feedback resistor divider taps
to these pins.
PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The
PGOOD pins are the open-collector outputs of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. As well as indicating
output regulation, the PGOOD pins can sequence the
switching regulators. These pins must be left unconnected
if unused. The PGOOD outputs are valid when VIN is greater
than 3.8V and any of the RUN pins are high. They are not
valid when all RUN pins are low.
RT/SYNC (Pin 13): The RT/SYNC pin requires a resistor
to ground or a clock signal to set the operating frequency
of the LT3507.
RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are
used to shut down the individual switching regulators.
When all three RUN pins are low, the LT3507 shuts down
and draws less than 1µA from VIN1.
BIAS (Pin 17): The BIAS pin supplies the current to the
LT3507’s internal regulator. This pin should be tied to the
lowest available voltage source above 3V (either VIN, VOUT
or any other available supply). The LDO pass transistor’s
base current is supplied from the BIAS pin if it is at least
0.8V above the LDO DRIVE output.
DRIVE (Pin 24): The DRIVE pin provides the base drive
for an external NPN transistor used for the LDO regulator.
FB4 (Pin 25): The FB4 pin is the negative input to the LDO
error amplifier. It is regulated to 0.8V through the LDO
feedback resistor divider.
VIN2 (Pins 30, 31)/VIN3 (Pins 35, 36 ): The VIN2 and VIN3
pins supply power to the internal switches of the 1.5A
converters. These pins must be locally bypassed (Note 6).
SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33, 34):
The SW pins are the outputs of the internal power switches.
Connect these pins to the inductors and switching diodes.
Exposed Pad (Pin 39): Ground. The underside Exposed
Pad metal of the package provides both electrical contact
to ground and good thermal contact to the printed circuit
board. The Exposed Pad must be soldered to a grounded
pad on the circuit board for proper operation.
Note 6: VINX pins that are connected together may share a bypass capacitor.
3507fb
For more information www.linear.com/LT3507
7
LT3507
Block Diagram
VINSW
VIN1
OVLO
+
BIAS
–
RUN1
INT REG
AND REF
RUN2
MASTER
OSC
CLK1
CLK2
CLK3
1.2V
+
RUN3
RT/SYNC
UVLO
–
VIN4
DRIVE
VOUT4
SHDN
THERMAL
SHUTDOWN
+
+
–
TRK/SS4
0.8V
VIN
UNDERVOLTAGE
DETECTION
CHANNEL
SHUTDOWN
–
C1
+
+
SLOPE
C3
SLAVE
OSC
VOUTX
D1
0.4V
RC
–
CC
1.7V
+CLAMP
R2
0.8V
+
ILIMIT
+
1.25µA
C1
R1
FB
–
ERROR
–
AMP
+
VC
PGOOD
L1
SW
+
CF
D2
BOOST
R
S Q
–
–
VINX
CIN
+
0.9V
CLK
FB4
80mV
TRK/SS
+
GND
–
ONE OF THREE STEP-DOWN REGULATORS
3507 F01
Figure 1. LT3507 Block Diagram with Typical External Components
3507fb
8
For more information www.linear.com/LT3507
LT3507
Operation
The LT3507 contains three independent, constant frequency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common circuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by referring to the Block Diagram (Figure 1).
If the RUN pins are tied to ground, the LT3507 is shut
down and draws 1.25V. The master oscillator generates three clock signals,
with the signal for Channel 1 out of phase by 180°.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, current mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets the RS flip-flop and turns on the internal NPN bipolar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at VC, current comparator
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the VC
pin controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the VC pin voltage. The threshold
for switching on the VC pin is >0.9V and an active clamp
of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when VFB is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. VFB is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The switch drivers operate either from VIN or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will flow from VIN.
A power good comparator trips when the FB pin is at
90% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowing an external resistor to pull the PGOOD
pin high. Power good is valid when the LT3507 is enabled
and VIN > 3.5V.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2µF or greater.
The LDO is disabled when all three of the RUN pins are low.
The overvoltage and undervoltage detection shuts down
the LT3507 if the OVLO pin >1.2V or the UVLO pin 125°C
tON(MIN) = 155ns) and tOFF(MIN) = 170ns.
fMAX1 is the frequency at which the minimum duty cycle
is exceeded. The regulator will skip ON pulses in order to
reduce the overall duty cycle at frequencies above fMAX1.
It will continue to regulate but with increased inductor
current and greatly increased output ripple. The increased
peak inductor current in pulse-skipping will also stress
the switch transistor at high voltages and high switching
frequency. If the LT3507 is allowed to pulse-skip and
3507fb
10
For more information www.linear.com/LT3507
LT3507
APPLICATIONS INFORMATION
the input voltage is greater than 20V, then the switching
frequency must be kept below 1.1MHz to prevent damage
to the LT3507.
the BAS70 from On Semi or CMOD6263 from Central Semi.
RT should be set to provide a frequency within ±25% of
the final sync frequency.
fMAX2 is the frequency at which the maximum duty cycle
is exceeded. If there is sufficient charge on the BOOST
capacitor, the regulator will skip OFF periods to increase
the overall duty cycle at frequencies about fMAX2. It will
continue to regulate but with increased inductor current
and greatly increased output ripple.
Note that the restriction on the operating input voltage
refers to steady-state limits to keep the output in regulation; the circuit will tolerate input voltage transients up to
the absolute maximum rating.
Switching Frequency
Once the upper and lower bounds for the switching
frequency are found from the duty cycle requirements,
the frequency may be set within those bounds. Lower
frequencies result in lower switching losses, but require
larger inductors and capacitors. The user must decide
the best trade-off.
The switching frequency is set by a resistor connected
from the RT/SYNC pin to ground, or by forcing a clock
signal into RT/SYNC. The LT3507 applies a voltage of
~1.25V across this resistor and uses the current to set
the oscillator speed. The switching frequency is given by
the following formula:
fSW =
55
R T + 12
VCC
CLOCK
SYNC
CLK
The frequency sync signal will support VH logic levels from
1.8V to 5V CMOS or TTL. The duty cycle is not important,
but it needs a minimum on time of 100ns and a minimum
off time of 100ns. If the sync circuit is to be powered from
one of the LT3507 outputs there may be start-up problems
if the driving gate is high impedance without a supply or
pulls high or low at some intermediate supply voltage.
The circuit shown in Figure 2 prevents these problems by
isolating the clock sync circuit until the clock is operating.
The Schottky diode should be a low leakage type such as
LT3507
470pF
RT/SYNC SW1
BAS70
VOUT1
RT
3507 F02
Figure 2. Clock Powered from LT3507 Output
Inductor Selection and Maximum Output Current
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-topeak inductor ripple current. The LT3507 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3507 will deliver depends on the switch current
limit, the inductor value and the input and output voltages.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
ΔIL = (1– DC)
VOUT + VF
L•f
where f is the switching frequency of the LT3507 and L
is the value of the inductor. The peak inductor and switch
current is:
where fSW is in MHz and RT is in kΩ.
1k
ISWPK =ILPK =IOUT +
ΔIL
2
To maintain output regulation, this peak current must
be less than the LT3507’s switch current limit, ILIM. For
SW1, ILIM is at least 3A at low duty cycles and decreases
linearly to 2.4A at DC = 0.8. For SW2 and SW3, ILIM is at
least 2A for at low duty cycles and decreases linearly to
1.6A at DC = 0.8.
The minimum inductance can now be calculated as:
LMIN =
1− DCMIN VOUT + VF
•
2•f
ILIM – IOUT
3507fb
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11
LT3507
APPLICATIONS INFORMATION
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
large output capacitors to keep output voltage ripple low.
Select an inductor greater than LMIN that keeps the ripple
current below 30% of ILIM.
The inductor’s RMS current rating must be greater than the
maximum load current and its saturation current should
be greater than ILPK. For highest efficiency, the series
resistance (DCR) should be less than 0.1Ω. Table 1 lists
several vendors and types that are suitable.
Table 1. Inductors
PART NUMBER
VALUE
(µH)
ISAT
(A)
DCR
(Ω)
HEIGHT
(mm)
2.2
2.16
0.030
2.5
Sumida
CDC5D23-2R2
CDRH5D28-2R6
2.6
2.60
0.013
3.0
CDRH6D26-5R6
5.6
2.00
0.027
2.8
CDH113-100
10
2.00
0.047
3.7
1.5
2.10
0.060
2.0
Coilcraft
DO1606T-152
LPS6225-222ML
2.2
4.00
0.045
2.4
DO1608C-332
3.3
2.00
0.080
2.9
MSS6132-472ML
4.7
2.60
0.056
3.2
DO1813P-682HC
6.8
2.20
0.080
5.0
SD414-2R2
2.2
2.73
0.061
1.35
DRA73-6R8-R
6.8
2.96
0.041
3.55
UP1B-100
10
1.90
0.111
5.0
(D62F)847FY-2R4M
2.4
2.5
0.037
2.7
(D73LF)817FY-2R2M
2.2
2.7
0.03
3.0
Cooper
Toko
This analysis is valid for continuous mode operation
(IOUT > ILIM/2). For details of maximum output current in
discontinuous mode operation, see Linear Technology’s
Application Note AN44. Finally, for duty cycles greater
than 50% (VOUT/VIN > 0.5), a minimum inductance is
required to avoid subharmonic oscillations. This minimum
inductance is:
SW1:LMIN = ( VOUT + VF ) •
0.45
fSW
SW2, SW3:LMIN = ( VOUT + VF ) •
0.9
fSW
with LMIN in µH and fSW in MHz.
Output Capacitor Selection
The output capacitor filters the inductor current to generate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3507’s
control loop. Because the LT3507 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following
equations:
VRIPPLE =
ΔIL
for ceramic capacitors
8 • f • COUT
and
VRIPPLE = ΔIL • ESR for electrolytic capacitors
(tantalum and aluminum)
where ΔIL is the peak-to-peak ripple current in the inductor.
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
IC(RMS) =
ΔIL
12
3507fb
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LT3507
APPLICATIONS INFORMATION
Another constraint on the output capacitor is that it must
have greater energy storage than the inductor; if the stored
energy in the inductor transfers to the output, the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
⎛I
⎞2
LIM
COUT >10 •L • ⎜
⎟
VOUT ⎠
⎝
Diode Selection
The catch diode (D1 from Figure 2) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
The low ESR and small size of ceramic capacitors make them
the preferred type for LT3507 applications. Not all ceramic
capacitors are the same, however. Many of the higher value
capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
a large fraction of their capacitance with applied voltage
and at temperature extremes. Because loop stability and
transient response depend on the value of COUT, this loss
may be unacceptable. Use X7R and X5R types.
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 2 lists
several capacitor vendors.
Table 2. Low ESR Surface Mount Capacitors
VENDOR
TYPE
SERIES
Taiyo-Yuden
Ceramic
AVX
Ceramic
Tantalum
TPS
Kemet
Tantalum
Tantalum Organic
Aluminum Organic
T491,T494,T495
T520
A700
Sanyo
Tantalum or
Aluminum Organic
POSCAP
Panasonic
Aluminum Organic
SP CAP
TDK
Ceramic
ID(AVG) =
IOUT ( VIN – VOUT )
VIN
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current. Peak
reverse voltage is equal to the regulator input voltage. Use
a diode with a reverse voltage rating greater than the input
voltage, but not higher than 40V. Using higher breakdown
Schottky diodes may result in undesirable behavior. The
programmable OVLO can protect the diode from excessive
reverse voltage by shutting down the regulator if the input
voltage exceeds the maximum rating of the diode. Table
3 lists several Schottky diodes and their manufacturers.
Table 3. Schottky Diodes
VR
(V)
IAVE
(A)
VF AT 1A
(mV)
VF AT 2A
(mV)
MBRM120E
20
1
530
595
MBRM140
40
1
550
B120
20
1
500
B140
40
1
500
B220
20
2
500
B240
40
2
500
DFLS140L
40
1
DFLS240L
40
2
PART NUMBER
On Semiconductor
Diodes Inc
550
550
Boost Pin Considerations
The capacitor and diode tied to the BOOST pin generate a
voltage that is higher than the input voltage. In most cases,
a small ceramic capacitor and fast switching diode (such
as the CMDSH-3 or MMSD914LT1) will work well. The
capacitor value is a function of the switching frequency,
3507fb
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13
LT3507
APPLICATIONS INFORMATION
D2
D2
C3
BOOST
VIN
VIN
C3
BOOST
LT3507
LT3507
VIN
VOUT
SW
VIN
SW
VOUT
GND
GND
VBOOST – VSW ≅ VIN
MAX VBOOST ≅ 2VIN
VBOOST – VSW ≅ VOUT
MAX VBOOST ≅ VIN + VOUT
(3a)
(3b)
D2
VINB > 3V
BOOST
C3
LT3507
VIN
VIN
SW
VOUT
GND
VBOOST – VSW ≅ VINB
MAX VBOOST ≅ VINB + VIN
MINIMUM VALUE FOR VINB = 3V
3507 F03
(3c)
Figure 3. Generating the Boost Voltage
peak current, duty cycle and boost voltage; in general a
value of (0.1µF • 1MHz/fSW) works well. Figure 3 shows
three ways to arrange the boost circuit. The BOOST pin
must be more than 2.5V above the SW pin for full efficiency. For outputs of 3.3V and higher, the standard
circuit (Figure 3a) is best. For outputs between 2.8V and
3.3V, use a small Schottky diode (such as the BAT54).
For lower output voltages, the boost diode can be tied
to the input (Figure 3b). The circuit in Figure 3a is more
efficient because the BOOST pin current comes from a
lower voltage source. Finally, as shown in Figure 3c, the
anode of the boost diode can be tied to another source
that is at least 3V. For example, if you are generating 3.3V
and 1.8V and the 3.3V is on whenever the 1.8V is on, the
1.8V boost diode can be connected to the 3.3V output. In
this case, the 3.3V output cannot be set to track the 1.8V
output (see Output Voltage Tracking).
In any case, be sure that the maximum voltage at the
BOOST pin is less than 55V and the voltage difference
between the BOOST and SW pins is less than 25V.
The minimum operating voltage of an LT3507 application is limited by the internal undervoltage lockout (4V
for Channel 1, 3V for Channels 2 and 3) and by the
maximum duty cycle. The boost circuit also limits the
minimum input voltage for proper start-up. If the input
voltage ramps slowly, or the LT3507 turns on when the
output is already in regulation, the boost capacitor may
not be fully charged. Because the boost capacitor charges
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
input and output voltages, and on the arrangement of
the boost circuit. The minimum load current generally
goes to zero once the circuit has started. Figure 4 shows
a plot of minimum load to start and to run as a function
of input voltage. Even without an output load current, in
many cases the discharged output capacitor will present
a load to the switcher that will allow it to start.
The boost current is generally small but can become significant at high duty cycles. The required boost current is:
⎛ V ⎞⎛ I
⎞
IBOOST = ⎜ OUT ⎟⎜ OUT ⎟
⎝ VIN ⎠⎝ 40 ⎠
3507fb
14
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LT3507
APPLICATIONS INFORMATION
8.0
5.5
TA = 25°C
7.5 VOUT = 5V
5.0
TA = 25°C
VOUT = 3.3V
TO START
6.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
7.0
6.0
5.5
TO RUN
5.0
4.5
TO START
4.0
TO RUN
3.5
3.0
4.5
4.0
0.001
0.010
0.100
LOAD CURRENT (A)
2.5
0.001
1.000
3507 F04a
0.010
0.100
LOAD CURRENT (A)
1.000
3507 F04b
Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
Converter with Backup Output Regulator
Input Capacitor Selection
There is another situation to consider in systems where
the output will be held high when the input to the LT3507
is absent. If the VIN and one of the RUN pins are allowed
to float, then the LT3507’s internal circuitry will pull its
quiescent current through its SW pin. This is acceptable if
the system can tolerate a few mA of load in this state. With
all three RUN pins grounded, the LT3507 enters shutdown
mode and the SW pin current drops to 5% IOUT)
and the loop crossover frequency is less than fSW/5. A
phase lead capacitor (CPL) across the feedback divider
may improve the transient response.
SHUTDOWN
The RUN pins are used to place the individual switching
regulators and the internal bias circuits in shutdown mode.
When all three RUN pins are pulled low, the LT3507 is in
shutdown mode and draws less than 1µA from the input
supply. When any RUN pin is pulled high (>1.25V) the
internal reference, the LDO and selected channel are all
turned on.
The RUN pins draw a small amount of current to power
the reference. The current is less than 3µA at 1.8V, so the
RUN pin can be driven directly from 1.8V logic. The RUN
pins are rated up to 36V and can be connected directly to
the input voltage.
A RUN pin cannot be pulled up by logic powered by its
own output, i.e., RUN1 can’t be pulled up by logic powered
by OUT1.
POWER GOOD INDICATORS
The PGOOD pin is the open-collector output of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200µA. Note that this pin will be open when the LT3507
is in shutdown mode (all three RUN pins at ground) regardless of the voltage at the FB pin. PGOOD is valid when
the LT3507 is enabled (any RUN pin is high) and VIN is
greater than ~3.5V.
OUTPUT SEQUENCING
The LT3507 outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
each case channel 1 starts first, followed by channel 2,
then channel 3. The sequence shown is not a requirement;
the LT3507 can sequence the channels in any order. Note
that these circuits sequence the outputs during start-up.
When shut down the three channels turn off simultaneously.
3507fb
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17
LT3507
APPLICATIONS INFORMATION
LT3507
RUN1
RUN1
RUN2
RUN3
LT3507
RUN1
TRK/SS1
RUN2
RUN2
TRK/SS2
RUN3
RUN3
TRK/SS3
RUN
LT3507
C
RUN
RUN1
2C
VINSW
4C
PG1
RUN2
(7a)
(7b)
PG2
RUN3
LT3507
RUN
RUN1
TRK/SS1
RUN2
PG1
RUN3
TRK/SS2
PG2
(7c)
VIN
LT3507
RUN2
PG1
TRK/SS3
3507 F07
(7d)
(7e)
Doesn’t Work!
Figure 7. Output Sequencing
The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
Another possibility is to use the soft-start feature to slow
the start-up of specific channels (Figure 7b). All three RUN
pins are tied together and the difference in soft-start capacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
required, depending on the output capacitance and load on
each channel. Make sure to test the circuit in the system
before deciding on final values for these capacitors. Also
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
The PG pins can be also used to sequence the three outputs. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The resistors pull up to VINSW so that there is no current
draw in shutdown. They should be sized to provide at least
1µA into the RUN pin. The capacitors keep channels 2 and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its final value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
outputs at start-up, they also disable the slaved channels
if the master channel falls out of regulation (due to a short
circuit or a collapsing input voltage).
Finally, be aware that the circuit in Figure 7e does not
work, because the power good comparators are disabled
in shutdown.
3507fb
18
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LT3507
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT2
3507 F08
TIME
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8. Two Different Modes of Output Voltage Tracking
VOUT1
TO
TRK/SS2
PIN
VOUT2
R5
R6
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
Tracking Setup
R3
SELECTING VALUES FOR R5 AND R6
R4
R5 =
R6 =
COINCIDENT RATIOMETRIC
R3
R1
R4
R1
VOUT1/1V – 1
R3 VOUT2 ⎞
⎛ R1 VOUT1
⎜⎝ R2 = 0.8 – 1, R4 = 0.8 – 1⎟⎠
Figure 9. Setup for Coincident and Ratiometric Tracking
OUTPUT VOLTAGE TRACKING
The LT3507 allows the user to program how the output
ramps up by means of the TRK/SS pins. Through these
pins, any channel output can be set up to either coincidently or ratiometrically track any other channel output.
This example will show the channel 2 output tracking the
channel 1 output, as shown in Figure 8. The TRK/SS2 pin
acts as a clamp on channel 2’s reference voltage. VOUT2
is referenced to the TRK/SS2 voltage when the TRK/SS2
< 0.8V and to the internal precision reference when TRK/
SS2 > 0.8V.
To implement the coincident tracking in Figure 8a, connect
an extra resistive divider to the output of channel 1 and
connect its midpoint to the TRK/SS2 pin (Figure 9). The
ratio of this divider should be selected the same as that
of channel 2’s feedback divider (R5 = R3 and R6 = R4). In
this tracking mode, VOUT1 must be set higher than VOUT2.
To implement the ratiometric tracking in Figure 8b, change
the extra divider ratio to R5 = R1 and R6 = R2 + ΔR. The
extra resistance on R6 should be set so that the TRK/SS2
voltage is ≥1V when VOUT1 is at its final value.
The need for this extra resistance is best understood with
the help of the equivalent input circuit shown in Figure 10.
At the input stage of the error amplifier, two common anode
diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted
common mode voltage. The top two current sources are
of the same amplitude. In the coincident mode, the TRK/
SS2 voltage is substantially higher than 0.8V at steady
state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching
between VFB2 and the internal precision 0.8V reference. In
the ratiometric mode with R6 = R2, TRK/SS2 equals 0.8V
at steady state. D1 will divert part of the bias current and
make VFB2 slightly lower than 0.8V. Although this error
I
I
1.25µA
TRK/SS
0.8V
FB
D1
+
D2
EA2
–
D3
3507 F10
Figure 10. Equivalent Input Circuit of Error Amplifier
3507fb
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19
LT3507
APPLICATIONS INFORMATION
is minimized by the exponential I-V characteristic of the
diodes, it does impose a finite amount of output voltage
deviation. Further, when channel 1’s output experiences
dynamic excursions (under load transient, for example),
channel 2 will be affected as well. Setting R6 to a value
that pushes the TRK/SS2 voltage to 1V at steady state will
eliminate these problems while providing near ratiometric
tracking.
The example shows channel 2 tracking channel 1, however
any channel may be set up to track any other channel.
If a capacitor is tied from the TRK/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This results in a ramp at the output, limiting the
inductor current and therefore input current during start-up.
A good value for the soft-start capacitor is COUT/10,000,
where COUT is the value of the output capacitor.
MULTIPLE INPUT SUPPLIES
VIN1, VIN2 and VIN3 are independent and can be powered
with different voltages provided VIN1 is present when VIN2
or VIN3 is present. Each supply must be bypassed as close
to the VIN pins as possible.
For applications requiring large inductors due to high VIN
to VOUT ratios, a 2-stage step-down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application steps down the input voltage (VIN1)
to the highest output voltage, then uses that voltage to
power the other outputs (VIN2 and VIN3). VOUT1 must be
able to provide enough current for its output plus the
input current at VIN2 and VIN3 when VOUT2 and VOUT3 are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
For applications with multiple voltages, the LT3507 can
accommodate input voltages as low as 3V on VIN2 and
VIN3. This can be useful in applications regulating outputs
from a PCI Express bus, where the 12V input is power
limited and the 3.3V input has power available to drive
other outputs. In this case, tie the 12V input to VIN1 and
the 3.3V input to VIN2 and VIN3.
LOW DROPOUT REGULATOR
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same 0.8V
reference as the switching regulators. It requires an external
NPN pass transistor and 2.2µF of output capacitance for
stability. The internal compensation is stable with loads
up to 300mA.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 4 lists some suitable
NPN transistors with their saturation specifications.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
5V – VBESAT where VBESAT is the base-emitter saturation
voltage of the pass transistor.
Table 4. NPN Pass Transistors and Saturation Characteristics
PART NUMBER
VCESAT
VBESAT
IC (mA)
IB (mA)
On Semiconductor
NSS30071
0.25
0.85
500
5
NSS30101
0.2
0.85
1000
10
500
20
Fairchild
KSC3265
0.4
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pulling the FB4 pin up with a 30µA current source. The FB4
pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3507 outputs provided that channel is
always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
3507fb
20
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LT3507
APPLICATIONS INFORMATION
FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (Refer to Block Diagram) between the
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
⎛V
⎞
R1=R2 ⎜ OUT4 −1⎟
⎝ 800mV ⎠
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
Figure 11 shows a typical connection. The threshold
voltages are:
⎛ R3 ⎞
VOVTH = 0.3V+1.2V • ⎜1+ ⎟
⎝ R4 ⎠
⎛ R1 ⎞
VUVTH = 0.3V+1.2V • ⎜1+ ⎟
⎝ R2 ⎠
The hysteresis voltages are:
VOVHYST = 10µA • R3
VUVHYST = 10µA • R1
PROGRAMMABLE OVERVOLTAGE and
UNDERVOLTAGE LOCKOUT
The LT3507 provides two input pins that allow userprogrammable overvoltage and undervoltage lockout. Both
the trip levels and hysteresis can be set by resistor values.
VINSW provides a switched VIN1 to minimize power consumption in shutdown. VINSW is connected to VIN1 when
the LT3507 is operating, with a saturation voltage of about
0.3V. It is high impedance when the LT3507 is in shutdown
(all three RUN pins low).
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO comparator trips when the UVLO pin drops below 1.2V. These
comparators shut down all four regulators until the input
voltage recovers.
The comparators also activate current sources that generate hysteresis to eliminate chatter. The UVLO comparator
activates a 10µA current sink on the UVLO pin. The OVLO
comparator activates a 10µA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to VINSW.
VINSW
R1
10µA
R3
UVLO
R2
–
UVLO
+
1.2V
–
OVLO
OVLO
+
R4
10µA
3507 F11
Figure 11. Undervoltage and Overvoltage Lockout Circuit
3507fb
For more information www.linear.com/LT3507
21
LT3507
APPLICATIONS INFORMATION
VIN
VIN
SW
GND
SW
GND
(12a)
VIN
IC1
(12b)
VSW
C1
L1
SW
D1
GND
(12c)
C2
3507 F12
Figure 12. Subtracting the Current When the Switch is ON (12a) From the Current When the Switch is OFF (12b) Reveals the Path of
the High Frequency Switching Current (12c) Keep this Loop Small. The Voltage on the SW and Boost Nodes Will Also be Switched;
Keep These Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
Figure 13. Power Path Components and Topside Layout
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regulator circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components, along with the inductor and output capacitor,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of
the output capacitor C2. Additionally, keep the SW and
BOOST nodes as small as possible. Figure 13 shows an
example of proper PCB layout.
3507fb
22
For more information www.linear.com/LT3507
LT3507
APPLICATIONS INFORMATION
THERMAL CONSIDERATIONS
The high output current capability of the LT3507 will require
careful attention to power dissipation of all the components
to insure a safe thermal design. The PCB must provide
heat sinking to keep the LT3507 cool. The Exposed Pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to other copper layers
below with thermal vias; these layers will spread the heat
dissipated by the LT3507. Place additional vias near the
catch diodes. Adding more copper to the top and bottom
layers and tying this copper to the internal planes with vias
can reduce thermal resistance further. With these steps,
the thermal resistance from die (or junction) to ambient
can be reduced to θJA = 34°C/W or less. With 100 LFPM
airflow, this resistance can fall by another 25%. Further
increases in airflow will lead to lower thermal resistance.
The maximum allowed power dissipation by the LT3507
can be determined by:
PDISS(MAX) =
TJ(MAX) – TA
θJA
where TJMAX is the maximum die temperature of 125°C
(150°C for H-grade).
However, take care in determining TA since the catch
diodes also dissipate power and must be located close
to the LT3507. Another potential heat source is the LDO
pass transistor. In a compact layout the pass transistor
will be located close to the LT3507. The inductors will
also dissipate some power due to their series resistance
and they must be close to the LT3507. All of these heat
sources will increase the effective ambient temperature
seen by the LT3507.
A thorough analysis of eight heat sources in a small PCB
area is beyond the scope of this data sheet, however a
number of thermal analysis programs are available to
calculate the temperature rise in each component (such
as PCAnalyze from K&K Associates or BETAsoft from
Mentor). The power dissipation of each component will be
needed to accurately calculate the thermal characteristics
of the system.
The contributors to power dissipation inside the LT3507
are switch DC loss, switch AC loss, boost current, quiescent current and LDO drive current. The total dissipation
within the LT3507 can be expressed as:
3
PDISS = ∑ (PSWDCi + PSWACi + PBSTi ) + PQ + PLDO
i=1
The switch DC and AC losses in channel i are:
2
PSWDCi =
RSWi (IOUTi ) VOUTi
VINi
PSWACi = 17ns (IOUTi ) ( VINi ) ( f )
where RSWi is the equivalent switch resistance (0.18Ω for
channel 1 and 0.22Ω for channels 2 and 3) and f is the
operating frequency.
The boost loss in channel i is:
⎞
⎛I
VOUTi ( VBOOSTi ) ⎜ OUTi +0.02A ⎟
⎝ 50
⎠
PBSTi =
VINi
The quiescent loss is:
PQ = VIN1(IQ(VIN1)) + VBIAS(IQ(BIAS))
If the BIAS pin does not have a voltage of at least 3V applied, then VIN1 must replace VBIAS in the equation. Also,
IQ(VIN1) can be reduced by 0.2mA (typ) if the LDO is shut
off (see the LDO section).
The LDO drive loss is:
⎛ IOUT(LDO) ⎞
PLDO =(VBIAS −VLDO(OUT) −0.7V)⎜
⎟,
⎝ βPASS ⎠
if VBIAS ≥ VLDO(OUT) +1.5V
or
⎛ IOUT(LDO) ⎞
PLDO =(VIN1 −VLDO(OUT) −0.7V)⎜
⎟,
⎝ βPASS ⎠
if VBIAS 1V becomes VC pin >0.9V.
9
Clarified last paragraph in Operation description.
9
Clarified first paragraph of Input Voltage Range.
10
Added clarification in second paragraph of Diode Selection.
13
Replaced >1.5V with >1.25V in Shutdown description.
17
Clarified Figure 10.
19
Clarified Low Dropout Regulator first paragraph.
20
Clarified Typical Application Schematic.
26
Clarified Typical Application Schematic.
30
3507fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3507
29
LT3507
typical applications
12V to 5V, 3.3V, 1.8V and 1.6V with 1.5mm Maximum Height
VIN
8V TO 16V
10µF
VIN1
VOUT1
1.8V
2A
VOUT2
3.3V
1.5A
L1 2µH
0.1µF
22.6k
33µF
D1
18.2k
13.3k
L2 4.5µH
1000pF
D2
SW1
2000pF
OVLO
PGOOD1
PGOOD2
PGOOD3
TRK/SS1
BOOST3
UVLO = 7V
VOUT2
VOUT1
FB3
FB2
100k
100k
PGOOD1
PGOOD2
PGOOD3
0.1µF
SW3
LT3507
L3 4.5µH
61.9k
1200pF
VC2
11.3k
1.5nF
VOUT2
VOUT3
5V
1.4A
10µF
D3
VC3
11.8k
TRK/SS3
BIAS
TRK/SS2
D1: DIODES, INC. DFLS220L
D2, D3: DIODES, INC. DFLS120L
L1: COOPER SD14-2R0-R
L2, L3: COOPER SD14-4R5-R
Q1: ON SEMI NSS30071MR6T1G
OVLO = 17V
100k
VC1
1.5nF
RT/SYNC
31.6k
VOUT2
VOUT1
DRIVE
FB4
RUN1
RUN2
RUN3
SHDN
11.3k
FB1
SW2
7.32k
13.3k
UVLO
BOOST2
41.2k
4.02k
49.9k
VIN3 VINSW
BOOST1
1.5nF
0.1µF
10µF
VIN2
49.9k
Q1
20.0k
TRK/SS4
GND
VOUT4
1.6V
0.2A
2.2nF
fSW = 1.25MHz
2.2µF
20.0k
3507 TA03
related parts
PART NUMBER DESCRIPTION
COMMENTS
LT1939
25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO Controller
VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 2.5mA, ISD < 10µA, 3 × 3 DFN-10 Package
LT1940
Dual 25V, 1.4A (IOUT), 1.1MHz, High Efficiency Step-Down DC/DC
Converter
VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 1.20V,
IQ = 3.8mA, ISD < 30µA, TSSOP16E Package
LT3480
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode® Operation
VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3481
34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode Operation
VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V,
IQ = 50µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3493
36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter
VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V,
IQ = 1.9mA, ISD < 1µA, 2 × 3 DFN-6 Package
LT3500
36V, 40Vmax, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO
Controller
VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V,
IQ = 2.5mA, ISD < 10µA, 3 × 3 DFN-10 Package
LT3501/
LT3510
25V, Dual 3A/2A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC
Converter
VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 3.7mA, ISD = 10µA, TSSOP-20E Package
LT3505
36V with Transient Protection to 40V, 1.4A (IOUT), 3MHz, High Efficiency
Step-Down DC/DC Converter
VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 0.78V,
IQ = 2mA, ISD = 2µA, 3 × 3 DFN-8, MSOP-8E Package
LT3506/
LT3506A
25V, Dual 1.6A (IOUT), 575kHz/1.1MHz High Efficiency Step-Down DC/
DC Converter
VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 3.8mA, ISD = 30µA, TSSOP-16E, 5 × 4 DFN-16 Package
LT3508
36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz, High
Efficiency Step-Down DC/DC Converter
VIN(MIN) = 3.7V, VIN(MAX) = 37V, VOUT(MIN) = 0.8V,
IQ = 4.6mA, ISD = 1µA, 4 × 4 QFN-24, TSSOP-16E Package
LT3684
34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency
Step-Down DC/DC Converter
VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V,
IQ = 850µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3685
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency
Step-Down DC/DC Converter
VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
3507fb
30
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT3507
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT3507
LT 0116 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2008
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