LT3579/LT3579-1
6A Boost/Inverting
DC/DC Converter with Fault Protection
FEATURES
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DESCRIPTION
6A, 42V Combined Power Switch
Output Short Circuit Protection
Wide Input Range: 2.5V to 16V Operating,
40V Maximum Transient
LT3579-1: Dual-Phase Capable
Master/Slave (3.4A/2.6A) Switch Design
User Configurable Undervoltage Lockout
Easily Configurable as a Boost, SEPIC, Inverting, or
Flyback Converter
Low VCESAT Switch: 250mV at 5.5A (Typical)
Can Be Synchronized to External Clock
Can Synchronize other Switching Regulators
High Gain SHDN Pin Accepts Slowly Varying Input
Signals
20-Lead TSSOP and 20-Pin 4mm × 5mm QFN
Packages
The LT®3579 is a PWM DC/DC converter with built-in fault
protection features to aid in protecting against output shorts,
input/output overvoltage, and overtemperature conditions.
The part consists of a 42V master switch, and a 42V slave
switch that can be tied together for a total current limit of 6A.
The LT3579 is ideal for many local power supply designs. It
can be easily configured in Boost, SEPIC, Inverting, or Flyback
configurations, and is capable of generating 12V at 1.7A, or
–12V at 1.2A from a 5V input. In addition, the LT3579’s slave
switch allows the part to be configured in high voltage, high
power charge pump topologies that are very efficient and
require fewer components than traditional circuits.
The LT3579’s switching frequency range can be set bet
ween 200kHz and 2.5MHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to
ground, or it may be synchronized to an external clock.
A buffered version of the clock signal is driven out of
the CLKOUT pin, and may be used to synchronize other
compatible switching regulator ICs to the LT3579.
APPLICATIONS
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Local Power Supply
Vacuum Fluorescent Display (VFD) Bias Supplies
TFT-LCD Bias Supplies
Automotive Engine Control Unit (ECU) Power
The LT3579 also features innovative SHDN pin circuitry
that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features
such as frequency foldback and soft-start are integrated.
The LT3579 is available in 20-lead TSSOP and 20-pin
4mm × 5mm QFN packages.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7579816.
TYPICAL APPLICATION
Efficiency and Power Loss
1MHz, 5V to 12V Boost Converter with Output Short Circuit Protection
2.2µH
SW1 SW2
22µF
100k
200k
VIN
FAULT
SHDN
6.3k
10µF
GATE
LT3579
CLKOUT
VC
RT
SYNC GND
86.6k
130k
FB
VIN
TEMPERATURE
MONITOR
8k
SS
0.1µF
47pF
2.2nF
3.2
90
2.8
80
2.4
70
2.0
60
1.6
50
1.2
40
0.8
30
0.4
20
35791 TA01
0
0.25 0.5 0.75 1 1.25 1.5 1.75
LOAD CURRENT (A)
2
POWER LOSS (W)
10µF
VOUT
12V
1.7A
EFFICIENCY (%)
VIN
5V
100
0
35791 TA02
Rev. B
Document Feedback
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1
LT3579/LT3579-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN Voltage.................................................. –0.3V to 40V
SW1/SW2 Voltage ...................................... –0.4V to 42V
RT Voltage..................................................... –0.3V to 5V
SS, FB Voltage .......................................... –0.3V to 2.5V
VC Voltage .................................................... –0.3V to 2V
SHDN Voltage............................................. –0.3V to 40V
SYNC Voltage............................................. –0.3V to 5.5V
GATE Voltage.............................................. –0.3V to 80V
FAULT.......................................................... –0.3V to 40V
FAULT Current......................................................±0.5mA
CLKOUT........................................................ –0.3V to 3V
CLKOUT Current..................................................... ±1mA
Operating Junction Temperature Range
LT3579E (Notes 2, 4).......................... –40°C to 125°C
LT3579I (Notes 2, 4)........................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
19 SS
GATE
3
18 RT
FAULT
4
17 SHDN
VIN
5
SW1
6
16 RT
15 SHDN
FAULT 2
16 CLKOUT
VIN 3
14 CLKOUT
21
GND
13 SW2
15 SW2
SW1 4
14 SW2
SW1 5
12 SW2
SW1 6
11 SW2
13 SW2
SW1
9
12 SW2
SW1 10
11 SW2
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
7
8
9 10
SW2
8
GND
SW1
GND
7
20 19 18 17
GATE 1
SW1
SW1
21
GND
SYNC
20 SYNC
2
SS
1
FB
FB
VC
VC
TOP VIEW
TOP VIEW
UFD PACKAGE
20-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 2.7°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3579EFE#PBF
LT3579EFE#TRPBF
LT3579FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3579IFE#PBF
LT3579IFE#TRPBF
LT3579FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3579EUFD#PBF
LT3579EUFD#TRPBF
3579
20-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3579IUFD#PBF
LT3579IUFD#TRPBF
3579
20-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3579EFE-1#PBF
LT3579EFE-1#TRPBF
LT3579FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
LT3579IFE-1#PBF
LT3579IFE-1#TRPBF
LT3579FE-1
20-Lead Plastic TSSOP
–40°C to 125°C
LT3579EUFD-1#PBF
LT3579EUFD-1#TRPBF
35791
20-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3579IUFD-1#PBF
LT3579IUFD-1#TRPBF
35791
20-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
2
Rev. B
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LT3579/LT3579-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2).
PARAMETER
CONDITIONS
Minimum Input Voltage
MIN
TYP
2.3
2.5
V
16.2
18.7
21.2
V
V
l
VIN Overvoltage Lockout
MAX
UNITS
Positive Feedback Voltage
l
1.195
1.215
1.230
Negative Feedback Voltage
l
3
9
16
mV
µA
Positive FB Pin Bias Current
VFB=Positive Feedback Voltage, Current into Pin
l
80.5
83.3
85
Negative FB Pin Bias Current
VFB=Negative Feedback Voltage, Current out of Pin
l
81
83.3
85.5
Error Amp Transconductance
ΔI=10μA
Error Amp Voltage Gain
Quiescent Current
Not Switching
Quiescent Current in Shutdown
VSHDN = 0V
Reference Line Regulation
2.5V ≤ VIN ≤ 15V
Switching Frequency, fOSC
RT = 34kΩ
l
2.2
RT = 432kΩ
l
175
Switching Frequency in Foldback
Compared to Normal fOSC
Switching Frequency Range
Free-Running or Synchronizing
200
SYNC High Level for Sync
l
1.3
SYNC Low Level for Sync
l
SYNC Clock Pulse Duty Cycle
µmhos
70
V/V
1.9
2.4
mA
0
1
µA
0.01
0.05
%/V
2.5
2.8
MHz
200
225
kHz
1/6
l
VSYNC = 0V to 2V
µA
250
ratio
2500
kHz
V
20
0.4
V
80
%
Recommended Minimum SYNC Ratio
fSYNC/fOSC
3/4
Minimum Off-Time
45
nS
Minimum On-Time
55
nS
SW1 Current Limit
At All Duty Cycles (Note 3)
SW Current Sharing, ISW2/ISW1
SW1 and SW2 Tied Together
SW1 + SW2 Current Limit
ISW2/ISW1 = 0.78, At All Duty Cycles (Note 3)
Switch VCESAT
l
3.4
4.2
5.1
0.78
7.5
9.4
A
SW1 and SW2 Tied Together, ISW1 + ISW2 = 5.5A (Note 5)
250
350
mV
SW1 Leakage Current
VSW1 = 5V
0.01
1
µA
SW2 Leakage Current
VSW2 = 5V
0.01
1
µA
l
6
A
A/A
Rev. B
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3
LT3579/LT3579-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN unless otherwise noted. (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Soft-Start Charge Current
VSS = 30mV, Current Flows Out of SS pin
l
5.7
8.7
11.3
µA
Soft-Start Discharge Current
Part in FAULT
VSS = 2.1V,
Current Flows into SS Pin
l
5.7
8.7
11.3
µA
Soft-Start High Detection Voltage
Part in FAULT
l
1.65
1.8
1.95
V
Soft-Start Low Detection Voltage
Part Exiting FAULT
l
30
50
85
SHDN Minimum Input Voltage High
Active Mode, SHDN Rising
Active Mode, SHDN Falling
l
l
1.27
1.24
1.33
1.3
1.41
1.38
l
.3
V
60
13.4
0.1
µA
µA
µA
mV
V
V
SHDN Input Voltage Low
Shutdown Mode
SHDN Pin Bias Current
VSHDN = 3V
VSHDN = 1.3V
VSHDN = 0V
9.5
40
11.4
0
CLKOUT Output Voltage High
CCLKOUT = 50pF
1.9
2.1
2.3
V
200
mV
CLKOUT Output Voltage Low
CCLKOUT = 50pF
100
CLKOUT Duty Cycle
LT3579, TJ = 25°C
42
LT3579-1, All TJ
50
%
CLKOUT Rise Time
CCLKOUT = 50pF
12
ns
CLKOUT Fall Time
CCLKOUT = 50pF
8
ns
GATE Pull Down Current
VGATE = 3V
VGATE = 80V
l
l
GATE Leakage Current
VGATE = 50V, GATE Off
FAULT Output Voltage Low
50μA into FAULT Pin
FAULT Leakage Current
VFAULT = 40V, FAULT Off
800
800
l
933
933
%
1100
1100
µA
µA
0.01
1
µA
100
300
mV
0.01
1
µA
FAULT Input Voltage Low Threshold
l
700
750
800
mV
FAULT Input Voltage High Threshold
l
950
1000
1050
mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3579E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3579I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
4
Note 3: Current limit guaranteed by design and/or correlation to static test.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 5: The UFD package switch VCESAT is guaranteed by design,
characterization and bench correlation.
Rev. B
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LT3579/LT3579-1
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Current Limit
Switch Saturation Voltage
10
1.0
0.9
300
7
6
5
4
3
2
VSW1 = VSW2
0.8
250
0.7
ISW2/ISW1 (A/A)
8
SATURATION VOLTAGE (mV)
SW1 + SW2 CURRENT (A)
Switch Current Sharing
350
9
200
150
100
20
30
40
50
60
DUTY CYCLE (%)
70
0
80
0.4
0.3
0
1
2
3
4
5
6
SW1 + SW2 CURRENT (A)
7
0.0
8
9
9
8
8
5
4
3
2
1
1.5 2 2.5 3
SW1 CURRENT (A)
1
3.5
4
Positive Feedback Voltage
1.23
1.225
7
FB VOLTAGE (V)
SW1 + SW2 CURRENT (A)
10
6
0.5
35791 G03
Commanded Switch Current vs SS
10
7
0
35791 G02
Switch Current Limit
vs Temperature
SW1 + SW2 CURRENT (A)
0.5
0.1
35791 G01
6
5
4
3
2
1.22
1.215
1.21
1.205
1
0
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
0.2
0.4
0.6
0.8
SS VOLTAGE (V)
1
35791 G04
RT = 34k
RT = 432k
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G07
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G06
Oscillator Frequency During
Soft-Start
CLKOUT Duty Cycle
1
80
70
CLKOUT DUTY CYCLE (%)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
–50 –25
1.2
–50 –25
1.2
35791 G05
NORMALIZED OSCILLATOR FREQUENCY (FSW/FNOM)
Oscillator Frequency
FREQUENCY (MHz)
0.6
0.2
50
1
0
TA = 25°C, unless otherwise noted.
1/2
1/3
1/4
1/5
1/6
0
INVERTING
CONFIGURATIONS
0
0.2
BOOSTING
CONFIGURATIONS
0.4
0.6
0.8
FB VOLTAGE (V)
1
1.2
35791 G08
60
50
40
30
20
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G09
Rev. B
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5
LT3579/LT3579-1
TYPICAL PERFORMANCE CHARACTERISTICS
45
900
40
CLKOUT RISE TIME
35
30
25
20
15
CLKOUT FALL TIME
10
Gate Pin Current (VSS = 2.1V)
1000
800
TA = –40°C
700
TA = 25°C
TA = 125°C
600
550
400
300
800
700
600
500
400
300
200
200
5
100
100
0
0
0
50
100
150
200
CLKOUT CAPACITIVE LOAD (pF)
250
Gate Pin Current (VGATE = 5V)
900
GATE PIN CURRENT (µA)
1000
GATE PIN CURRENT (µA)
CLKOUT RISE OR FALL TIME (ns)
CLKOUT Rise Time at 1MHz
50
TA = 25°C, unless otherwise noted.
0
10
20 30 40 50 60
GATE PIN VOLTAGE (V)
70
0
80
0
0.25
0.5
0.75
1
SS VOLTAGE (V)
1.25
1.5
35791 G10
35791 G11
Active/Lockout Threshold
35791 G12
SHDN Pin Current
1.4
SHDN Pin Current
30
250
TA = –40°C
1.38
1.34
SHDN PIN CURRENT (µA)
SHDN VOLTAGE (V)
SHDN RISING
1.32
1.3
SHDN FALLING
1.28
1.26
1.24
20
15
10
TA = 25°C
5
TA = 125°C
1.22
1.2
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
Internal UVLO
22
2.45
21
2.2
0
5
10
15 20 25 30
SHDN VOLTAGE (V)
35
40
Fault Input Threshold
1.25
FAULT RISING
1
19
18
17
16
15
0.75
FAULT FALLING
0.5
0.25
13
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G16
6
VIN OVLO
14
2.15
50
35791 G15
FAULT VOLTAGE (V)
VIN VOLTAGE (V)
VIN VOLTAGE (V)
2.4
2.25
100
0
2
20
2.3
TA = 125°C
150
35791 G14
2.5
2.35
TA = 25°C
200
TA = –40°C
0.25 0.5 0.75 1 1.25 1.5 1.75
SHDN VOLTAGE (V)
35791 G13
2.1
–50 –25
SHDN PIN CURRENT (µA)
25
1.36
12
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G17
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
35791 G18
Rev. B
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LT3579/LT3579-1
PIN FUNCTIONS
(QFN/TSSOP)
GATE (Pin 1/Pin 3): PMOS Gate Drive Pin. The GATE pin
is a pull-down current source, and can be used to drive
the gate of an external PMOS transistor for output short
circuit protection or output disconnect. The GATE pin
current increases linearly with the SS pin’s voltage, with
a maximum pull-down current of 933µA at SS voltages
exceeding 500mV. Note that if the SS voltage is greater
than 500mV, and the GATE pin voltage is less than 2V, the
GATE pin looks like a 2kΩ impedance to ground. See the
Appendix for more information.
FAULT (Pin 2/Pin 4): Fault Indication Pin. This active low,
bidirectional pin can either be pulled low (below 750mV)
by an external source, or internally by the chip to indicate a fault. When pulled low, this pin causes the power
switches to turn off, the GATE pin to become high impedance, the CLKOUT pin to become disabled, and the SS
pin to go through a charge/discharge sequence. The end/
absence of a fault is indicated when the voltage on this
pin exceeds 1V. A pull-up resistor or some other form of
pull-up network needs to exist on this pin to pull it above
1V in the absence of a fault.
VIN (Pin 3/Pin 5): Input Supply Pin. Must be locally
bypassed.
SW1 (Pins 4 - 7/Pins 6 - 10): Master Switch Pin. This is the
collector of the internal master NPN power switch. SW1
is designed to handle a peak collector current of 3.4A
(minimum). Minimize the metal trace area connected to
this pin to minimize EMI.
GND (Pins 8, 9, Exposed Pad Pin 21/Exposed Pad Pin 21):
Ground. Must be soldered directly to local ground plane.
SW2 (Pins 10-13/Pins 11-15): Slave Switch Pin. This is
the collector of the internal slave NPN power switch. SW2
is designed to handle a peak collector current of 2.6A
(minimum). Minimize the metal trace area connected to
this pin to minimize EMI.
CLKOUT (Pin 14/Pin 16): Clock Output Pin. Use this pin to
synchronize one or more other ICs to the LT3579. This pin
oscillates at the same frequency as the internal oscillator
of the part or as the SYNC pin. CLKOUT may also be used
as a temperature monitor since the CLKOUT pin’s duty
cycle varies linearly with the part’s junction temperature.
The CLKOUT pin signal of the LT3579-1 is 180° out of
phase with the internal oscillator or SYNC pin, and the
duty cycle is fixed at ~50%. The LT3579-1 is useful for
multiphase switching regulators.
SHDN (Pin 15/Pin 17): Shutdown Pin. In conjunction
with the UVLO (undervoltage lockout) circuit, this pin is
used to enable/disable the chip and restart the soft-start
sequence. Drive below 0.3V to disable the chip with very
low quiescent current. Drive above 1.33V (typical) to activate the chip and restart the soft-start sequence. Do not
float this pin.
RT (Pin 16/Pin 18): Timing Resistor Pin. Adjusts the
LT3579’s switching frequency. Place a resistor from this
pin to ground to set the frequency to a fixed free running
level. Do not float this pin.
SYNC (Pin 17/Pin 20): To synchronize the switching frequency to an outside clock, simply drive this pin with a
clock. The high voltage level of the clock must exceed
1.3V, and the low level must be less than 0.4V. Drive this
pin to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
SS (Pin 18/Pin 19): Soft-Start Pin. Place a soft-start
capacitor here. Upon start-up, the SS pin will be charged
by a (nominally) 250kΩ resistor to ~2.1V. During a fault,
the SS pin will be slowly charged up and discharged as
part of a timeout sequence.
VC (Pin 19/Pin 2): Error Amplifier Output Pin. Tie external
compensation network to this pin.
FB (Pin 20/Pin 1): Positive and Negative Feedback Pin.
For a Boost or Inverting Converter, tie a resistor from the
FB pin to VOUT according to the following equations:
– 1.215V ⎞
⎛V
R FB = ⎜ OUT
⎟⎠ ; Boost or SEPIC Converter
⎝
83.3µA
| +9mV ⎞
⎛|V
; Inverting Converter
R FB = ⎜ OUT
⎝ 83.3µA ⎟⎠
Rev. B
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7
LT3579/LT3579-1
BLOCK DIAGRAM
OPTIONAL
D1
L1
M1
VIN
CIN
COUT1
RFAULT
+
–
250k
SW1
+
–
SW2
+
–
ISW1
**
STARTUP
& FAULT
LOGIC
+
–
1.8V
+
–
**
SS
42V (MIN)
3.4A (MIN)
1.33V
+
–
SHDN
+
–
SW2
VBE • 0.9
Q2
SW1
COMPARATOR
R
A3
1.215V
REFERENCE
+
+
14.6k
Q1
Q
A4
–
RAMP
GENERATOR
+
14.6k
S
15.4m
DRIVER
+
∑
A1
–
FB
SR1
–
UVLO
VIN
45mV
TD ~ 30ns
DRIVER
DISABLE
CSS
1.17V
FB
42V (MIN)
–
+
+
–
750mV
+
–
2.1V
–
+
16.2V
DIE TEMP
VIN
165°C
–
+
933µA
VC
50mV
RGATE
FAULT
GATE
SOFTSTART
VOUT
COUT
FREQUENCY
FOLDBACK
A2
RS
12m
RFB
GND
÷N ADJUSTABLE
OSCILLATOR
SS
–
SYNC
BLOCK
VC
SYNC
RT
CLKOUT
RC
CC
RT
35791 BD
** SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3579/LT3579-1 DURING SW OVERVOLTAGE EVENTS.
Figure 1. Block Diagram
8
Rev. B
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LT3579/LT3579-1
STATE DIAGRAM
SHDN < 1.33V
OR
VIN < 2.3V
CHIP OFF
• ALL SWITCHES DISABLED
• IGATE OFF
• FAULTS CLEARED
SHDN > 1.33V
AND
VIN > 2.3V
INITIALIZE
• SS PULLED LOW
FAULT1
SS < 50mV
FAULT2
FAULT DETECTED
SOFT START
• IGATE ENABLED
• SS CHARGES UP
• SWITCHER ENABLED
FAULT1
• SS CHARGES UP
• IGATE OFF
• FAULT PULLED LOW INTERNALLY BY LT3579
• SWITCHER DISABLED
• CLKOUT DISABLED
SS > 1.8V
AND NO FAULT1
CONDITIONS STILL DETECTED
POST FAULT DELAY
• SS SLOWLY DISCHARGES
SAMPLE MODE
• Q1 & Q2 SWITCHES
FORCED ON EVERY CYCLE
FOR AT LEAST MINIMUM
ON-TIME
• IGATE FULLY ACTIVATED
WHEN SS > 500mV
FAULT1
FAULT1
SS < 50mV
LOCAL FAULT OVER
IF |VOUT| DROPS CAUSING:
FB < 1.17V (BOOST)
OR
FB > 45mV (INVERTING)
FAULT1 =
• INTERNAL FAULT PULLDOWN
RELEASED BY LT3579
• SS CONTINUES DISCHARGING
TO GND
NORMAL MODE
• NORMAL OPERATION
• CLKOUT ENABLED WHEN
SS > 1.8V
OVER VOLTAGE PROTECTION ON VIN (VIN > 16.2V (MIN))
OVER TEMPERATURE (TJUNCTION > 165°C (TYP))
OVER CURRENT ON SW1 (ISW1 > 3.4A (MIN))
OVER VOLTAGE PROTECTION ON SW1 (VSW1 > 42V (MIN))
OVER VOLTAGE PROTECTION ON SW1 (VSW2 > 42V (MIN))
FAULT1
FAULT > 1.0V
FAULT1
FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V)
35791 SD
Figure 2. State Diagram
Rev. B
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9
LT3579/LT3579-1
OPERATION
OPERATION – OVERVIEW
The LT3579 uses a constant-frequency, current mode
control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function,
together with soft-start and frequency foldback, offers a
controlled means of starting up. Fault features are incorporated in the LT3579 to aid in the detection of output
shorts, over-voltage, and overtemperature conditions.
Refer to the Block Diagram (Figure 1) and the State
Diagram (Figure 2) for the following description of the
part’s operation.
Several functions are provided to enable a very clean
start-up for the LT3579.
Precise Turn-On Voltage
The SHDN pin compares to an internal voltage reference to give a precise turn on voltage level. Taking the
SHDN pin above 1.33V (typical) enables the part. Taking
the SHDN pin below 0.3V shuts down the chip, resulting
in extremely low quiescent current. The SHDN pin has
30mV of hysteresis to protect against glitches and slow
ramping.
Undervoltage-Lockout (UVLO)
The SHDN pin can also be used to create a configurable
UVLO. The UVLO function sets the turn on/off of the
LT3579 at a desired input voltage (VINUVLO). Figure 3
shows how a resistor divider (or single resistor) from
VIN to the SHDN pin can be used to set VINUVLO. RUVLO2
is optional. It may be left out, in which case set it to infinite
in the equation below. For increased accuracy, set RUVLO2
≤ 10kΩ. Pick RUVLO1 as follows:
10
VINUVLO – 1.33V
⎛ 1.33V
⎜
⎜⎝ R UVLO2
⎞
⎟ + 11.6µA
⎟⎠
1.33V
RUVLO1
SHDN
–
ACTIVE/
LOCKOUT
+
11.6µA
AT 1.33V
RUVLO2
(OPTIONAL)
GND
35791 F03
Figure 3. Configurable UVLO
The LT3579 also has internal UVLO circuitry that disables
the chip when VIN < 2.3V (typical).
OPERATION – START-UP
R UVLO1 =
VIN
VIN
Soft-Start of Switch Current
The soft-start circuitry provides for a gradual ramp-up of
the switch current (refer to Commanded Switch Current
vs. SS in Typical Performance Characteristics). When the
part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic
circuits in the chip. Then an integrated 250k resistor pulls
the SS pin to ~1.8V at a ramp rate set by the external
capacitor connected to the pin. Once SS gets to 1.8V, the
CLKOUT pin is enabled, and an internal regulator pulls
the pin up quickly to ~2.1V. Typical values for the external
soft-start capacitor range from 100nF to 1μF.
Soft-Start of External PMOS (if used)
The soft-start circuitry also gradually ramps up the GATE
pin pull-down current which allows an external PMOS to
slowly turn on (M1 in Block Diagram). The GATE pin current increases linearly with SS voltage, with a maximum
current of 933µA when the SS voltage gets above 500mV.
Note that if the GATE pin voltage is less than 2V for SS
voltages exceeding 500mV, then the GATE pin impedance
to ground is 2kΩ. The soft turn on of the external PMOS
helps limit inrush current at start-up, making hot plugs
of the LT3579 feasible and safe.
Rev. B
For more information www.analog.com
LT3579/LT3579-1
OPERATION
Sample Mode
Sample Mode is the mechanism used by the LT3579 to
aid in the detection of output shorts. It refers to a state of
the LT3579 where the master and slave power switches
(Q1 and Q2) are turned on for a minimum period of time
every clock cycle (or every few clock cycles in frequency
foldback) in order to “sample” the inductor current. If the
sampled current through Q1 exceeds the master switch
current limit of 3.4A (minimum), the LT3579 triggers an
overcurrent fault internally (see Operation-Fault section
for details). Sample Mode exists when FB is out of regulation by more than 3.7% or 45mV < FB < 1.17V (typical).
The LT3579’s power switches are designed to handle a
total peak current of 6A (minimum).
Frequency Foldback
The frequency foldback circuit reduces the switching frequency when 350mV < FB < 900mV (typical). This feature
lowers the minimum duty cycle that the part can achieve,
thus allowing better control of the inductor current during start-up. When the FB voltage is pulled outside of this
range, the switching frequency returns to normal.
Note that the peak inductor current at start-up is a function
of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. Test the
application’s performance at start-up to ensure that the
peak inductor current does not exceed the minimum
current limit.
OPERATION – REGULATION
The following description of the LT3579’s operation
assumes the FB voltage is close enough to its regulation
target so that the part is not in Sample Mode. Use the
Block Diagram as a reference when stepping through the
following description of the LT3579 operating in regulation. At the start of each oscillator cycle, the SR latch
(SR1) is set, which turns on the power switches Q1 and
Q2. The collector current through the master switch,
Q1, is ~1.3 times the collector current through the slave
switch, Q2, when the collectors of the two switches are
tied together. Q1’s emitter current flows through a current
sense resistor (RS) generating a voltage proportional to
the total switch current. This voltage (amplified by A4) is
added to a stabilizing ramp and the resulting sum is fed
into the positive terminal of the PWM comparator A3.
When the voltage on the positive input of A3 exceeds the
voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage
on the negative input of A3 (VC pin) is set by A1 (or A2),
which is simply an amplified difference between the FB pin
voltage and the reference voltage (1.215V if the LT3579 is
configured as a boost converter, or 9mV if configured as
an inverting converter). In this manner, the error amplifier sets the correct peak current level to maintain output
regulation.
As long as the part is not in fault (see Operation – FAULT
section) and the SS pin exceeds 1.8V, the LT3579 drives
its CLKOUT pin at the frequency set by the RT pin or
the SYNC pin. The CLKOUT pin can synchronize other
compatible switching regulator ICs (including additional
LT3579s) with the LT3579. Additionally, the duty cycle
of CLKOUT varies linearly with the part’s junction temperature and may be used as a temperature monitor. The
CLKOUT signal on the LT3579-1 is ~180° out of phase
with the internal oscillator and has a fixed duty cycle of
~50%.
OPERATION – FAULT
The LT3579’s FAULT pin is an active low, bidirectional
pin (refer to Block Diagram) that pulls low to indicate a
fault. Each of the following events can trigger a fault in
the LT3579:
A. FAULT1 Events:
1. SW Overcurrent
a. ISW1 > 3.4A (minimum)
b. (ISW1 + ISW2) > 6A (minimum)
2. VIN Voltage > 16.2V (minimum)
3. SW1 Voltage and/or SW2 Voltage > 42V
(minimum)
4. Die Temperature > 165°C
B. FAULT2 Events:
1. Pulling the FAULT pin low externally
Rev. B
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11
LT3579/LT3579-1
OPERATION
When a fault is detected, in addition to the FAULT pin
being pulled low internally, the LT3579 also disables
its CLKOUT pin, turns off its power switches, and the
GATE pin becomes high impedance (refer to the State
Diagram). The external PMOS, M1, turns off when the
gate of M1 is pulled up to its source by the external
RGATE resistor (see Block Diagram) With the external
PMOS turned off, the power path from VIN to VOUT is
cut off, protecting power components downstream.
At the same time, a timeout sequence commences where
the SS pin is charged up to 1.8V (the SS pin will continue
charging up to ~2.1V and be held there in the case of a
FAULT1 event still existing), and then discharged to 50mV.
This timeout period relieves the part, the PMOS, and other
downstream power components from electrical and thermal stress for a minimum amount of time as set by the
voltage ramp rate on the SS pin.
In the absence of faults, the FAULT pin is pulled high by
the external RFAULT resistor (typically 100k). Figure 4 and
Figure 5 show the events that accompany the detection
of an output short on the LT3579.
12
VOUT
10V/DIV
CLKOUT
2V/DIV
IL
5A/DIV
FAULT
5V/DIV
10µs/DIV
35791 F04
Figure 4. Output Short Circuit Protection of the LT3579
SS
2V/DIV
GATE
5V/DIV
IL
5A/DIV
FAULT
5V/DIV
50ms/DIV
35791 F05
Figure 5. Continuous Output Short Showing FAULT Timeout Cycle
Rev. B
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LT3579/LT3579-1
APPLICATIONS INFORMATION
BOOST CONVERTER COMPONENT SELECTION
D1
30V, 4A
L1
2.2µH
VIN
5V
100k
200k
CIN
22µF
VIN
SW1 SW2
FAULT
Table 1. Boost Design Equations
PARAMETERS/EQUATIONS
OPTIONAL
M1
COUT1
10µF
RFB
130k
VOUT
12V
1.7A
RGATE
6.3k
COUT
10µF
FB
Step 1:
Inputs
Pick VIN, VOUT, and fOSC to calculate equations below.
Step 2:
DC
DC ≅
VIN
GATE
L TYP =
LT3579
SHDN
CLKOUT
RT
VC
SYNC GND
SS
RT
86.6k
CSS
0.1µF
CF
47pF
VOUT – VIN + 0.5V
VOUT + 0.5V – 0.27V
( VIN – 0.27V ) • DC
(1)
fOSC • 1.8A
( VIN – 0.27V ) • ( 2 • DC – 1)
4A • fOSC • ( 1 – DC )
( VIN – 0.27V ) • DC
=
L MIN =
RC
8k
CC
2.2nF
Step 3:
L1
L MAX
35791 F06
• The minimum of the L1 value range is the higher of LTYP
and LMIN.
• The maximum of the L1 value range is LMAX.
Step 4:
IRIPPLE
IRIPPLE =
( VIN – 0.27V ) • DC
fOSC • L1
Step 5:
IOUT
I
⎛
⎞
IOUT = ⎜ 6A – RIPPLE ⎟ • ( 1 – DC )
⎝
2 ⎠
Step 6:
D1
VR > VOUT ; I AVG > IOUT
Table 1 is a step-by-step set of equations to calculate
component values for the LT3579 when operating as a
Boost converter. Input parameters are input and output
voltage, and switching frequency (VIN , VOUT and fOSC
respectively). Refer to the Appendix for further information on the design equations presented in Table 1.
Step 7:
COUT,
COUT1
Variable Definitions:
Step 9:
RFB
VIN = Input Voltage
VOUT = Output Voltage
DC = Power Switch Duty Cycle
fOSC = Switching Frequency
IOUT = Maximum Output Current
IRIPPLE = Inductor Ripple Current
RDSON_PMOS = RDSON of External PMOS (set to 0 if not
using PMOS)
(3)
• Solve equations 1, 2, and 3 for a range of L1 values.
Figure 6. Boost Converter – The Component Values Given Are
Typical Values for a 1MHz, 5V to 12V Boost
The LT3579 can be configured as a Boost converter as
in Figure 6. This topology allows for positive output voltages that are higher than the input voltage. An external
PMOS (optional) driven by the GATE pin of the LT3579
can achieve input or output disconnect during a FAULT
event. A single feedback resistor sets the output voltage.
For output voltages higher than 40V, see the Charge Pump
topology in the Charge Pump Aided Regulators section.
fOSC • 0.5A
(2)
Step 8:
CIN
COUT =COUT1 =
IOUT • DC
fOSC • (0.01•VOUT –0.5•IOUT •RDSON_PMOS
)
CIN = CPWR + C VIN
CIN =
Step 10:
RT
IRIPPLE
8 • fOSC • 0.005 • VIN
+
6A • DC
40 • fOSC • 0.005 • VIN
V
– 1.215V
R FB = OUT
83.3µA
RT =
87.6
fOSC
– 1; fOSC in MHz and R T in kΩ
Only needed for input or output disconnect. See PMOS
Step 11:
Selection in the Appendix for information on sizing the PMOS
PMOS
and the biasing resistor, RGATE.
Note: The maximum design target for peak switch current is 6A and
is used in this table. The final values for COUT and CIN may deviate
from the above equations in order to obtain desired load transient
performance for a particular application.
Rev. B
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13
LT3579/LT3579-1
APPLICATIONS INFORMATION
SEPIC CONVERTER COMPONENT SELECTION –
COUPLED OR UNCOUPLED INDUCTORS
VPWR
9V TO 16V
C1
4.7µF
L1
6.8µH
CPWR
4.7µF
VIN
3.3V
TO 5V
VIN
L2
6.8µH
100k
FAULT
LT3579
SYNC
VOUT
12V
1.6A (VPWR >9V)
1.9A (VPWR >12V)
PARAMETERS/EQUATIONS
Step 1:
Inputs
Step 2: DC
COUT
10µF
×3
FB
GATE
DC ≅
VOUT + 0.5V
VIN + VOUT + 0.5V – 0.27V
( VIN – 0.27V ) • DC
fOSC • 1.8A
( VIN – 0.27V ) • ( 2 • DC – 1)
4A • fOSC • ( 1 – DC )
( VIN – 0.27V ) • DC
=
L MIN =
VC
GND
Pick VIN, VOUT, and fOSC to calculate equations below.
L TYP =
CLKOUT
RT
RT
86.6k
RFB
130k
SW1 SW2
SHDN
CVIN
4.7µF
D1
60V, 3A
Table 2. SEPIC Design Equations
CF
47pF
SS
CSS
0.22µF
RC
9.53k
Step 3: L
CC
2.2nF
L MAX
fOSC • 0.5A
(3)
• The minimum of the L value range is the higher of
LTYP and LMIN.
• The maximum of the L value range is LMAX.
Figure 7. SEPIC Converter – The Component Values Given Are
Typical Values for a 1MHz, 9V–16V to 12V SEPIC Topology Using
Coupled Inductors
The LT3579 can also be configured as a SEPIC as in
Figure 7. This topology allows for positive output voltages
that are lower, equal, or higher than the input voltage.
Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and
output due to capacitor C1. This implies that a PMOS controlled by the GATE pin is not required in the power path.
• L = L1 = L2 for coupled inductors.
• L = L1||L2 for uncoupled inductors.
Step 4:
IRIPPLE
IRIPPLE =
( VIN – 0.27V ) • DC
fOSC • L
Step 5: IOUT
I
⎛
⎞
IOUT = ⎜ 6A – RIPPLE ⎟ • ( 1 – DC )
⎝
2 ⎠
Step 6: D1
VR > VIN + VOUT ; I AVG > IOUT
Table 2 is a step-by-step set of equations to calculate
component values for the LT3579 when operating as a
SEPIC converter using coupled inductors. Input parameters are input and output voltage, and switching frequency
(VIN , VOUT and fOSC respectively). Refer to the Appendix
for further information on the design equations presented
in Table 2.
Step 7: C1
4.7µF (typical) ; VRATING > VIN
Variable Definitions:
14
(2)
• Solve equations 1, 2, and 3 for a range of L values.
35791 F07
VIN = Input Voltage
VOUT = Output Voltage
DC = Power Switch Duty Cycle
fOSC = Switching Frequency
IOUT = Maximum Output Current
IRIPPLE = Inductor Ripple Current
(1)
Step 8: COUT
COUT =
Step 9: CPWR
CPWR =
Step 10: CVIN
C VIN =
fOSC • 0.005 •VOUT
IRIPPLE
8 • fOSC • 0.005 • VIN
6A • DC
40 • fOSC • 0.005 • VIN
V
– 1.215V
R FB = OUT
83.3µA
Step 11: RFB
Step 12: RT
IOUT • DC
RT =
87.6
fOSC
– 1; fOSC in MHz and R T in kΩ
Note: The maximum design target for peak switch current is 6A and
is used in this table. The final values for COUT, CPWR, and CVIN may
deviate from the above equations in order to obtain desired load
transient performance for a particular application.
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPLICATIONS INFORMATION
DUAL INDUCTOR INVERTING CONVERTER COMPONENT
SELECTION – COUPLED OR UNCOUPLED INDUCTORS
C1
4.7µF
L1
3.3µH
VIN
5V
VIN
CIN
22µF
SW1 SW2
RFB
144k
FB
LT3579
100k
FAULT
RT
SYNC
RT
72k
Pick VIN, VOUT, and fOSC to calculate equations below.
DC ≅
Step 2: DC
L TYP =
| VOUT | + 0.5V
VIN + | VOUT | +0.5V – 0.27V
( VIN – 0.27V ) • DC
(1)
fOSC • 1.8A
( VIN – 0.27V ) • ( 2 • DC – 1)
4A • fOSC • ( 1 – DC )
( VIN – 0.27V ) • DC
=
L MIN =
CLKOUT
VC
GND
VOUT
–12V
1.2A
COUT
10µF
×2
GATE
SHDN
PARAMETERS/EQUATIONS
Step 1: Inputs
L2
3.3µH
D1
30V, 2A
Table 3. Dual Inductor Inverting Design Equations
SS
CSS
0.22µF
CF
27pF
RC
20k
CC
1nF
Step 3: L
• The minimum of the L value range is the higher of
LTYP and LMIN.
Figure 8. Dual Inductor Inverting Converter – The Component
Values Given Are Typical Values for a 1.2MHz, 5V to –12V
Inverting Topology Using Coupled Inductors
Table 3 is a step-by-step set of equations to calculate
component values for the LT3579 when operating as a
Dual Inductor Inverting converter using coupled inductors.
Input parameters are input and output voltage, and
switching frequency (VIN , VOUT and fOSC respectively).
Refer to the Appendix for further information on the
design equations presented in Table 3.
Variable Definitions:
VIN = Input Voltage
VOUT = Output Voltage
DC = Power Switch Duty Cycle
fOSC = Switching Frequency
IOUT = Maximum Output Current
IRIPPLE = Inductor Ripple Current
(3)
fOSC • 0.5A
• Solve equations 1, 2, and 3 for a range of L values.
35791 F08
Due to its unique FB pin, the LT3579 can work in a Dual
Inductor Inverting configuration as in Figure 8. Changing
the connections of L2 and the Schottky diode in the SEPIC
topology, results in generating negative output voltages.
This solution results in very low output voltage ripple due
to inductor L2 in series with the output. Output disconnect
is inherently built into this topology due to the capacitor
C1.
L MAX
(2)
• The maximum of the L value range is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1||L2 for uncoupled inductors.
IRIPPLE =
Step 4: IRIPPLE
( VIN – 0.27V ) • DC
fOSC • L
Step 5: IOUT
I
⎛
⎞
IOUT = ⎜ 6A – RIPPLE ⎟ • ( 1 – DC )
⎝
2 ⎠
Step 6: D1
VR > VIN + | VOUT | ; I AVG > IOUT
Step 7: C1
4.7µF (typical) ; VRATING > VIN + | VOUT |
C OUT =
Step 8: COUT
IRIPPLE
8 • fOSC • 0.005 • | VOUT |
CIN = CPWR + C VIN
Step 9: CIN
CIN =
IRIPPLE
8 • fOSC • 0.005 • VIN
R FB =
Step 10: RFB
Step 11: RT
RT =
87.6
fOSC
+
6A • DC
40 • fOSC • 0.005 • VIN
| VOUT | + 9mV
83.3µA
– 1; fOSC in MHz and R T in kΩ
Note: The maximum design target for peak switch current is 6A and
is used in this table. The final values for COUT and CIN may deviate
from the above equations in order to obtain desired load transient
performance for a particular application.
Rev. B
For more information www.analog.com
15
LT3579/LT3579-1
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
• Place the bypass capacitor for the inductor (CPWR) as
close as possible to the inductor.
General Layout Guidelines
• Bypass capacitors, CPWR and CVIN, may be combined
into a single bypass capacitor, CIN, if the input side of
the inductor can be close to the VIN pin of the LT3579.
• To optimize thermal performance, solder the exposed
ground pad of the LT3579 to the ground plane with
multiple vias around the pad connecting to additional
ground planes.
• A ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise.
• High speed switching path (see specific topology below
for more information) must be kept as short as possible.
• The VC , FB, and RT components should be placed as
close to the LT3579 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated
from the switch current path.
• Place the bypass capacitor for the VIN pin (CVIN) as
close as possible to the LT3579.
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path)
governing switch, diode D1, output capacitor COUT, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) governing
switch, flying capacitor C1, diode D1, output capacitor COUT,
and ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
21
1
CIN
A
–
VIN
+
20
SYNC
2
19
3
18
4
17
SHDN
5
16
CLKOUT
6
15
7
14
8
13
9
12
10
11
B
COUT1
–
COUT
VOUT
D1
L1
M1
+
D2
RGATE
35791 F08
A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND
WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE
COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
Figure 9. Suggested Component Placement for Boost Topology in FE20 Package
16
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Rev. B
LT3579/LT3579-1
APPLICATIONS INFORMATION
Inverting Topology Specific Layout Guidelines
the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the
underside of the IC. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into a copper plane with as much area
as possible.
• Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor COUT’s ground
return path (to chip) in order to minimize switching
noise coupling into the output. Notice the separate
ground return for D1’s cathode in Figure 11.
• Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic inductive spikes at the switch node during switching.
Power & Thermal Calculations
Power dissipation in the LT3579 chip comes from four
primary sources: switch I2R loss, NPN base drive loss
(AC), NPN base drive loss (DC), and additional VIN pin
current. These formulas assume continuous mode operation, so they should not be used for calculating thermal
losses or efficiency in discontinuous mode or at light
load currents.
THERMAL CONSIDERATIONS
For the LT3579 to deliver its full output power, it is imp
erative that a good thermal path be provided to dissipate
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
21
1
CIN
–
A
VIN
20
SYNC
2
19
3
18
4
17
SHDN
5
16
CLKOUT
6
15
7
14
8
13
9
12
10
11
B
–
COUT
+
C1
L1
L2
VOUT
D1
+
35791 F10
A– RETURN CIN AND L2 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2 –MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.
Figure 10. Suggested Component Placement for SEPIC Topology in FE20 Package
Rev. B
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17
LT3579/LT3579-1
APPLICATIONS INFORMATION
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
21
1
CIN
–
A
VIN
+
20
SYNC
2
19
3
18
4
17
SHDN
5
16
CLKOUT
6
15
7
14
8
13
9
12
10
11
B
C
GND
COUT
C1
D1
–VOUT
L1
L2
35791 F11
A– RETURN CIN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN COUT GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
C– RETURN D1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2 – MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.
Figure 11. Suggested Component Placement for Inverting Topology in FE20 Package.
Note Separate Ground Path for D1’s Cathode
18
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPLICATIONS INFORMATION
The following example calculates the power dissipation in the LT3579 for a particular boost application:
(VIN = 5V, VOUT = 12V, IOUT = 1.5A, fOSC = 1MHz,
VD = 0.5V, VCESAT = 0.185V).
where TJ=Die Junction Temperature, TA=Ambient
Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance
from the silicon junction to the ambient air.
To calculate die junction temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
TJ = TA + θJA • PTOTAL
Table 4. Boost Power Calculations Example with VIN = 5V, VOUT = 12V, IOUT = 1.5A, fOSC = 1MHz, VD = 0.5V, VCESAT = 0.185V
DEFINITION OF VARIABLES
DC = Switch Duty Cycle
IIN = Average Input Current
η = Power Conversion Efficiency
(typically 90% at high currents)
PSW = Switch I2R Loss
RSW = Switch Resistance (typically
45mΩ combined SW1 and SW2)
PBAC = Base Drive Loss (AC)
PBDC = Base Drive Loss (DC)
PINP = Input Power Loss
EQUATIONS
DC =
VOUT – VIN + VD
VOUT + VD – VCESAT
IIN =
VOUT • IOUT
VIN • η
2
DESIGN EXAMPLE
DC =
12V – 5V + 0.5V
IIN =
12V • 1.5A
2
PBAC = 13ns • IIN • VOUT • fOSC
PBAC = 13ns • 4A • 12V • 1MHz
PINP = 14mA • VIN
PBDC =
IIN = 4A
5V • 0.9
PSW = 0.609 • (4A) • 45mΩ
VIN • IIN • DC
40
DC = 60.9%
12V + 0.5V – .185V
PSW = DC • IIN • R SW
PBDC =
VALUE
5V • 4A • 0.609
PSW = 438mW
PBAC = 624mW
PBDC = 305mW
40
PINP = 14mA • 5V
PINP = 70mW
PTOTAL = 1.437W
Rev. B
For more information www.analog.com
19
LT3579/LT3579-1
APPLICATIONS INFORMATION
The published (http://www.linear.com/designtools/packaging/Linear_Technology_Thermal_Resistance_Table.pdf)
θJA value is 38°C/W for the TSSOP Exposed Pad package
and 34°C/W for the 4mm × 5mm QFN package. In practice,
lower θJA values are realizable if board layout is performed
with appropriate grounding (accounting for heat sinking
properties of the board) and other considerations listed in
the Layout Guidelines section. For instance, a θJA value of
~22°C/W was consistently achieved for both TSSOP and
QFN packages of the LT3579 (at VIN = 5V, VOUT = 12V,
IOUT = 1.7A, fOSC = 1MHz) when board layout was optimized
as per the suggestions in the Layout Guidelines section.
Junction Temperature Measurement
The duty cycle of the CLKOUT signal on the LT3579 is
linearly proportional to die junction temperature, TJ (the
CLKOUT duty cycle on the LT3579-1 is fixed at ~50%).
To get an accurate reading, measure the duty cycle of the
CLKOUT signal and use the following equation to approximate the junction temperature:
T = DC CLKOUT – 35%
J
0.3%
where DCCLKOUT is the CLKOUT duty cycle in % and TJ is
the die junction temperature in °C. Although the absolute
die temperature can deviate from the above equation by
±15°C, the relationship between change in CLKOUT duty
cycle and change in die temperature is well defined. A
3% increase in CLKOUT duty cycle corresponds to ~10°C
increase in die temperature:
Note that the CLKOUT pin is only meant to drive capacitive
loads up to 50pF.
Thermal Lockout
A fault condition occurs when the die temperature exceeds
~165°C (see Operation – FAULT Section), and the part
goes into thermal lockout. The fault condition ceases
when the die temperature drops by ~5°C (nominal).
SWITCHING FREQUENCY
There are several considerations in selecting the operating frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that case a 1.5MHz switching converter frequency may
be employed. The second consideration is the physical
size of the converter. As the operating frequency goes up,
the inductor and filter capacitors go down in value and
size. The trade-off is efficiency, since the switching losses
due to NPN base charge (see Thermal Considerations),
Schottky diode charge, and other capacitive loss terms
increase proportionally with frequency.
Oscillator Timing Resistor (RT)
The operating frequency of the LT3579 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
resistor from the RT pin to ground. An internally trimmed
timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula:
20
fOSC =
87.6
RT + 1
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPLICATIONS INFORMATION
where fOSC is in MHz and RT is in kΩ. Conversely, RT
(in kΩ) can be calculated from the desired frequency (in
MHz) using:
RT =
87.6
fOSC
–1
CLOCK SYNCHRONIZATION OF ADDITIONAL
REGULATORS
The CLKOUT pin of the LT3579 can synchronize additional
switching regulators and/or additional LT3579s as shown
in Figure 12.
VOUT
18V
1A
3.3µH
Clock Synchronization
10µF
An external source can set the operating frequency of the
LT3579 by providing a digital clock signal into the SYNC
pin (RT resistor still required). The LT3579 will operate at
the SYNC clock frequency. The LT3579 will revert to its
internal free-running oscillator clock when the SYNC pin
is driven below 0.4V for a few free-running clock periods.
Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1
from becoming set (see Block Diagram). As a result,
the switching operation of the LT3579 will stop and the
CLKOUT pin will be held at ground.
VIN
2. The SYNC frequency can always be higher than
the free-running oscillator frequency (as set by the
RT resistor), fOSC , but should not be less than 25%
below fOSC.
200k
CLKOUT
FAULT
SHDN
SYNC
RT
10µF
×2
FB
LT3579
SLAVE
4.7µF
VC
68pF
SS
GND
86.6k
0.1µF
8k
3.3nF
VOUT
12V
1.7A
2.2µH
VIN
5V
10µF
SW1 SW2
10k
The duty cycle of the SYNC signal must be between 20%
and 80% for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
1. SYNC may not toggle outside the frequency
range of 200kHz-2.5MHz unless it is stopped
below 0.4V to enable the free-running oscillator.
SW1 SW2
GATE
100k
110k
4.7µF
130k
GATE
CLKOUT
LT3579
VIN
FB
MASTER
VC
FAULT
47pF
SS
SHDN
RT
SYNC GND
86.6k
10µF
×3
8k
0.1µF
2.2nF
35791 F12
Figure 12. Synchronize Multiple LT3579s. The External PMOS
Disconnects the Input from Both Power Paths During FAULT
Events
Rev. B
For more information www.analog.com
21
LT3579/LT3579-1
APPLICATIONS INFORMATION
The frequency of the master LT3579 is set by the external
RT resistor. The SYNC pin of the slave LT3579 is driven
by the CLKOUT pin of the master LT3579. Note that the
RT pin of the slave LT3579 must have a resistor tied to
ground. It takes a few clock cycles for the CLKOUT signal
to begin oscillating, and it’s preferable for all LT3579s to
have the same internal free-running frequency. Therefore,
in general, use the same value RT resistor for all of the
synchronized LT3579s.
Also, the FAULT pins can be tied together so that a fault
condition from one LT3579 causes all of the LT3579s to
enter fault, until the fault condition disappears.
2-Phase Converters using LT3579-1
The CLKOUT pin on the LT3579-1 is ~180° out of phase
with the internal oscillator, which allows two LT3579-1s
to operate in parallel for a high current, high power output. The advantage of multiphase converters is that the
ripple current flowing into the output node is divided by
the number of phases or ICs used to generate the output
voltage. The VIN, SHDN, FAULT, FB, and VC pins of all
the LT3579-1s should be connected together. Figure 13
shows a typical application of a 2-phase 12V to 24V boost
with output disconnect.
4.7µH
4.7µF
×2
10µF
4.7µF
SW1 SW2
VIN
CLKOUT
FB
FAULT
LT3579-1
SLAVE
GATE
SHDN
VC
RT
SYNC GND
SS
0.22µF
86.6k
VOUT1
VPWR
12V
VIN
5V
4.7µH
10µF
VOUT1
500k
6.4k
4.7µF
×2
100k
21.5k
4.7µF
VIN
SW1 SW2
CLKOUT
86.6k
4.7µF
×2
137k
FB
FAULT
LT3579-1
MASTER
GATE
SHDN
VC
RT
SYNC GND
5k
VOUT
24V
3.7A,
89W
VPWR
47pF
SS
0.22µF
7k
2.2nF
35791 F13
Figure 13. 2-Phase Converters Using LT3579-1
Use the following equations to calculate the FB resistor
for 2-phase converters:
Note that the CLKOUT pin on the LT3579-1 runs at a fixed
duty cycle of ~50%. If monitoring the die temperature is
desired, the slave IC can be a LT3579.
⎛ VOUT – 1.215V ⎞
R FB = ⎜
; Boost or SEPIC
⎝ 2 • 83.3µA ⎟⎠
It is possible to use the LT3579-1 in a multiphase converter of more than 2 phases. Consult the LTC Applications
Engineering Department for more information.
⎛|V
Multiphase Converter
| + 9mV ⎞
R FB = ⎜ OUT
⎟⎠ ; Inverting Multiphase
2
•
83.3µA
⎝
Converter
22
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPLICATIONS INFORMATION
CHARGE PUMP AIDED REGULATORS
Single Inductor Inverting Topology
Designing charge pumps with the LT3579 can offer efficient solutions with fewer components than traditional
circuits because of the master/slave switch configuration on the IC. The current in the master switch (SW1) is
sensed by the current comparator (A4 in Block Diagram),
but the current in the slave switch (SW2) is not. Note
that the slave switch, SW2, operates in phase with SW1.
This method of operation by the master/slave switches
can offer the following benefits to charge pump designs:
If there is a need to use just 1 inductor to generate a
negative output voltage whose magnitude is greater than
VIN , the Single Inductor Inverting topology (shown in
Figure 15) can be used. Since the master and slave
switches are isolated by an external Schottky diode,
the current spike through C1 will flow through the slave
switch, thereby preventing the current comparator (A4 in
Block Diagram) from falsely tripping. Output disconnect is
inherently built into the single inductor topology.
• The slave switch, by not performing a current sense
operation like the master switch, can sustain fairly
large current spikes when the flying capacitors charge
up. Since this current spike flows through SW2, it
does not affect the operation of the current comparator
(A4 in Block Diagram).
• The master switch, immune from the capacitor current
spike, can sense the inductor current more accurately.
• Since the slave switch can sustain large current spikes,
the diodes that feed current into the flying capacitors
do not need current limiting resistors, leading to
efficiency and thermal improvements.
High VOUT Charge Pump Topology
The LT3579 can be used in a charge-pump topology (refer
to Figure 16), multiplying the output of an inductive boost
converter. The master switch (SW1) can be used to drive
the inductive boost converter, while the slave switch
(SW2) can be used to drive one or more charge pump
stages. This topology is useful for high voltage applications including VFD Bias Supplies.
HOT PLUG
The high inrush current associated with hot-plugging VIN
can be largely rejected with the use of an external PMOS.
A simple hot-plug controller can be designed by connecting an external PMOS in series with VIN, with the gate of
the PMOS being driven by the GATE pin of the LT3579.
Since the GATE pin pull-down current is linearly proportional to the SS voltage, and the SS charge up time is relatively slow, the GATE pin pull-down current will increase
gradually, thereby turning on the external PMOS slowly.
Controlled in this manner, the PMOS acts as an input
current limiter when VIN hot-plugs or ramps up sharply.
Likewise, when the PMOS is connected in series with
the output, inrush currents into the output capacitor can
be limited during a hot-plug event. To illustrate this, the
circuit in Figure 6 was re-configured by adding a large
1500µF capacitor to the output. An 18Ω resistive load was
used and a 2.2µF capacitor was placed on SS. Figure 14
shows the result of hot-plugging this re-configured circuit. The inductor current is well behaved and VOUT comes
up once VIN settles out.
Rev. B
For more information www.analog.com
23
LT3579/LT3579-1
APPLICATIONS INFORMATION
VIN
5V/DIV
VOUT
10V/DIV
IL
5A/DIV
SS
1V/DIV
35791 F14
1s/DIV
Figure 14. VIN Hot-Plug Control. Inrush Current is Well
Controlled
C1
D1
L1
VIN
D3
–VOUT
D2
VIN
SW1
RFB
SW2
SHDN
FB
COUT
GATE
LT3579
100k
FAULT
CIN
CLKOUT
VC
RT
SYNC GND
SS
RT
CF
RC
CC
CSS
35791 F15
Figure 15. Single Inductor Inverting Topology
4.7µF
VOUT2
100V
200mA
4.7µF
VOUT1
67V
100mA
4.7µF
4.7µF
10µH
VIN
12V
6.8µF
VIN
100k
SW1 SW2
FAULT
383k
6.8µF
6.5k
FB
GATE
VIN
LT3579
536k
SHDN
RT
10µF
SYNC
86.6k
CLKOUT
VC
GND
SS
27pF
2.2µF
34k
470pF
35791 F16
Figure 16. High VOUT Charge Pump Topology
24
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPENDIX
SETTING THE OUTPUT VOLTAGE
For the boost topology (see Figure 6):
The output voltage is set by connecting a resistor (RFB)
from VOUT to the FB pin. RFB is determined from the following equation:
|V
– VFB |
R FB = OUT
83.3µA
where VFB is 1.215V (typical) for non-inverting topologies
(i.e. boost and SEPIC regulators) and 9mV (typical) for
inverting topologies (see Electrical Characteristics).
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain “on” for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DCMAX =
( TP – MinOffTime ) • 100%
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain “off” for 100% of each clock
cycle, and will turn on for a minimum time (MinOnTime)
when in regulation. This MinOnTime governs the minimum allowable duty cycle given by:
VOUT – VIN + VD
VOUT + VD – VCESAT
For the SEPIC or Dual Inductor Inverting topology (see
Figure 7 and Figure 8):
DC SEPIC _& _INVERT ≅
VD + | VOUT |
VIN + | VD | + VOUT − VCESAT
For the Single Inductor Inverting topology (see Figure 14):
DC SI_INVERT ≅
| VOUT | − VIN + VCESAT + 3 • VD
| VOUT | + 3 • VD
The LT3579 can be used in configurations where the duty
cycle is higher than DCMAX , but it must be operated in
the discontinuous conduction mode so that the effective
duty cycle is reduced.
INDUCTOR SELECTION
TP
where TP is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 45nS.
DCMIN =
DCBOOST ≅
(MinOnTime ) • 100%
TP
where TP is the clock period and MinOnTime (found in the
Electrical Characteristics) is typically 55nS.
The application should be designed such that the operating duty cycle is between DCMIN and DCMAX.
Duty cycle equations for several common topologies are
given below where VD is the diode forward voltage drop
and VCESAT is typically 250mV at 5.5A for a combined
SW1 and SW2 current.
The high frequency operation of the LT3579 allows for the
use of small surface mount inductors. For high efficiency,
choose inductors with high frequency core material, such
as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given
inductance. The inductor should have low DCR (copperwire resistance) to reduce I2R losses, and must be able to
handle the peak inductor current without saturating. Note
that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC
topology where each inductor only carries one half of the
total switch current. Multilayer chokes or chip inductors
usually do not have enough core volume to support peak
inductor currents in the 4A to 7A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5
for a list of inductor manufacturers.
Rev. B
For more information www.analog.com
25
LT3579/LT3579-1
APPENDIX
where:
Table 5. Inductor Manufacturers
Vishay
IHLP-2020BZ-01 and
IHLP-2525CZ-01 Series
www.vishay.com
Coilcraft
XLP, MLC and MSS Series www.coilcraft.com
Cooper Bussmann DRQ125 and DRQ127
Series
www.cooperbussmann.
com
Sumida
www.sumida.com
CDRH series
TDK
RLF and SLF series
www.tdk.com
Würth
WE-PD, WE-PDF, WE-HC
and WE-DD Series
www.we-online.com
Minimum Inductance
Although there can be a trade-off with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance; (1) providing adequate load current, (2) avoidance of subharmonic
oscillation, and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator.
Adequate Load Current
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load. In
order to provide adequate load current, L should be at
least:
Boost
DC • ( VIN − VCESAT )
Topology
L BOOST >
⎛
VOUT • IOUT ⎞
2 • fOSC • ⎜ IPK −
VIN • η ⎟⎠
⎝
or
L DUAL >
26
DC • ( VIN − VCESAT )
SEPIC
or
Inverting
⎞ Topologies
⎛
|VOUT |•IOUT
2 • fOSC • ⎜ IPK −
− IOUT ⎟
VIN • η
⎝
⎠
LBOOST = L1 for Boost Topologies (see Figure 6)
LDUAL = L1 = L2 for Coupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
LDUAL = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
DC = Switch Duty Cycle (see Power Switch Duty
Cycle section in Appendix)
IPK
= Maximum Peak Switch Current; Should
Not Exceed 6A for a Combined SW1 +
SW2 Current or 3.4A of SW1 Current (see
Electrical Characteristics section.)
η
= Power Conversion Efficiency (typically 90%
for Boost and 85% for Dual Inductor
Topologies at high currents)
fOSC = Switching Frequency
IOUT = Maximum Output Current
Negative values of LBOOST or LDUAL indicate that the output load current, IOUT, exceeds the switch current limit
capability of the LT3579.
Avoiding Sub-Harmonic Oscillations
The LT3579’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the
duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance
must be at least:
L MIN =
( VIN − VCESAT ) • ( 2 • DC − 1)
where:
4A • fOSC • ( 1− DC )
LMIN = L1 for Boost Topologies (see Figure 6)
LMIN = L1 = L2 for Coupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
LMIN = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPENDIX
Maximum Inductance
DIODE SELECTION
Excessive inductance can reduce ripple current to levels
that are difficult for the current comparator (A4 in the
Block Diagram) to cleanly discriminate, thus causing duty
cycle jitter and/or poor regulation. The maximum inductance can be calculated by:
Schottky diodes, with their low forward voltage drops and
fast switching speeds, are recommended for use with the
LT3579. Choose a Schottky with low parasitic capacitance
to reduce reverse current spikes through the power switch
of the LT3579. The Diodes Inc. MBRM360 is a very good
choice with a 60V reverse voltage rating and an average
forward current of 3A.
L MAX =
where:
( VIN − VCESAT ) • DC
fOSC • 0.5A
OUTPUT CAPACITOR SELECTION
LMAX = L1 for Boost Topologies (see Figure 6)
LMAX = L1 = L2 for Coupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
LMAX = L1 || L2 for Uncoupled Dual Inductor
Topologies (see Figure 7 and Figure 8)
Inductor Current Rating
The inductor(s) must have a rating greater than its (their)
peak operating current to prevent inductor saturation,
which would result in catastrophic failure and efficiency
losses. The maximum inductor current (considering startup and steady-state conditions) is given by:
IL _ PEAK = ILIM +
where:
VIN • TMIN _ PROP
L
IL_PEAK = Peak Inductor Current in L1 for a Boost
Topology, or the sum of the Peak
Inductor Currents in L1 and L2 for Dual
Inductor Topologies.
ILIM
= For Hard-Saturation Inductors, 9.4A with
SW1 and SW2 Tied Together, or 5.1A
with just SW1 used. For Soft-Saturation
Inductors, 6A with SW1 and SW2 Tied
Together, or 3.4A with just SW1 used.
TMIN_PROP = 100ns (Propagation Delay through the
Current Feedback Loop).
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads, provided
the SS capacitor is sized appropriately to limit inductor
currents at start-up.
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice,
as they have an extremely low ESR and are available in
very small packages. X5R or X7R type are preferred, as
these materials retain their capacitance over wide voltage
and temperature ranges. A 22μF to 47μF output capacitor
is sufficient for most applications, but systems with low
output currents may need only 4.7μF to 22μF. Always use
a capacitor with a sufficient voltage rating. Many ceramic
capacitors, particularly 0805 or 0603 case sizes, have
greatly reduced capacitance at the desired output voltage.
Tantalum polymer or OS-CON capacitors can be used, but
it is likely that these capacitors will occupy more board
area than a ceramic, and will have higher ESR with greater
output ripple.
INPUT CAPACITOR SELECTION
Ceramic capacitors make a good choice for the input
decoupling capacitor, CVIN, which should be placed as
close as possible to the VIN pin of the LT3579. This
ensures that the voltage seen at the VIN pin of the LT3579
remains a nearly flat DC voltage. A 1μF to 4.7μF input
capacitor is sufficient for most applications.
A ceramic bypass capacitor, CPWR, should also be placed
as close as possible to the input of the inductor. This
ensures that the inductor ripple current is supplied from
the bypass capacitor and provides a nearly flat DC voltage to the input of the voltage converter. A 4.7µF to 10µF
input power capacitor is sufficient for most applications.
Rev. B
For more information www.analog.com
27
LT3579/LT3579-1
APPENDIX
Table 6 shows a list of several ceramic capacitor man
ufacturers. Consult the manufacturers for detailed infor
mation on their entire selection of ceramic parts.
the relationship between RGATE (see Block Diagram) and
the desired VSG that the PMOS is biased with:
Table 6. Ceramic Capacitor Manufacturers
TDK
www.tdk.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
PMOS SELECTION
An external PMOS, controlled by the LT3579’s GATE pin,
can be used to facilitate input or output disconnect. The
GATE pin turns on the PMOS gradually during start-up
(see Soft-Start of External PMOS in the Operation section), and turns the PMOS off when the LT3579 is in
shutdown or in fault.
The use of the external PMOS, controlled by the GATE pin,
is particularly beneficial when dealing with unintended
output shorts in a boost regulator. In a conventional
boost regulator, the inductor, Schottky diode, and power
switches are susceptible to damage in the event of an
output short to ground. Using an external PMOS in the
boost regulator’s power path (path from VIN to VOUT) controlled by the GATE pin, will serve to disconnect the input
from the output when the output has a short to ground,
thereby helping save the IC, and the other components in
the power path from damage.
The PMOS chosen must be capable of handling the maximum input or output current depending on whether the
PMOS is used at the input (see Figure 12) or the output
(see Figure 13).
Ensure that the PMOS is biased with enough source to
gate voltage (VSG) to enhance the device into the triode
mode of operation. The higher the VSG voltage that biases
the PMOS, the lower the RDSON of the PMOS, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application
in which the PMOS is used. The following equations show
28
⎧
R GATE
if VGATE < 2V
⎪ VS
R GATE + 2kΩ
VSG = ⎨
⎪
933µA • R GATE if VGATE > 2V
⎩
When using a PMOS, it is advisable to configure the
specific application for undervoltage lockout (see the
Operation section). The goal is to have VIN get to a certain
minimum voltage where the PMOS has sufficient headroom to attain a high enough VSG, which prevents it from
entering the saturation mode of operation during start-up.
Figure 6 shows the PMOS connected in series with the
output to act as an output disconnect during a fault condition. The Schottky diode from the VIN pin to the GATE
pin is optional and helps turn off the PMOS quicker in the
event of hard shorts. The resistor from VIN to the SHDN
pin sets a UVLO of 4V for this application.
Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input:
• Since the load current is always less than the input
current for a boost converter, the current rating of the
PMOS goes down when connected in series with the
output as opposed to the input.
• A PMOS in series with the output can be biased with
a higher overdrive voltage than a PMOS used in series
with the input, since VOUT > VIN. This higher overdrive
results in a lower RDSON for the PMOS, thereby improving the efficiency of the regulator.
In contrast, an input connected PMOS works as a simple
hot-plug controller (covered in more detail in the Hot-Plug
section). The input connected PMOS also functions as an
inexpensive means of protecting against multiple output
shorts in boost applications that synchronize the LT3579
with other compatible ICs (see Figure 12).
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPENDIX
Table 7 shows a list of several discrete PMOS manufa
cturers. Consult the manufacturers for detailed information
on their entire selection of PMOS devices.
VOUT
500mV/DIV
AC COUPLED
IL
2A/DIV
Table 7. Discrete PMOS Manufacturers
Vishay
www.vishay.com
Fairchild Semiconductor
www.fairchildsemi.com
Central Semiconductor
www.centralsemi.com
ILOAD
1A/DIV
RC = 1k
COMPENSATION – ADJUSTMENT
100µs/DIV
35791 F17a
Figure 17a. Transient Response Shows Excessive Ringing
To compensate the feedback loop of the LT3579, a series
resistor-capacitor network in parallel with an optional
single capacitor must be connected from the VC pin to
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 2.2nF being a good starting
value. The optional parallel capacitor should range in value
from 22pF to 180pF with 47pF being a good starting value.
The compensation resistor, RC , is usually in the range of
5k to 50k. A good technique to compensate a new application is to use a 100kΩ potentiometer in place of the
series resistor RC. With the series and parallel capacitors
at 2.2nF and 47pF respectively, adjust the potentiometer
while observing the transient response and the optimum
value for RC can be found. Figure 17a to Figure 17c illustrate this process for the circuit of Figure 20 with a load
current stepped between 0.7A and 1.5A. Figure 17a shows
the transient response with RC equal to 1k. The phase
margin is poor as evidenced by the excessive ringing in
the output voltage and inductor current. In Figure 17b, the
value of RC is increased to 3.5k, which results in a more
damped response. Figure 17c shows the results when RC
is increased further to 8k. The transient response is nicely
damped and the compensation procedure is complete.
VOUT
500mV/DIV
AC COUPLED
IL
2A/DIV
ILOAD
1A/DIV
RC = 3.5k
100µs/DIV
35791 F17b
Figure 17b. Transient Response Is Better
VOUT
500mV/DIV
AC COUPLED
IL
2A/DIV
ILOAD
1A/DIV
RC = 8k
100µs/DIV
35791 F17c
Figure 17c. Transient Response Is Well Damped
COMPENSATION – THEORY
Like all other current mode switching regulators, the
LT3579 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT3579: a
fast current loop which does not require compensation,
and a slower voltage loop which does. Standard Bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
Rev. B
For more information www.analog.com
29
LT3579/LT3579-1
APPENDIX
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 18 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the IC, inductor and diode have been replaced
by a combination of the equivalent transconductance
amplifier gmp and the current controlled current source
(which converts IVIN to ηVIN I ). Gmp acts as a current
VOUT
VIN
source where the peak input current, IVIN, is proportional
to the VC voltage.
DC Gain:
gmp
Output Pole: P1 =
IVIN
η • VIN
• IVIN
RESR
RL
Error Amp Pole: P2 =
ESR Zero: Z2 =
COUT
+
gma
RC
RO
CC
1.215V
REFERENCE
CPL
RHP Zero: Z3 =
R1
1
2• π • (RO + RC ) • CC
1
2• π •RC • CC
1
2• π •RESR • COUT
VIN 2•RL
2• π • VOUT 2•L
f
High Frequency Pole: P3 > S
3
R2
FB
–
VIN
2• π •RL • COUT
VOUT
VOUT
CF
R
0.5R 2
• L•
VOUT 2 R1 + 0.5R 2
2
A DC = gma •RO • gmp • η•
Error Amp Zero: Z1 =
–
+
From Figure 18, the DC gain, poles and zeros can be
calculated as follows:
R2
35791 F18
CC: COMPENSATION CAPACITOR
COUT: OUTPUT CAPACITOR
CPL: PHASE LEAD CAPACITOR
CF: HIGH FREQUENCY FILTER CAPACITOR
gma: TRANSCONDUCTOR AMPLIFIER INSIDE IC
gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
RC: COMPENSATION RESISTOR
RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOADMAX
RO: OUTPUT RESISTANCE OF gma
R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK
RESR: OUTPUT CAPACITOR ESR
η: CONVERTER EFFICIENCY (~90% AT HIGHER CURRENTS)
Figure 18. Boost Converter Equivalent Model
Phase Lead Zero: Z4 =
1
2• π •R1 • CPL
Phase Lead Pole: P4 =
2• π •
1
R1 • 0.5R 2
R1 + 0.5R 2
• CPL
Error Amp Filter Pole:
P5 =
1
R •R
2• π • C O CF
RC + RO
C
, CF < C
10
Note that the maximum output currents of gmp and gma are
finite. The output of the gmp stage is limited by the minimum switch current limit (see Electrical Specifications)
and gma is nominally limited to about ±12μA.
30
Rev. B
For more information www.analog.com
LT3579/LT3579-1
APPENDIX
The current mode zero (Z3) is a right half plane zero which
can be an issue in feedback control design, but is manageable with proper external component selection.
140
COMMENT
RL
7
Ω
Application Specific
COUT
30
µF
Application Specific
RESR
2
mΩ
Application Specific
R0
305
kΩ
Not Adjustable
CC
2200
pF
Adjustable
CF
47
pF
Optional/Adjustable
CPL
0
pF
Optional/Adjustable
RC
8
kΩ
Adjustable
R1
130
kΩ
Adjustable
R2
14.6
kΩ
Not Adjustable
VOUT
12
V
Application Specific
VIN
5
V
Application Specific
gma
250
µmho
Not Adjustable
gmp
28
mho
Not Adjustable
L
2.2
µH
Application Specific
fOSC
1.0
MHz
Adjustable
–90
–135
GAIN (dB)
80
60
–180
40
46° AT
8kHz
GAIN
–225
20
–270
0
–315
–20
10
1k
100
PHASE (DEG)
UNITS
PHASE
100
Table 8. Bode Plot Parameters
VALUE
–45
120
Using the circuit in Figure 20 as an example, Table 8
shows the parameters used to generate the Bode plot
shown in Figure 19.
PARAMETER
0
–360
1M
10k
100k
FREQUENCY (Hz)
35791 F19
Figure 19. Bode Plot for Example Boost Converter
L1
2.2µH
VIN
5V
D1
130k
SW1 SW2
100k
CIN
22µF
From Figure 19, the phase is –134° when the gain reaches
0dB giving a phase margin of 46°. The crossover frequency is 8kHz, which is more than three times lower
than the frequency of the RHP zero Z3 to achieve adequate
phase margin.
VIN
FAULT
SHDN
LT3579
FB
COUT
10µF
×3
GATE
CLKOUT
RT
SYNC GND
86.6k
VOUT
12V
1.7A
VC
SS
47pF
0.1µF
8k
2.2nF
35791 F20
Figure 20. 5V to 12V Boost Converter
Rev. B
For more information www.analog.com
31
LT3579/LT3579-1
TYPICAL APPLICATION
1MHz, 5V to 12V Boost Converter can Survive Output Shorts
L1
2.2µH
VIN
5V
D1
VOUT
12V
1.7A
M1
COUT1
10µF
VIN
100k
FAULT
200k
SHDN
CIN
22µF
130k
SW1 SW2
RT
SYNC
LT3579
COUT
10µF
6.3k
FB
D2
VIN
GATE
CLKOUT
VC
GND
86.6k
SS
47pF
8k
0.1µF
2.2nF
35791 TA03a
CIN: 22µF, 16V, X7R, 1210
COUT1, COUT: 10µF, 25V, X7R, 1210
D1: VISHAY SSB43L
D2: CENTRAL SEMI CMDSH-3TR
L1: WÜRTH WE-PD 744771002
M1: SILICONIX SI7123DN
100
3.2
90
2.8
80
2.4
70
2
60
1.6
50
1.2
40
0.8
30
0.4
20
0
0.25 0.5 0.75 1 1.25 1.5 1.75
LOAD CURRENT (A)
2
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
0
35791 TA03
Output Short
Transient Response with 0.7A to 1.5A to 0.7A Output Load Step
VOUT
10V/DIV
VOUT
500mV/DIV
AC COUPLED
CLKOUT
2V/DIV
IL
2A/DIV
IL
2A/DIV
ILOAD
1A/DIV
FAULT
5V/DIV
10µs/DIV
32
35791 TA05
100µs/DIV
35791 TA06
Rev. B
For more information www.analog.com
LT3579/LT3579-1
TYPICAL APPLICATION
500kHz SEPIC Converter Generates 3.3V from a 3V to 33V Input
D3
VBAT
3V TO 33V (OPERATING)
6V TO 16V (START-UP)
•
C2
4.7µF
L1
3.3µH
CPWR
4.7µF
×2
D4
L2
3.3µH
10k
200k
4.7nF
M1
VIN
D1
15V
SHDN
100k
CVIN
10µF
174k
COUT
47µF
×6
FAULT
LT3579
GATE
VC
100pF
RT
CLKOUT
SYNC GND SS
10k
0.22µF
90
4
80
3.5
70
3
2.5
VBAT = 12V
2
40
1.5
30
1
20
0.5
10
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
3.5
4.7nF
Transient Response with 9V to 33V to 9V VBAT Glitch (RLOAD = 1.5Ω)
4
VOUT
2V/DIV
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
8.25k
35791 TA07a
C1: 10nF, 16V, X7R, 0603
CVIN: 10µF, 16V, X7R, 1206
CPWR, C2: 4.7µF, 50V, X7R, 1210
COUT: 47µF, 6.3V, X7R, 1210
D1: CENTRAL SEMI CMHZ5245B-LTZ
D2: VISHAY SS5P6
D3: CENTRAL SEMI CMMSH2-40
D4: CENTRAL SEMI CMMSH2-40
L1, L2: WÜRTH WE-DD 744870003
M1: 2N7002
Q1: MMBT3904
VBAT = 3V
24.9k
FB
Q1
50
•
SW1 SW2
C1
10nF
60
VOUT
3.3V
1.8A (VBAT = 3V)
3.1A (VBAT = 9V)
3.4A (VBAT ≥ 12V)
D2
VBAT
10V/DIV
IL1 + IL2
1A/DIV
50ms/DIV
35791 TA08b
0
35791 TA08a
Rev. B
For more information www.analog.com
33
LT3579/LT3579-1
TYPICAL APPLICATION
1.2MHz, 5V to -12V Inverting Converter
C1
4.7µF
L1
3.3µH
VIN
5V
L2
3.3µH
D1
SW1 SW2
VIN
SHDN
100k
FAULT
CIN
22µF
FB
LT3579
GATE
COUT
10µF
×2
CLKOUT
RT
SYNC GND
71.5k
143k
VOUT
–12V
1.2A
VC
SS
27pF
20k
1nF
0.22µF
35791 TA14
CIN: 22µF, 16V, X7R, 1210
C1: 4.7µF, 25V, X7R, 1206
COUT: 10µF, 25V, X7R, 1210
D1: DIODES INC B230A
L1, L2: COOPER BUSSMANN DRQ125-3R3-R
Transient Response with 0.5A to 1A to 0.5A Output Load Step
100
3.2
90
2.8
80
2.4
70
2
60
1.6
50
1.2
40
0.8
30
0.4
20
0
0.25
0.5
0.75
LOAD CURRENT (A)
1
VOUT
500mV/DIV
AC COUPLED
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
IL1 + IL2
1A/DIV
ILOAD
1A/DIV
100µs/DIV
35791 TA16
0
1.25
35791 TA15
34
Rev. B
For more information www.analog.com
LT3579/LT3579-1
TYPICAL APPLICATION
VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz
Danger High Voltage! Operation by High Voltage Trained Personnel Only
D6
C6
2.2µF
×2
D5
C4
2.2µF
×2
VOUT1
67V
C5
500mA*
2.2µF
×2
D4
D3
C3
2.2µF
×2
D2
L1
10µH
VIN
9V TO 16V
VOUT2
100V
330mA*
D1
M1**
C1
2.2µF
×3
D9**
VIN
100k
SW1 SW2
FAULT
536k
LT3579
6.5k**
FB
D7**
C2
2.2µF
×3
VIN
GATE
CLKOUT
VC
SHDN
CIN
10µF
383k
D8**
8.2V
RT
SYNC
GND
SS
86.6k
27pF
2.2µF
34k
470pF
35791 TA17
CIN: 10µF, 25V, X7R, 1210
C1-C6: 2.2µF, 50V, X7R, 1210
D1-D6: DIODES INC SBR2A40P1
D7: CENTRAL SEMI CMDSH-3TR
D8: CENTRAL SEMI CMDZ5237B-LTZ
D9: DIODES INC MBRM360
L1: WÜRTH WE-PD 7447710
M1: SILICONIX SI7461DP
*MAX TOTAL
OUTPUT POWER
22W (VIN = 9V)
27W (VIN = 12V)
33W (VIN = 16V)
**OPTIONAL FOR OUTPUT
SHORT CIRCUIT PROTECTION
90
5
85
4
80
3
75
2
70
1
Cycle-to-Cycle
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss (VIN = 12V)
VOUT1
2V/DIV
AC COUPLED
VOUT2
2V/DIV
AC COUPLED
IL
1A/DIV
SW1
20V/DIV
1µs/DIV
65
0
5
10
20
25
15
TOTAL OUTPUT POWER (W)
35791 TA19
0
30
35791 TA18
Rev. B
For more information www.analog.com
35
LT3579/LT3579-1
TYPICAL APPLICATION
1MHz, 5V to ±12V Converter
C2
4.7µF
D5
D4
L1
4.7µH
VIN
5V
C1
4.7µF
D1
R1**
1.2k
D3
D2
SW1
VIN
SHDN
100k
FAULT
CIN
10µF
RT
SYNC
SW2
LT3579
VOUT 2
–12V
COUT 2 0.8A*
10µF
×2
VOUT1
12V
0.8A*
130k
COUT1
10µF
×2
FB
GATE
CLKOUT
VC
GND
SS
86.6k
27pF
0.1µF
34k
1nF
35791 TA20
CIN: 10µF, 16V, X7R, 1206
C1, C2: 4.7µF, 25V, X7R, 1206
COUT1, COUT2: 10µF, 25V, X7R, 1210
D1-D5: DIODES INC SBR2A40P1
L1: VISHAY IHLP-2525CZ-01-4R7
R1: 1.2k, 2W
*MAX TOTAL OUTPUT POWER = 9.6W
**IF DRIVING ASYMMETRICAL LOADS, PLACE A 1.2k, 2W
RESISTOR FROM THE +12V OUTPUT TO THE –12V OUTPUT FOR
IMPROVED LOAD REGULATION OF THE –12V OUTPUT.
Transient Response with 0.15A to 0.35A to 0.15A
Symmetrical Output Load Step
90
3
85
2.7
80
2.4
75
2.1
70
1.8
65
1.5
60
1.2
55
0.9
50
0.6
45
0.3
40
0
100
200
400
300
LOAD CURRENT (mA)
VOUT1
500mV/DIV
AC COUPLED
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
VOUT2
500mV/DIV
AC COUPLED
0
500
IL
1A/DIV
100µs/DIV
35791 TA22
35791 TA21
36
Rev. B
For more information www.analog.com
LT3579/LT3579-1
TYPICAL APPLICATION
1MHz, 2-Phase Converter Generates a 24V Output from a 8V to 16V Input and Uses Small Components
L2
4.7µH
D2
COUT1S
4.7µF
×2
CPWR2
10µF
SW1 SW2
VIN
CLKOUT
FB
FAULT
LT3579-1
SLAVE
GATE
SHDN
VC
RT
CVIN2
4.7µF
SYNC GND
SS
0.22µF
86.6k
L1
4.7µH
VPWR
8V TO 16V
VIN
3.3V TO VPWR
D1
6.4k**
COUT1M
4.7µF
×2
CPWR1
10µF
VOUT1
500k
VIN
100k
SW1 SW2
CLKOUT
FB
FAULT
LT3579-1
MASTER
GATE
SHDN
VC
RT
21.5k
CVIN1
4.7µF
SYNC GND
5k
86.6k
VOUT
24V
5.1A*
M1**
VOUT1
COUT
4.7µF
×2
137k
D3**
VPWR
47pF
SS
0.22µF
7k
2.2nF
35791 TA23
CPWR1, CPWR2: 10µF, 25V, X7R, 1210
CVIN1, CVIN2: 4.7µF, 25V, X7R, 1206
COUT1M, COUT1S, COUT: 4.7µF, 50V, X5R, 1210
D1, D2: CENTRAL SEMI CTLSH5-40M833
D3: CENTRAL SEMI CTLSH1-40M563
L1, L2: VISHAY IHLP-2525CZ-01-4R7
M1: SILICONIX SI7461DP
100
8
90
7
80
6
VIN = 12V
70
60
5
4
VIN = 3.3V
50
3
40
2
30
1
20
0
4.5
0
0.5
1
1.5 2 2.5 3 3.5
LOAD CURRENT (A)
4
VPWR = 8V
VPWR = 12V
VPWR = 16V
VIN = 3.3V TO 5V
2.4A
3.7A
5.1A
VIN = VPWR
2.2A
3.1A
3.9A
**OPTIONAL FOR OUTPUT SHORT CIRCUIT PROTECTION
Transient Response with 1.5A to 3.25A to 1.5A
Output Load Step (VPWR = 12V and VIN = 3.3V)
VOUT
1V/DIV
AC COUPLED
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss (VPWR = 12V)
*MAX OUTPUT CURRENT
IL1 + IL2
5A/DIV
ILOAD
1A/DIV
100µs/DIV
35791 TA25
35791 TA24
Rev. B
For more information www.analog.com
37
LT3579/LT3579-1
TYPICAL APPLICATION
2MHz, Boost Converter with Output Disconnect Generates a 5V Output from 2.8V to 4.2V Input
L1
0.47µH
VIN
2.8V TO 4.2V
D1
VOUT
5V
2A
M1
COUT1
22µF
VIN
SW1 SW2
SHDN
43.5k
10k
FB
GATE
LT3579
100k
COUT
22µF
CLKOUT
FAULT
VC
RT
SYNC GND
SS
CIN
10µF
43.2k
47pF
6.34k
22nF
2.2nF
35791 TA26
CIN: 10µF, 16V, X7R, 1206
COUT1, COUT: 22µF, 16V, X7R, 1210
D1: CENTRAL SEMI CTLSH3-30M833
L1: VISHAY IHLP-2020BZ-01-R47
M1: SILICONIX SI7123DN
Transient Response with 0.8A to 1.8A to 0.8A
Output Load Step (VIN = 3.3V)
2.4
90
2.1
80
1.8
70
1.5
60
1.2
VIN = 3.3V
50
0.9
40
0.6
30
0.3
20
0
0.5
1
1.5
LOAD CURRENT (A)
2
POWER LOSS (W)
EFFICIENCY (%)
Efficiency and Power Loss
100
VOUT
200mV/DIV
AC COUPLED
IL
1A/DIV
ILOAD
1A/DIV
100µs/DIV
0
2.5
35791 TA28
35791 TA27
38
Rev. B
For more information www.analog.com
LT3579/LT3579-1
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation CB
DETAIL A
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
0.60
(.024)
REF
0.28
(.011)
REF
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
DETAIL A
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV L 0117
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev. B
For more information www.analog.com
39
LT3579/LT3579-1
PACKAGE DESCRIPTION
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 ±0.05
4.50 ±0.05
1.50 REF
3.10 ±0.05
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
1.50 REF
R = 0.05 TYP
19
20
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
2.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD20) QFN 0506 REV B
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
40
Rev. B
For more information www.analog.com
LT3579/LT3579-1
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/14
Clarified Electrical Specifications
4
Clarified Table 1
13
Clarified Table 2
14
Clarified Table 3
15
B
10/18
PAGE NUMBER
Clarified Table 8
30
Added Note 5 to Switch VCESAT parameter and notes section
3, 4
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
41
LT3579/LT3579-1
TYPICAL APPLICATION
Efficiency and Power Loss
VPWR
9V TO 16V
C1
4.7µF
L1
6.8µH
•
L2
6.8µH
SW1
VIN
SHDN
100k
CVIN
4.7µF
•
SW2
VIN
3.3V TO VPWR
130k
COUT
10µF
×3
FB
LT3579
GATE
CLKOUT
FAULT
RT
VC
SYNC GND SS
86.6k
VOUT
12V
1.9A*
0.22µF
100
3.2
90
2.8
80
2.4
70
2
60
50
1.2
40
0.8
30
0.4
20
47pF
1.6
VPWR = 12V
VIN = 5V
9.53k
2.2nF
0
0.25 0.5 0.75 1 1.25 1.5 1.75
LOAD CURRENT (A)
2
POWER LOSS (W)
CPWR
4.7µF
D1
EFFICIENCY (%)
1MHz SEPIC Converter Generates a 12V Output from
a 9V to 16V Input
0
35791 TA30
35791 TA29
CPWR: 4.7µF, 25V, X7R, 1206
*MAX OUTPUT CURRENT
CVIN: 4.7µF, 25V, X7R, 1206
VPWR = 9V VPWR = 12V
C1: 4.7µF, 25V, X7R, 1206
COUT: 10µF, 25V, X7R, 1210
1.6A
1.9A
VIN = 3.3V TO 5V
D1: DIODES INC MBRM360
=
V
1.4A
1.4A
V
L1, L2: COOPER BUSSMANN DRQ125-6R8-R IN PWR
LINE REGULATION (VIN = 5V, IOUT = 1A) = 0.017%/V
LOAD REGULATION (VPWR = 12V, VIN = 5V) = –0.23%/A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3581
3.3A (ISW), 42V, 2.5MHz, High Efficiency
Step-Up DC/DC Converter
VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = < 1µA, 4mm × 3mm DFN-14,
MSOP-16E
LT3580
2A (ISW), 42V, 2.5MHz, High Efficiency Step-Up
DC/DC Converter
VIN: 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = < 1µA, 3mm × 3mm DFN-8,
MSOP-8E
LT3479
3A (ISW), 40V, 3.5MHz, High Efficiency Step-Up
DC/DC Converter
VIN: 2.5V to 24V, VOUT(MAX) = 40V, IQ = 5mA, ISD = < 1µA, 4mm × 3mm DFN-14,
TSSOP-16E
42
Rev. B
10/18
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For more information www.analog.com
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