LT3686AEMSE#TRPBF

LT3686A 37V/1.2A Step-Down Regulator in 3mm × 3mm DFN and MSE Description Features Wide Input Range: Operation from 3.6V to 37V Overvoltage Lockout Protects Circuit Through 60V Transients ■ Low Minimum On-Time: Converts 16VIN to 3.3VOUT at 2MHz ■ 1.2A Output Current ■ Adjustable Frequency: 300kHz to 2.5MHz ■ Constant Switching Frequency at Light Loads ■ Can Be Synchronized to External Clock ■ Tracking and Soft-Start ■ Precision UVLO ■ Short-Circuit Robust ■ I in Shutdown 0.8V, BD < 6V 100 110 150 200 Switch VCESAT ISW = 1.2A 680 Switch Current Limit (Note 3) 0.3 1.9 Minimum Off Time ● Switch Active Current 1.9 1.85 SW = 10V (Note 4) SW = 0V (Note 5) 2.6 2.65 A A 400 20 600 30 µA µA BOOST Pin Current ISW = 1.2A 20 ISW = 1.2A 2.2 Max BD Pin Active Load Current SYNC/MODE > 0.8V, BD < 6V 30 40 6 6.5 ● 1.2 1.7 ● 0.8 BD Pin Voltage to Disable Active Load ● DA Pin Current to Stop OSC SYNC/MODE High SYNC/MODE Low ● EN/UVLO Bias Current VEN/UVLO = 10V VEN/UVLO = 0V EN/UVLO Threshold to Turn Off 1.3 ● EN/UVLO Hysteresis Current IBD to IBOOST = 200mA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3686AE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3686AI is guaranteed over the full –40°C to 125°C operating junction temperature range. The LT3686AH is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. (Note 6) V mA 7 V A 0.4 V 0.2 µA 2.7 µA 40 1 µA µA 0.9 VSS = 1V Boost Diode Forward Drop mA 2.4 V SYNC/MODE Bias Current SS Threshold ns mV 2.3 2.3 Minimum Boost Voltage Above Switch SS Source Current UNITS 2 V 1.22 1.28 1.34 V 1.8 2.4 3 µA 0.85 V Note 3: Current limit guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycle. Note 4: Current flows into pin. Note 5: Current flows out of pin. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. See High Temperature Considerations section. Also see Operation section. Note 7: Absolute Maximum Voltage at VIN and EN/UVLO pins is 60V for nonrepetitive one second transients, and 55V for continuous operation. 3686afa 3 LT3686A Typical Performance Characteristics 5VOUT Efficiency 3.3VOUT Efficiency (2MHz) 90 30 VIN = 12V VOUT = 3.3V L = 6.8µH f = 2MHz 20 10 0 200 800 1000 600 400 LOAD CURRENT (mA) 50 MODE/SYNC < 0.4V 40 30 10 0 200 800 1000 600 400 LOAD CURRENT (mA) 3686A G01 10 20 VIN (V) 30 40 3686A G03 Internal Undervoltage Lockout (UVLO) 4.0 700 3.5 600 MINIMUM VSW (mV) IOUT (A) 0 800 1.0 0.8 500 400 3.0 300 0.6 0.4 10 20 VIN (V) 30 100 40 0 500 0 1000 1500 ISW (mA) 2000 Overvoltage Lockout (OVLO) 2.0 –50 0 50 100 TEMPERATURE (°C) 150 3686A G06 VFB vs Temperature 40 820 39 810 38 VFB (mV) VIN (V) 2500 3686A G05 3686A G04 37 800 790 36 35 –50 2.5 150°C 125°C 25°C –50°C 200 VOUT = 5V L = 10µH f = 2MHz 0.2 0 0 1200 900 1.6 1.2 VOUT = 3.3V L = 6.8µH f = 2MHz 0.2 Switch Voltage Drop TYPICAL 1.4 0.8 3686A G02 5VOUT Maximum Load Current 1.8 1.0 0.4 VIN (V) 2.0 1.2 0.6 VIN = 12V VOUT = 5V L = 10µH f = 2MHz 20 0 MINIMUM 1.4 60 1200 TYPICAL 1.6 IOUT (A) EFFICIENCY (%) MODE/SYNC < 0.4V 40 1.8 MODE/SYNC > 0.8V 70 60 50 2.0 80 MODE/SYNC > 0.8V 70 EFFICIENCY (%) 3.3VOUT Maximum Load Current 90 80 0 TA = 25°C unless otherwise noted. 0 50 100 TEMPERATURE (°C) 150 3686A G07 780 –50 0 50 100 TEMPERATURE (°C) 150 3686A G08 3686afa 4 LT3686A Typical Performance Characteristics Switching Frequency vs Temperature Switching Frequency vs RT 2.20 FREQUENCY (MHz) 250 RT (kΩ) 200 150 100 50 0 Soft-Start/Track vs Frequency (1MHz) 1200 RT = 15.4k 2.15 1000 2.10 800 FREQUENCY (kHz) 300 2.05 2.00 0 0.5 1 1.5 FREQUENCY (MHz) 2 1.90 –50 2.5 0 50 100 TEMPERATURE (°C) 600 30 400 300 20 15 5 0 0 1000 1200 0 10 20 30 EN/UVLO (V) 40 3.0 1.0 –50 50 SWITCH PEAK MODE/SYNC > 0.8 30 25 MODE/SYNC < 0.4 15 VIN (V) VIN (V) 150 5VOUT Maximum VIN for Full Frequency (2MHz) MODE/SYNC > 0.8 2.0 1.0 50 100 TEMPERATURE (°C) 35 20 DA VALLEY 0 3686A G14 25 2.5 CURRENT LIMIT (A) 1.5 3.3VOUT Maximum VIN for Full Frequency (2MHz) Current Limit vs Duty Cycle 2500 2.0 3686A G13 3686A G12 1.5 2000 2.5 25 100 600 800 SS (mV) 1000 1500 SS (mV) 3.0 10 200 400 500 Switch Current Limit vs Temperature CURRENT LIMIT (A) 35 EN/UVLO (µA) FB (mV) 700 500 0 3686A G11 45 40 10 MODE/SYNC < 0.4 20 15 10 5 0.5 0 0 150 EN/UVLO Pin Current 800 200 400 3686A G10 Soft-Start/Track vs VFB 0 600 200 1.95 3686A G09 900 TA = 25°C unless otherwise noted. 0 25 50 75 DUTY CYCLE (%) 100 3686A G15 0 VOUT = 3.3V L = 6.8µH f = 2MHz 0 500 1000 LOAD CURRENT (mA) 1500 3686A G16 VOUT = 5V L = 10µH f = 2MHz 5 0 0 1000 500 LOAD CURRENT (mA) 3686A G17 3686afa 5 LT3686A Typical Performance Characteristics 3.3VOUT Typical Minimum Input Voltage 8 6 7 VIN (V) 3 IL 200mA/DIV 4 2 VOUT = 3.3V L = 15µH f = 1MHz 1 1 10 100 1000 VOUT = 5V L = 22µH f = 1MHz 1 0 3686A G20 200ns/DIV 3 2 0 VSW 2V/DIV MODE/SYNC > 0.8 5 MODE/SYNC > 0.8 Continuous Mode Waveform MODE/SYNC < 0.4 6 MODE/SYNC < 0.4 4 VIN (V) 5VOUT Typical Minimum Input Voltage 7 5 TA = 25°C unless otherwise noted. 10 1 ILOAD (mA) 100 1000 VIN = 10V VOUT = 3.3V L = 6.8µH f = 2MHz COUT = 22µF ILOAD = 200mA MODE/SYNC = 0V ILOAD (mA) 3686A G18 3686A G19 Fixed Frequency No Load Waveform Light Load Discontinuous Mode Waveform Start-Up Shutdown Waveform ILOAD = 5mA VIN 1V/DIV VSW 2V/DIV VSW 2V/DIV IL 200mA/DIV IL 200mA/DIV 3686A G21 200ns/DIV VIN = 10V VOUT = 3.3V L = 6.8µH f = 2MHz COUT = 22µF ILOAD = 25mA MODE/SYNC = 0V Start-Up Shutdown Waveform ILOAD = 5mA VIN 1V/DIV VOUT 1V/DIV 3686A G22 200ns/DIV VIN = 10V VOUT = 3.3V L = 6.8µH f = 2MHz COUT = 22µF ILOAD = 0mA MODE/SYNC = 3.3V Start-Up Shutdown Waveform ILOAD = 500mA 200ms/DIV VOUT = 5V L = 22µH f = 1MHz ILOAD = 5mA MODE/SYNC = 1V VIN 1V/DIV VOUT 1V/DIV 3686A G24 3686A G23 Start-Up Shutdown Waveform ILOAD = 500mA VIN 1V/DIV VOUT 1V/DIV 200ms/DIV VOUT = 5V L = 22µH f = 1MHz ILOAD = 5mA MODE/SYNC = 0V 200ms/DIV VOUT = 5V L = 22µH f = 1MHz ILOAD = 500mA MODE/SYNC = 0V VOUT 1V/DIV 3686A G25 200ms/DIV VOUT = 5V L = 22µH f = 1MHz ILOAD = 500mA MODE/SYNC = 1V 3686A G26 3686afa 6 LT3686A Pin FunCtions (DFN/MSE) VIN (Pin 1/2): The VIN pin supplies current to the LT3686A’s internal regulator and to the internal power switch. This pin must be locally bypassed. BD (Pin 2/3): When the SYNC/MODE Pin is driven with clock pulses or tied greater than 0.8V, the LT3686A will prevent pulse-skipping at light loads by regulating an active load on the BD pin; see Applications Information section Fixed Frequency at Light Load. FB (Pin 3/4): The LT3686A regulates its feedback pin to 0.8V. Connect the feedback resistor divider tap to this pin. Set the output voltage according to: V  R1= R2  OUT – 1  0.8V  A good value for R2 is 10k. SS (Pin 4/5): Provides Soft-Start and Tracking. An internal 2µA current source tied to a 2.5V reference supplies current to this pin to charge an external capacitor to create a voltage ramp at the pin. Feedback voltage and switching frequency both track SS voltage. Feedback voltage stops tracking at 0.8V. SS is reset under UVLO, OVLO and thermal shutdown conditions. Float the pin if soft-start feature is not being used. RT (Pin 5/6): The RT pin is used to program the oscillator frequency. Select the value of RT resistor according to table 1 in the applications section of the data sheet. EN/UVLO (Pin 6/7): The EN/UVLO pin is used to start up the LT3686A. Pull the pin below 0.4V to shutdown the LT3686A. The 1.28V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from operating until the input voltage has reached the programmed level. Do not drive the EN/UVLO pin above VIN. SYNC/MODE (Pin 7/8): The SYNC/MODE pin is used to synchronize the internal oscillator of the LT3686A to an external signal. The SYNC signal can be driven by a signal with pulse width of at least 200ns on and off time. The SYNC/MODE Pin also acts as mode select for the BD active load; when it is driven with pulses or tied above 0.8V, the LT3686A will prevent pulse skipping at light loads by regulating an active load on the BD pin. To disable the active load, tie SYNC/MODE to below 0.4V. BOOST (Pin 8/9): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. DA (Pin 9/10): Connect catch diode (D1) anode to this pin. SW (Pin 10/11, 12): The SW pin is the output of the internal power switch. Connect this pin to the inductor, catch diode and boost capacitor. GND (Exposed Pad Pin 11/Pin 1, Exposed Pad Pin 13): The exposed pad GND pin is the only ground connection for the device. The exposed pad should be soldered to a large copper area to reduce thermal resistance. 3686afa 7 LT3686A Block Diagram BOOST VIN VIN R4 C2 EN/ULVO OFF ON R5 INT REG UVLO OVLO DRIVER 1.27V C3 Q1 SW L1 R1 FB SS R2 VOUT C1 BD – + + D1 gm ACTIVE LOAD VC SLOPE COMP C4 R Q S Q 0.8V DA OSC FREQUENCY FOLDBACK GND RT SYNC/MODE 3686A BD R3 3686afa 8 LT3686A Operation The LT3686A is a current mode step-down regulator. The EN/UVLO pin is used to place the LT3686A in shutdown. The 1.28V threshold on the EN/UVLO pin can be programmed by an external resistor divider (R4, R5) to disable the LT3686A. When the EN/UVLO pin is driven above 1.28V, an internal regulator provides power to the control circuitry. This regulator includes both overvoltage and undervoltage lockout to prevent switching when VIN is more than 37V or less than 3.6V. Tracking soft-start is implemented by providing constant current via the SS pin to an external soft-start capacitor (C4) to generate a voltage ramp. FB voltage is regulated to the voltage at the SS pin until it exceeds 0.8V; FB is then regulated to the reference 0.8V. Soft-start also reduces the oscillator frequency to avoid hitting current limit during start-up. The SS capacitor is reset during fault events such as overvoltage, undervoltage, thermal shutdown and startup. An oscillator is programmed by resistor RT. The oscillator sets an RS flip-flop, turning on the internal 1.2A power switch Q1. An amplifier and comparator monitor the current flowing between the VIN and SW pins, turning the switch off when this current reaches a level determined by the voltage at VC. An error amplifier measures the output voltage through an external resistor divider tied to the FB pin and servos the VC node. If the error amplifier’s output increases, more current is delivered to the output; if it decreases, less current is delivered. An active clamp (not shown) on the VC node provides current limit. The switch driver operates from either VIN or from the BOOST pin. An external capacitor and the internal boost diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to fully saturate the internal bipolar NPN power switch for efficient operation. A comparator monitors the current flowing through the catch diode via the DA pin and reduces the LT3686A’s operating frequency when the DA pin current exceeds the 1.7A valley current limit. This helps to control the output current in fault conditions such as shorted output with high input voltage. The DA comparator works in conjunction with the switch peak current limit comparator to determine the maximum deliverable current of the LT3686A. The SYNC/MODE pin doubles as mode select for the BD active load circuit. The active load is enabled when SYNC/MODE is driven with sync pulses or tied above 0.8V and disabled when SYNC/MODE is tied below 0.4V. The LT3686A will prevent pulse skipping at light loads by regulating the active load. The active load will assist startup by guaranteeing a minimum load to charge the boost capacitor. It also hastens the recharge of boost capacitor when operating beyond maximum duty cycle. The active load works only when the BD pin is less than 6V. 3686afa 9 LT3686A Applications Information FB Resistor Network 45 The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: 40 EN/UVLO (µA) 35 ⎛V ⎞ R1= R2 ⎜ OUT – 1⎟ ⎝ 0.8V ⎠ 30 25 20 15 10 R2 should be 20k or less to avoid bias current errors. Reference designators refer to the Block Diagram. 5 0 0 10 Programmable Undervoltage Lockout  V  R4 = R5  IN – 1  1.28V  R4 also sets the hysteresis voltage for the programmable UVLO: Hysteresis = R4 • 2.4µA Once VIN drops below the programmed voltage, the LT3686A will enter a low quiescent current state (Iq ≈ 15µA). To shutdown the LT3686A completely (Iq < 1µA), reduce EN/UVLO pin voltage to below 0.4V. 10000 50 Figure 2. EN/UVLO Pin Current Input Voltage Range The input voltage range for the LT3686A applications depends on the output voltage and on the absolute maximum ratings of the VIN and BOOST pins. The minimum input voltage is determined by either the LT3686A’s minimum operating voltage of 3.6V, or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: VOUT + VD DC = VIN – VSW + VD Where VD is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.67V at maximum load). This leads to a minimum input voltage of: 1000 100 IQ (µA) 40 3686A F02 The EN/UVLO pin can be programmed by an external resistor divider between VIN and the EN/UVLO pin. Choose the resistors according to: 10 1 0.1 20 30 EN/UVLO (V) VIN(MIN) = VOUT + VD – VD + VSW DCMAX DCMAX can be adjusted with frequency. 0 1 2 3 4 5 EN/UVLO (V) 6 7 8 3686A F01 Figure 1. IQ vs VEN/UVLO (VIN = 10V) The boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to sustain the charge across the boost capacitor. 3686afa 10 LT3686A Applications Information The maximum input voltage is determined by the absolute maximum ratings of the VIN and BOOST pins. For fixed frequency operation, the maximum input voltage is determined by the minimum duty cycle DCMIN: VIN(MAX) = VOUT + VD – VD + VSW DCMIN DCMIN can be adjusted with frequency. Note that this is a restriction on the operating input voltage for fixed frequency operation; the circuit will tolerate transient inputs up to the absolute maximum ratings of the VIN and BOOST pins. Minimum On Time As the input voltage is increased, the LT3686A is required to switch for shorter periods of time. Delays associated with turning off the power switch dictate the minimum on time of the part. The minimum on time for the LT3686A is 100ns (Figure 3). When the required on time decreases below the typical minimum on time of 100ns, instead of the switch pulse width becoming narrower to accommodate the lower duty cycle requirement, the switch pulse width remains fixed at 100ns. The inductor current ramps up to a value exceeding the load current and the output ripple increases. The part then remains off until the output voltage dips below the programmed value before it begins switching again (Figure 4). VSW 20V/DIV IL 500mA/DIV VOUT 100mA/DIV AC 2µs/DIV 3686A F04 VIN = 35V VOUT = 3.3V L = 6.8µH COUT = 22µF IOUT = 300mA Figure 4. Pulse Skip Occurs When Required On Time Is Below 100ns VSW 10V/DIV IL 500mA/DIV VOUT 100mV/DIV AC 500ns/DIV 3686A F03 VIN = 18V VOUT = 3.3V L = 6.8µH COUT = 22µF ILOAD = 1.2mA Figure 3. Continuous Mode Operation Near Minimum On Time Provided that the load can tolerate the increased output voltage ripple and that the components have been properly selected, operation while pulse skipping is safe and will not damage the part. As the input voltage increases, the inductor current ramps up quicker, the number of skipped pulses increases, and the output voltage ripple increases. Inductor current may reach current limit when operating in pulse skip mode with small valued inductors. In this case, the LT3686A will periodically reduce its frequency 3686afa 11 LT3686A Applications Information to keep the inductor valley current to 1.7A (Figure 5). Peak inductor current is therefore peak current plus minimum switch delay: 1.7A + (VIN – VOUT )/L • 100ns VSW 10V/DIV IL 500mA/DIV VOUT 100mA/DIV AC 2µs/DIV 3686A F05 VIN = 35V VOUT = 3.3V L = 6.8µH COUT = 22µF IOUT = 1.2A Table 1. RT vs Frequency FREQUENCY (MHz) RT (kΩ) MIN SYNC FREQUENCY (MHz) 2.5 9.53 N/A 2.3 12.1 N/A 2.1 15.4 N/A 1.9 20.0 N/A 1.8 22.6 2.50 1.7 25.5 2.30 1.5 31.6 1.99 1.3 40.2 1.70 1.1 52.3 1.42 0.9 69.8 1.14 0.7 97.6 0.874 0.5 150 0.615 0.3 280 0.363 Figure 5. Pulse Skip with Large Load Current Will Be Limited by the DA Valley Current Limit. Notice the Flat Inductor Valley Current and Reduced Switching Frequency 250 200 RT (kΩ) The part is robust enough to survive prolonged operation under these conditions as long as the peak inductor current does not exceed 2A. Inductor current saturation and junction temperature may further limit performance during this operating regime. 300 100 50 Frequency Selection 0 0 0.5 1 1.5 FREQUENCY (MHz) 2 2.5 3686A F06a Figure 6a. Switching Frequency vs RT 40 35 30 INDUCTANCE (µH) The maximum frequency that the LT3686A can be programmed to is 2.5MHz. The minimum frequency that the LT3686A can be programmed to is 300kHz. The switching frequency is programmed by tying a 1% resistor from the RT pin to ground. Table 1 can be used to select the value of RT. Minimum on-time and edge loss must be taken into consideration when selecting the intended frequency of operation. Higher switching frequency increases power dissipation and lowers efficiency. Finite transistor bandwidth limits the speed at which the power switch can be turned on and off, effectively setting the minimum on-time of the LT3686A. For a given output voltage, the minimum on-time determines the maximum input voltage to remain in continuous mode operation outlined in the Minimum On Time section of the data sheet. Finite transition time results in a small amount of power dissipation each time the power switch turns on and off (edge loss). Edge loss increases with frequency, switch current, and input voltage. 150 5VOUT 25 12VOUT 20 15 3.3VOUT 10 5 0 0.25 0.75 1.25 1.75 FREQUENCY (MHz) 2.25 3686A F06b Figure 6b. Suggested Inductance vs Frequency 3686afa 12 LT3686A Applications Information The SYNC/MODE pin is used to synchronize the internal oscillator with an external square wave. The synchronizing clock signal to the LT3686A should be below 2.5MHz with pulse width of at least 200ns on and off time, a low state below 0.4V and a high state above 0.8V. The SYNC frequency must be higher than the RT programmed frequency; see Table 1. Using a smaller value inductor will increase inductor current ripple and reduce the VIN voltage at which the active load can keep the LT3686A at full switching frequency. The SYNC/MODE pin doubles as mode select for the BD active load circuit. The active load is enabled when SYNC/MODE is driven with clock pulses or tied greater than 0.8V and disabled when SYNC/MODE is tied below 0.4V. See Fixed Frequency at Light Load section. There are several graphs in the Typical Performance Characteristics section of this data sheet that show the maximum load current as a function of input voltage and inductor value for several popular output voltages. Low inductance may result in discontinuous mode operation, which is okay, but further reduces maximum load current. For details of the maximum output current and discontinuous mode operation, see Linear Technology Application Note 44. Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. See Linear Technology Application Note 19. Inductor Selection and Maximum Output Current Catch Diode A good first choice for the inductor value is: A low capacitance 1-2A Schottky diode is recommended for the catch diode, D1. The diode must have a reverse voltage rating equal to or greater than the maximum input voltage. The MBRM140 is a good choice; it is rated for 1A continuous forward current and a maximum reverse voltage of 40V. The inductor value should be chosen based on the RT frequency rather than the highest synchronization frequency. L= 4(VOUT + VD) f where VD is the voltage drop of the catch diode (~0.4V), L is in μH, frequency is in MHz. With this value there will be no subharmonic oscillation. The inductor’s RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. For robust operation during fault conditions, the saturation current should be above 2A. To keep efficiency high, the series resistance (DCR) should be less than 0.1Ω. Table 2 lists several vendors and types that are suitable. For small size, the inductor can be chosen according to: L= 2(VOUT + VD) f Input Capacitor Bypass the input of the LT3686A circuit with a 2.2μF or higher value ceramic capacitor of X7R or X5R type. Y5V types have poor performance over temperature and applied voltage and should not be used. A 2.2μF ceramic is adequate to bypass the LT3686A and will easily handle the ripple current. However, if the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be Table 2. VENDOR URL PART SERIES INDUCTANCE RATE(µH) SIZE (mm) Sumida www.sumida.com CDRH4D28 CDRH5D28 CDRH8D28 1.2 to 4.7 2.5 to 10 2.5 to 33 4.5 x 4.5 5.5 x 5.5 8.3 x 8.3 www.toko.com A916CY D585LC 2 to 12 1.1 to 39 6.3 x 6.2 8.1 x 8 www.we-online.com WE-TPC(M) WE-PD2(M) WE-PD(S) 1 to 10 2.2 to 22 1 to 27 4.8 x 4.8 5.2 x 5.8 7.3 x 7.3 Toko Würth Elektronik 3686afa 13 LT3686A Applications Information necessary. This can be provided with a low performance electrolytic capacitor. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3686A and to force this very high frequency switching current into a tight local loop, minimizing EMI. A 2.2μF capacitor is capable of this task, but only if it is placed close to the LT3686A and the catch diode (see the PCB Layout section). A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3686A. A ceramic input capacitor combined with trace or cable inductance forms a high quality (underdamped) tank circuit. If the LT3686A circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3686A’s voltage rating. This situation is easily avoided; see the Hot Plugging Safely section. where COUT is in μF and frequency is in MHz. Use an X5R or X7R type and keep in mind that a ceramic capacitor biased with VOUT will have less than its nominal capacitance. This choice will provide low output ripple and good transient response. Transient performance can be improved with a high value capacitor, but a phase lead capacitor across the feedback resistor, R1, may be required to get the full benefit (see the Compensation section). For small size, the output capacitor can be chosen according to: VOUT • f High performance electrolytic capacitors can be used for the output capacitor. Low ESR is important, so choose one that is intended for use in switching regulators. The ESR should be specified by the supplier and should be 0.1Ω or less. Such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance, because the capacitor must be large to achieve low ESR. Table 3 lists several capacitor vendors. The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT3686A to produce the DC output. In this role it determines the output ripple so low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and stabilize the LT3686A’s control loop. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best ripple performance. A good value is: 83 where COUT is in μF and frequency is in MHz. However, using an output capacitor this small results in an increased loop crossover frequency and increased sensitivity to noise, requiring careful PCB design. Output Capacitor C OUT = C OUT = 145 VOUT • f Table 3. VENDOR PHONE URL PART SERIES COMMENTS Panasonic (714) 373-7366 www.panasonic.com Ceramic Polymer Tantalum EEF Series Kemet (864) 963-6300 www.kemet.com Ceramic Tantalum Sanyo (408) 794-9714 www.sanyovideo.com Ceramic Polymer Tantalum Murata (404) 436-1300 AVX Taiyo Yuden (864) 963-6300 www.murata.com Ceramic www.avxcorp.com Ceramic Tantalum www.taiyo-yuden.com Ceramic T494, T495 POSCAP TPS Series 3686afa 14 LT3686A Applications Information Figure 7 shows the transient response of the LT3686A with several output capacitor choices. The output is 3.3V. The load current is stepped from 0.25A to 1A and back to 0.25A, and the oscilloscope traces show the output voltage. The upper photo shows the recommended value. The second photo shows the improved response (less voltage drop) resulting from a larger output capacitor and a phase lead capacitor. The last photo shows the response to a high performance electrolytic capacitor. Transient performance is improved due to the large output capacitance. BOOST and BD Pin Considerations Capacitor C3 and the internal boost diode are used to generate a boost voltage that is higher than the input voltage. In most cases a 0.22μF capacitor will work well. Figure 8 shows two ways to arrange the boost circuit. The BOOST pin must be at least 2.2V above the SW pin for best efficiency. For outputs of 3V and above, the standard circuit (Figure 8a) is best. For outputs less than 3V and above 2.5V, place a discrete Schottky diode (such as the SYNC/MODE < 0.4V SYNC/MODE > 0.8V VOUT 32.4k 22µF FB 10k IL 500mA/DIV IL 500mA/DIV VOUT 50mV/DIV AC VOUT 50mV/DIV AC 3686A F07a 20µs/DIV 3686A F07b 20µs/DIV 3686A F07c 20µs/DIV 3686A F07f 20µs/DIV 3686A F07i VOUT 32.4k 47pF 22µF ×2 FB 10k IL 500mA/DIV IL 500mA/DIV VOUT 50mV/DIV AC VOUT 50mV/DIV AC 3686A F07d 20µs/DIV 3686A F07e VOUT 32.4k FB 10k + 100µF SANYO 4TPB100M IL 500mA/DIV IL 500mA/DIV VOUT 50mV/DIV AC VOUT 50mV/DIV AC 3686A F07g 20µs/DIV 3686A F07h Figure 7. Transient Load Response of the LT3686A with Different Output Capacitors as the Load Current Is Stepped from 0.25A to 1A. VIN = 12V, VOUT = 3.3V, L = 6.8µH , Frequency = 2MHz 3686afa 15 LT3686A Applications Information BAT54) in parallel with the internal diode to reduce VD. The following equations can be used to calculate and minimize boost capacitance in μF: CBOOST = the optimal boost capacitor for the chosen BD voltage. The absence of BD voltage during startup will increase minimum voltage to start and reduce efficiency. You must also be sure that the maximum voltage rating of BOOST pin is not exceeded. The BD pin can also be tied to VIN (Figure 8c) but VIN will be limited to 25V and the active load circuit is automatically disabled. 0.065 (VBD + VCATCH – VD − 2.2) • f VD is the forward drop of the boost diode, VCATCH is the forward drop of the catch diode (D1), and frequency is in MHz. A typical value of 0.22µF can be used for CBOOST. The minimum operating voltage of an LT3686A application is limited by the undervoltage lockout (3.6V) and by the maximum duty cycle as outlined above. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or For lower output voltages the BD pin can be tied to an external voltage source with adequate local bypassing (Figure 8b). The above equations still apply for calculating BD BOOST LT3686A VIN VIN SW DA GND 8a VOUT VBOOST – VSW ≅ VOUT MAX VBOOST ≅ VIN + VOUT VDD BD BOOST LT3686A VIN VIN SW DA GND 8b VOUT VBOOST – VSW ≅ VDD MAX VBOOST ≅ VIN + VDD BD BOOST LT3686A VIN VIN SW GND 8c VOUT DA VBOOST – VSW ≅ VIN MAX VBOOST ≅ 2VIN 3686A F08 Figure 8. 3686afa 16 LT3686A Applications Information the LT3686A is turned on with its EN/UVLO pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on the input and output voltages, and on the arrangement of the boost circuit. The minimum load generally goes to zero once the circuit has started. Figure 9 shows plots of minimum load to start and to run as a function of input voltage. In many cases the discharged output capacitor will present a load to the switcher which will allow it to start. At light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. This reduces the minimum input voltage to approximately 400mV above VOUT. At higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle, requiring a higher input voltage to maintain regulation. As the LT3686A enters dropout, the boost capacitor voltage will be limited by VOUT, which is fixed by the maximum duty cycle. If the boost capacitor’s voltage during dropout falls 7 9 8 6 7 6 4 VIN (V) VIN (V) 5 3 4 3 2 2 START RUN SUSTAIN 1 0 5 1 10 100 START RUN SUSTAIN 1 0 1000 1 10 ILOAD (mA) 100 3686A F09a Figure 9a. Typical Minimum Input Voltage, VOUT = 3.3V, f = 1MHz, L = 15µH, SYNC/MODE < 0.4V Figure 9b. Typical Minimum Input Voltage, VOUT = 5V, f = 1MHz, L = 22µH, SYNC/MODE < 0.4V 8 6 7 RUN 5 4 3 4 3 2 2 1 0 RUN 6 VIN (V) VIN (V) 3686A F09b 7 5 1000 ILOAD (mA) 1 1 10 100 1000 ILOAD (mA) 0 1 10 100 1000 ILOAD (mA) 3686A F09c Figure 9c. Typical Minimum Input Voltage, VOUT = 3.3V, f = 1MHz, L = 15µH, SYNC/MODE > 0.8V 3686A F09d Figure 9d. Typical Minimum Input Voltage, VOUT = 5V, f = 1MHz, L = 22µH, SYNC/MODE > 0.8V 3686afa 17 LT3686A Applications Information below the minimum voltage to sustain boosted operation (2.2V across the boost capacitor), the output voltage will fall suddenly to: VOUT = (VIN –2.2) • DCMAX Figure 9 shows the minimum VIN necessary to sustain boosted operation during dropout. Once VIN drops below the sustain voltage, VIN will need to reach the start voltage again to refresh the boost capacitor. The programmable undervoltage lockout (UVLO) function can be used to avoid operating unless VIN is greater than the start voltage. Fixed Frequency at Light Load The LT3686A contains unique active load circuitry to allow for full frequency switching at very light loads. To enable the active load, drive the SYNC/MODE pin with clock pulses or a DC voltage greater than 0.8V. Typical fixed frequency nonsynchronous buck regulators skip pulses at light loads. With a fixed input voltage, as the load current decreases in discontinuous mode, the regulator is required to switch for shorter periods of time. When the required on time decreases below the typical minimum on time, the regulator skips one or more pulses so the effective average duty cycle is equal to the required duty cycle. This likelihood of entering pulse-skipping is exacerbated by the tendency for minimum on time to increase at very light loads. Pulse-skipping is undesirable because it causes unpredictable, sub-harmonic output ripple that can interfere with the operation of other sensitive components such as AM receivers and audio equipment. into a fixed on time, fixed frequency, open loop current source. Instead of controlling switch current, the internal error amplifier servos the active load on the output via the BD pin to maintain output voltage regulation. The impact on efficiency is mitigated by pulling the minimum current necessary to keep switching at full frequency. The necessary BD load to maintain output regulation depends on VIN, inductor size, and load current. As the necessary BD load increases beyond its 40mA limit, pulse-skipping mode will resume. The BD active load circuitry is enabled when MODE tied high and disabled when MODE is tied low. Even when activated, the active load will shutdown when BD voltage exceeds either 6V or VIN in an effort to minimize power dissipation and intelligently react to external configurations. To address the startup concerns delineated in the BOOST and BD Pin Considerations section, the active load will assist startup by pulling maximum current (40mA) to charge the boost capacitor voltage in the absence of an adequate load. An internal power good circuit will disable the BD active load when VFB reaches 0.7V. Figure 9 compares plots of minimum input voltage to start and run as a function of load current. In many cases the discharged output capacitor will present a load to the switcher which will allow it to start. The plots show the worst-case situation where VIN is ramping very slowly. The active load also activates to hasten the recharge of boost cap when operating beyond maximum duty cycle. When not in use, the active load pulls no current. The BD active load is designed to combat pulse-skipping by providing an operational regime between full frequency discontinuous and pulse-skipping modes. As the LT3686A approaches minimum on time in discontinuous mode, its power switch transitions smoothly 18 35 PULSE-SKIPPING 30 ACTIVE LOAD 25 VIN (V) The maximum VIN before pulse-skipping in discontinuous mode is directly dependent on load current; as the load decreases, so does the pulse-skipping boundary. An artificial load on the output helps push the pulse-skipping boundary higher. The LT3686A achieves this goal by commanding the minimum load necessary to keep itself at full switching frequency, hence the circuitry is called an active load. 40 20 DCM 15 CCM 10 5 0 0 20 40 60 80 IOUT (mA) 100 120 140 3686A F10 Figure 10. Regions of Operation (5VOUT, 2MHz) 3686afa LT3686A Applications Information Soft-Start The SS pin is used to soft-start the LT3686A, eliminating input current surge during start-up. It can also be used to track another voltage in the system (Figure 11). An internal 2µA current source charges an external softstart capacitor to generate a voltage ramp. FB voltage is regulated to the voltage at the SS pin until it exceeds 0.8V, FB is then regulated to the reference 0.8V. Soft-start also reduces the oscillator frequency to avoid hitting current limit during start-up. Figure 12 shows the start-up waveforms with and without the soft-start circuit. VOUT 2V/DIV VSS 500mV/DIV 1ms/DIV 3686A F11 Figure 11. LT3686A Configured to Track Voltage on SS Pin VSW 10V/DIV SS GND IL 500mA/DIV VOUT 2V/DIV VIN = 10V VOUT = 3.3V L = 6.8µH COUT = 22µF CSS = 0 5µs/DIV VSW 10V/DIV SS 1.2nF GND IL 500mA/DIV VOUT 2V/DIV VIN = 10V VOUT = 3.3V L = 6.8µH COUT = 22µF CSS = 1.2nF 50µs/DIV 3686A F12 Figure 12. To Soft Start the LT3686A, Add a Capacitor to the SS Pin 3686afa 19 LT3686A Applications Information Short and Reverse Protection If the inductor is chosen so that it won’t saturate excessively, the LT3686A will tolerate a shorted output. When operating in short-circuit condition, the LT3686A will reduce its frequency until the valley current is 1.7A (Figure 13). There is another situation to consider in systems where the output will be held high when the input to the LT3686A is absent. This may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode OR-ed with the LT3686A’s output. If the VIN pin is allowed to float and the EN/UVLO pin is held high (either by a logic signal or because it is tied to VIN), then the LT3686A’s internal circuitry will pull its quiescent current through its SW pin. This is fine if your system can tolerate a few mA in this state. If you ground the EN/UVLO pin, the SW pin current will drop to essentially zero. However, if the VIN pin is grounded while the output is held high, then parasitic diodes inside the LT3686A can VSW 20V/DIV pull large currents from the output through the SW pin and the VIN pin. Figure 14 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. Hot Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of LT3686A circuits. However, these capacitors can cause problems if the LT3686A is plugged into a live supply (see Linear Technology Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the VIN pin of the LT3686A can ring to twice the nominal input voltage, possibly exceeding the LT3686A’s rating and damaging the part. If the input supply is poorly controlled or the user will be plugging VIN VIN LT3686A BD BOOST EN/UVLO SW VOUT SYNC/MODE IL 500mA/DIV SS 2µs/DIV 3686A F13 VIN = 35V L = 6.8µH COUT = 22µF RT = 17.4k VOUT = 0V Figure 13. The LT3686A Reduces its Frequency from 2MHz to 160kHz to Protect Against Shorted Output DA RT GND FB 3686A F14 Figure 14. Input Diode Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output; it Also Protects the Circuit from a Reversed Input. The LT3686A Runs Only When the Input is Present 3686afa 20 LT3686A Applications Information the LT3686A into an energized supply, the input network should be designed to prevent this overshoot. Figure 15 shows the waveforms that result when an LT3686A circuit is connected to a 24V supply through six feet of 24-gauge twisted pair. The first plot is the response with a 2.2μF ceramic capacitor at the input. The input voltage rings as high as 35V and the input current peaks at 20A. One method of damping the tank circuit is to add another capacitor with a series resistor to the circuit. In Figure 15b an aluminum electrolytic capacitor has been added. This capacitor’s high equivalent series resistance damps the circuit and eliminates the voltage overshoot. The extra CLOSING SWITCH SIMULATES HOT PLUG IIN VIN + LOW IMPEDANCE ENERGIZED 24V SUPPLY + LT3686A capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the circuit. An alternative solution is shown in Figure 15c. A 1Ω resistor is added in series with the input to eliminate the voltage overshoot (it also reduces the peak input current). A 0.1μF capacitor improves high frequency filtering. This solution is smaller and less expensive than the electrolytic capacitor. For high input voltages its impact on efficiency is minor, reducing efficiency one percent for a 5V output at full load operating from 24V. VIN 20V/DIV 2.2µF 20µs/DIV (15a) LT3686A + RINGING VIN MAY EXCEED ABSOLUTE MAXIMUM RATING OF THE LT3686A IIN 5A/DIV STRAY INDUCTANCE DUE TO 6 FEET (2 METERS) OF TWISTED PAIR 10µF 35V AI.EI. DANGER! VIN 20V/DIV 2.2µF IIN 5A/DIV (15b) 1Ω + 0.1µF LT3686A 20µs/DIV VIN 20V/DIV 2.2µF IIN 5A/DIV (15c) 20µs/DIV 3686A F15 Figure 15. A Well Chosen Input Network Prevents Input Voltage Overshoot and Ensures Reliable Operation When the LT3686A Is Connected to a Live Supply 3686afa 21 LT3686A Applications Information Frequency Compensation The LT3686A uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3686A does not require the ESR of the output capacitor for stability allowing the use of ceramic capacitors to achieve low output ripple and small circuit size. Figure 16 shows an equivalent circuit for the LT3686A control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC node. Note that the output capacitor integrates this current, and that the capacitor on the VC node (CC) integrates the error amplifier output current, resulting in two poles in the loop. RC provides a zero. With the recommended output capacitor, 1V – + RC 160k CC 100pF GND gm = 2A/V OUT R1 – VC CURRENT MODE POWER STAGE CPL FB gm = 200µA/V ERROR AMPLIFIER 1M + LT3686A the loop crossover occurs above the RCCC zero. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. With a larger ceramic capacitor (very low ESR), crossover may be lower and a phase lead capacitor (CPL) across the feedback divider may improve the phase margin and transient response. Large electrolytic capacitors may have an ESR large enough to create an additional zero, and the phase lead may not be necessary. If the output capacitor is different than the recommended capacitor, stability should be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. ESR 800mV + C1 C1 R2 3686A F16 Figure 16. Model for Loop Response 3686afa 22 LT3686A Applications Information PCB Layout High Temperature Considerations For proper operation and minimum EMI, care must be taken during printed circuit board layout. Figure 17 shows the recommended component placement with trace, ground plane and via locations. Note that large, switched currents flow in the LT3686A’s VIN and SW pins, the catch diode (D1) and the input capacitor (C2). The loop formed by these components should be as small as possible and tied to system ground in only one place. These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. Place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor C1. The SW and BOOST nodes should be as small as possible. Finally, keep the FB node small so that the ground pin and ground traces will shield it from the SW and BOOST nodes. Include vias near the exposed GND pad of the LT3686A to help remove heat from the LT3686A to the ground plane. The die temperature of the LT3686A must be lower than the maximum rating of 125°C (150°C for LT3686AH). For high ambient temperatures, care should be taken in the layout of the circuit to ensure good heat sinking of the LT3686A. The maximum load current should be derated as the ambient temperature approaches the maximum allowed junction temperature. The die temperature is calculated by multiplying the LT3686A power dissipation by the thermal resistance from junction to ambient. Power dissipation within the LT3686A can be estimated by calculating the total power loss from an efficiency measurement and subtracting the catch diode loss. The resulting temperature rise at full load is nearly independent of input voltage. Thermal resistance depends on the layout of the circuit board, but 43°C/W is typical for the (3mm × 3mm) DFN package. C1 OUT SW D1 C2 BD FB VIN DA SS RT UVLO BST SYNC/ MODE 3686A F17 Figure 17. PCB Layout 3686afa 23 LT3686A Applications Information Outputs Greater Than 19V Note that for outputs above 19V, the input voltage range will be limited by the maximum rating of the BOOST pin. The sum of input and output voltages cannot exceed the BOOST pin’s 55V rating. The 25V circuit (Figure 18) shows how to overcome this limitation using an additional Zener diode. Other Linear Technology Publications Application Notes 19, 35 and 44 contain more detailed descriptions and design information for Buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note 318 shows how to generate a bipolar output supply using a buck regulator. VIN 30V TO 36V 2.2µ 0.22µF 15V VIN LT3686A BD BOOST EN/UVLO 0.22µF SYNC/MODE SW 100µH SS 100n RT DA GND 61.9k VOUT 500mA 301k FB 10µF 10k 3686A F18 Figure 18. 25V Step-Down Converter 3686afa 24 LT3686A Typical Applications 0.8V Step-Down Converter VIN 3.6V TO 25V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 0.22µF 2.2µH VOUT 0.8V 1.2A SW DA RT GND FB 61.9k 100µF 3686A TA02a 3.3V Step-Down Converter VIN 5V TO 37V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 0.22µF 6.8µH VOUT 3.3V 1.2A SW DA RT GND 31.6k FB 61.9k 22µF 10k 3686A TA02b 1.8V Step-Down Converter VIN 3.6V TO 25V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 3.3µH VOUT 1.8V 1.2A SW DA RT GND 61.9k 0.22µF 12.4k FB 47µF 10k 3686A TA02c 3686afa 25 LT3686A Typical Applications 3.3V Step-Down Converter with Programmed UVLO VIN 7.5V TO 37V BD VIN 500k 2.2µF EN/UVLO LT3686A 0.22µF 6.8µH VOUT 3.3V 1.2A SW 100k SYNC/MODE SS 1nF BOOST RT DA 31.6k FB 22µF 10k GND 61.9k 3686A TA02d 2.5V Step-Down Converter VIN 3.6V TO 25V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 0.22µF 4.7µH VOUT 2.5V 1.2A SW DA RT GND 21.5k FB 61.9k 33µF 10k 3686A TA02e 5V Step-Down Converter VIN 7V TO 37V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 10µH VOUT 5V 1.2A SW DA RT GND 61.9k 0.22µF 52.3k FB 15µF 10k 3686A TA02f 3686afa 26 LT3686A Package Description MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev D) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ± 0.102 (.112 ± .004) 5.23 (.206) MIN 2.845 ± 0.102 (.112 ± .004) 0.889 ± 0.127 (.035 ± .005) 6 1 1.651 ± 0.102 3.20 – 3.45 (.065 ± .004) (.126 – .136) 0.12 REF 12 0.65 0.42 ± 0.038 (.0256) (.0165 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 ± 0.102 (.159 ± .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 ± 0.076 (.016 ± .003) REF 12 11 10 9 8 7 DETAIL “A” 0° – 6° TYP 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ± 0.0508 (.004 ± .002) MSOP (MSE12) 0910 REV D 3686afa 27 LT3686A Package Description DD Package DD Package 10-Lead Plastic DFN× (3mm 10-Lead Plastic DFN (3mm 3mm) × 3mm) (Reference DWG # 05-08-1699 (Reference LTC DWGLTC # 05-08-1699 Rev C) Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ± 0.10 10 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3686afa 28 LT3686A Revision History REV DATE DESCRIPTION PAGE NUMBER A 5/11 Revised MSOP in Features, Pin Configuration, Order Information and Package Description sections 1, 2, 27 Updated Electrical Characteristics section 3 Updated value for EN/UVLO pin in Pin Functions section 7 Updated values in Operation section Revised equation in Programmable Undervoltage Lockout section, Table 1 and minor text edit to Minimum On Time in Applications Information section 9 10, 12, 13 3686afa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LT3686A Typical Application 5V Step-Down Converter VIN 7V TO 37V BD VIN 2.2µF BOOST EN/UVLO LT3686A SYNC/MODE SS 1nF 0.22µF 10µH VOUT 5V 1.2A SW DA RT GND 52.3k FB 61.9k 15µF 10k 3686A TA02f related Parts PART NUMBER DESCRIPTION COMMENTS LT3686 37V, 55V with Transient Protection 1.2A, 2.5MHz, High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 37V, Transient to 55V, VOUT(MIN) = 0.8V, IQ = 1.1mA, ISD