LT3692A
Monolithic Dual Tracking
3.5A Step-Down Switching Regulator
Description
Features
Wide Input Range:
– Operation from 3V to 36V
– OVLO Protects Circuit Through 60V Transients
n Independent Supply, Shutdown, Soft-Start, UVLO,
Programmable Current Limit and Programmable
Power Good for Each 3.5A Regulator
n Die Temperature Monitor
n Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2MHz with Synchronized
Clock Output
n Independent Synchronized Switching Frequencies
Optimize Component Size
n Antiphase Switching
n Outputs Can Be Paralleled
n Flexible Output Voltage Tracking
n Low Dropout: 95% Maximum Duty Cycle
n 5mm × 5mm QFN Package
n FMEA Compliant 38-Pin Exposed Pad TSSOP Package
n
Applications
Automotive Supplies
Distributed Supply Regulation
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
The LT®3692A is a dual current mode PWM step-down
DC/DC converter with two internal 3.8A switches. Independent
input voltage, shutdown, feedback, soft-start, UVLO current
limit and comparator pins for each channel simplify complex
power supply tracking and sequencing requirements.
To optimize efficiency and component size, both converters have a programmable maximum current limit and are
synchronized to either a common external clock input, or
a resistor settable fixed 250kHz to 2MHz internal oscillator.
A frequency divider is provided for channel 1 to further
optimize component size. At all frequencies, a 180° phase
relationship between channels is maintained, reducing voltage ripple and component size. A clock output is available
for synchronizing multiple regulators.
Minimum input to output voltage ratios are improved by
allowing the switch to stay on through multiple clock cycles
only switching off when the boost capacitor needs recharging. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent current to 24.9kΩ
f • RILIM
where f is frequency in MHz, L in µH and R in kΩ.
4.5
PEAK SWITCH CURRENT (A)
4.0
When the LT3692A’s input supplies are operated at different
input voltages, an input capacitor sized for that channel
should be placed as close as possible to the respective
VIN pins.
A caution regarding the use of ceramic capacitors at the
input. A ceramic input capacitor can combine with stray
inductance to form a resonant tank circuit. If power is
applied quickly (for example by plugging the circuit into
a live power source) this tank can ring, doubling the input
voltage and damaging the LT3692A. The solution is to
either clamp the input voltage or dampen the tank circuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details, see Application Note 88.
Output Capacitor Selection
Typically step-down regulators are easily compensated with
an output crossover frequency that is 1/10 of the switching frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 1%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
3.5
CVOUT =
3.0
2.5
Example:
2.0
VOUT = 3.3V, Frequency = 1MHz, Max Load Step = 2A.
1.5
1.0
0 10 20 30 40 50 60 70 80 90 100
ILIM PIN RESISTOR (kΩ)
3692a F06
Figure 6. Peak Switch Current vs ILIM Resistor
Input Capacitor Selection
Bypass the inputs of the LT3692A circuit with a 4.7µF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors.
16
Max Load Step
Frequency • 0.01• VOUT
CVOUT =
2
= 60µF
1E6 • 0.01• 3.3V
The calculated value is only a suggested starting value.
Increase the value if transient response needs improvement
or reduce the capacitance if size is a priority. The output
capacitor filters the inductor current to generate an output
with low voltage ripple. It also stores energy in order to
satisfy transient loads and to stabilize the LT3692A’s control
loop. The switching frequency of the LT3692A determines
the value of output capacitance required. Also, the current
mode control loop doesn’t require the presence of output
capacitor series resistance (ESR). For these reasons, you
are free to use ceramic capacitors to achieve very low
output ripple and small circuit size.
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LT3692A
Applications Information
You can also use electrolytic capacitors. The ESRs of most
aluminum electrolytics are too large to deliver low output
ripple. Tantalum and newer, lower ESR organic electrolytic
capacitors intended for power supply use, are suitable
and the manufacturers will specify the ESR. The choice of
capacitor value will be based on the ESR required for low
ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may
give better transient response for large changes in load
current. Table 3 lists several capacitor vendors.
BST Pin Considerations
Table 3
VENDOR
TYPE
Taiyo Yuden
Ceramic X5R, X7R
SERIES
AVX
Ceramic X5R, X7R
Tantalum
Kemet
Tantalum
TA Organic
AL Organic
T491, T494, T495
T520
A700
Sanyo
TA/AL Organic
POSCAP
Panasonic
AL Organic
SP CAP
TDK
Ceramic X5R, X7R
Catch Diode
The diode D1 conducts current only during switch-off
time. Use a Schottky diode to limit forward voltage drop to
increase efficiency. The Schottky diode must have a peak
reverse voltage that is equal to regulator input voltage and
sized for average forward current in normal operation.
Average forward current can be calculated from:
ID(AVG) =
IOUT
• ( VIN – VOUT )
VIN
With a shorted condition, diode current will increase to the
typical value determined by the peak switch current limit
of the LT3692A set by the ILIM pin. This is safe for short
periods of time, but it would be prudent to check with the
diode manufacturer if continuous operation under these
conditions can be tolerated.
The capacitor and diode tied to the BST pin generate a
voltage that is higher than the input voltage. In most cases
a 0.47µF capacitor and a small Schottky diode (such as the
CMDSH-4E) will work well. To ensure optimal performance
at duty cycles greater than 80%, use a 0.5A Schottky
diode (such as a PMEG4005). Almost any type of film or
ceramic capacitor is suitable, but the ESR should be VIN + 3V
VIN
BST
C3
VIN
SW
VIN
BST
SW
LT3692A
LT3692A
IND
VOUT
VBST – VSW = VX
VBST(MAX) = VIN + VX
VX(MIN) = 3V
VOUT < 3V
GND
VBST – VSW = VIN
VBST(MAX) = 2 • VIN
D2
VIN
SW
IND
VOUT
VOUT
(7a)
VX = LOWEST VIN
OR VOUT > 3V
C3
LT3692A
IND
VOUT
VBST – VSW = VOUT
VBST(MAX) = VIN + VOUT
BST
IND
VOUT
VOUT < 3V
GND
VBST – VSW = VX
VBST(MAX) = VX
VX(MIN) = VIN + 3V
(7c)
VOUT < 3V
GND
3692a F07
(7d)
Figure 7. BST Pin Considerations
The minimum input voltage of an LT3692A application is
limited by the minimum operating voltage (typically 2.8V)
and by the maximum duty cycle as outlined above. For
proper start-up, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3692A is turned on with its SS pin when the
output is already in regulation, then the boost capacitor
may not be fully charged. Because the boost capacitor is
charged with the energy stored in the inductor, the circuit
will rely on some minimum load current to get the boost
circuit running properly. This minimum load will depend
on input and output voltages, and on the arrangement of
the boost circuit. The Typical Performance Characteristics
section shows plots of the minimum load current to start
and to run as a function of input voltage for 3.3V outputs.
In many cases the discharged output capacitor will present
a load to the switcher which will allow it to start. The plots
show the worst-case situation where VIN is ramping very
slowly. Use a Schottky diode for the lowest start-up voltage.
18
Outputs Greater Than 6V
For outputs greater than 6V, add a resistor of 1k to 2.5k
across the inductor to damp the discontinuous ringing of
the SW node, preventing unintended SW current. The 12V
output circuit in the Typical Applications section shows
the location of this resistor.
Frequency Compensation
The LT3692A uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3692A does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
VC pin. Generally a capacitor and a resistor in series to
ground determine loop gain. In addition, there is a lower
value capacitor in parallel. This capacitor is not part of
the loop compensation but is used to filter noise at the
switching frequency.
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LT3692A
Applications Information
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the compensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the
stability using a transient load.
Figure 8 shows an equivalent circuit for the LT3692A control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that
the output capacitor integrates this current, and that the
capacitor on the VC pin (CC) integrates the error amplifier
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor in series with CC.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (CPL) across the feedback divider may improve
the transient response.
Synchronization
The RT/SYNC pin can also be used to synchronize the
regulators to an external clock source. Driving the RT/SYNC
resistor with a clock source triggers the synchronization
detection circuitry. Once synchronization is detected, the
rising edge of SW1 will be synchronized to the rising edge
of the RT/SYNC signal and the rising edge of SW2 synchronized to the falling edge of the RT/SYNC signal (see
Figures 10 and 11). During synchronization, a 0V to 2.4V
square wave with the same frequency and duty cycle as
the synchronization signal is output via the CLKOUT pin
with a typical propagation delay of 250ns. In addition, an
internal AGC loop will adjust slope compensation to avoid
subharmonic oscillation. If the synchronization signal is
halted, the synchronization detection circuitry will timeout
in typically 10µs at which time the LT3692A reverts to the
free-running frequency based on the RT/SYNC pin voltage.
The synchronizing clock signal input to the LT3692A must
have a frequency between 200kHz and 2MHz, a duty cycle
between 20% and 80%, a low state below 0.5V and a high
state above 1.6V. Synchronization signals outside of these
parameters will cause erratic switching behavior. If the
RT/SYNC pin is held above 1.6V at any time, switching
will be disabled.
If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must remain below 1V until the synchronization circuitry
is active for proper start-up operation.
LT3692A
CURRENT MODE
POWER STAGE
gm = 4.8mho
OUTPUT
gm = 400µmho
3.6M
RC
CF
CC
+
–
VC
ERROR
AMP
R1
CPL
ESR
FB
C1
+
0.806V
R2
C1
CERAMIC
TANTALUM
OR
POLYMER
3692a F08
Figure 8. Model for Loop Response
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19
LT3692A
Applications Information
If the synchronization signal powers up in an undetermined
state (VOL, VOH, Hi-Z), connect the synchronization clock
to the LT3692A as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3692A
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
VOUT1
LT3692A
PG1
RT/SYNC
If the synchronization signal powers up in a low impedance
state (VOL), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the startup frequency.
If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
RT/SYNC pin to ground will set the start-up frequency.
VCC
SYNCHRONIZATION
CIRCUITRY
CLK
3692a F09
Figure 9. Synchronous Signal Powered from Regulator’s Output
tP
tP
SW1
SW1
tP/2
tP
tP
SW2
SW2
tP
tP/2
tPON
CLKOUT
CLKOUT
tDCLKOSW1
tDCLKOSW1
tDCLKOSW2
tP/2
tP
tDCLKOSW2
tPON
tP
RT/SYNC
RT/SYNC
3692a F10
tDRTSYNC
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%
20
tP
3692a F11
tDRTSYNCH
tDRTSYNCH
Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
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LT3692A
Applications Information
Reducing Input Ripple Voltage
Shutdown and Undervoltage/Overvoltage Lockout
Synchronizing the switches to the rising and falling edges
of the synchronization signal provides the unique ability to
reduce input ripple currents in systems where VIN1 and VIN2
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3692A with a 71%
duty cycle synchronization signal.
Typically, undervoltage lockout (UVLO) is used in situations where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source current increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where these problems might occur.
SW1
Overvoltage lockout (OVLO) is typically used to shut down
the switching regulator during potentially harmful input
voltage transients.
The overvoltage lockout threshold is typically 39V. Each
channel of the LT3692A is forced into shutdown when its
input voltage exceeds 39V, and will survive voltages as
high as 60V. When the input voltage drops back below
39V, the LT3692A goes through a POR cycle and the output
soft-starts from its existing level to its regulation point.
SW2
INPUT
RIPPLE V
RT/SYNC
3692a F12
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
SW1
SW2
Additionally, an internal comparator will force both channels into shutdown below the minimum VIN1 of 2.8V.
This feature can be used to prevent excessive discharge
of battery-operated systems. In addition to the VIN1 undervoltage lockout, both channels will be disabled when
SHDN1 is less than 1.32V.
Programmable UVLO may be implemented using an input
voltage divider and one of the internal comparators (see
the Typical Applications section).
INPUT
RIPPLE V
RT/SYNC
3692a F13
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
When the SHDN pin is taken above 1.32V, its respective
channel is allowed to operate. When the SHDN pin is driven
below 1.32V, its channel is disabled. Taking SHDN1 below
0.6V will place the LT3692A in a low quiescent current
mode. A graph of quiescent current vs SHDN1 voltage
can be found in the Typical Performance Characteristics
section. There is no hysteresis on the SHDN pins.
Keep the connections from any series resistors to the SHDN
pins short and make sure that the interplane or surface
capacitance to switching nodes is minimized.
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LT3692A
Applications Information
Soft-Start
The output of the LT3692A regulates to the lowest voltage
present at either the SS pin or an internal 0.806V reference.
A capacitor from the SS pin to ground is charged by an
internal 12µA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
tRAMP
C • 0.806V
= SS
12µA
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 12µA current source
starts to charge the SS pin.
When the SS pin voltage is below 115mV, the VC pin is
pulled low which disables switching. This allows the SS
pin to be used as an individual shutdown for each channel.
As the SS pin voltage rises above 90mV, the VC pin is released and the output is regulated to the SS voltage. When
the SS pin voltage exceeds the internal 0.806V reference,
the output is regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at typically 2.15V.
In the event of a VIN1 undervoltage lockout, the soft-start latch
is set for both channels, triggering a full start-up sequence. If
a channel’s SHDN pin is driven below 1.32V, its overvoltage
lockout is enabled, or the internal die temperature for its
power switch exceeds its maximum rating during normal
operation, the soft-start latch is set for that channel.
In addition, if the load exceeds the maximum output switch
current, the output will start to drop causing the VC pin
clamp to be activated. As long as the VC pin is clamped,
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output is
loaded by 1Ω the SS pin will drop to 0.64V, regulating the
output at 4.8V (4.8A • 1Ω). Once the overload condition
is removed, the output will soft start from the temporary
voltage level to the normal regulation point.
Since the SS pin is clamped at typically 2.15V and has to
discharge to 0.806V before taking control of regulation,
momentary overload conditions will be tolerated without
22
a soft-start recovery. The typical time before the SS pin
takes control is:
tSS(CONTROL) =
CSS • 1.2V
1.4mA
Open-Collector Comparators
The CMPO pin is the open-collector output of an internal
comparator. The comparator compares the CMPI pin voltage to 90% of the reference voltage (0.72V) with 60mV
of hysteresis.
The CMPO pin has a typical sink capability of 300µA when
the CMPI pin is below the threshold and can withstand 40V
when the threshold is exceeded. The CMPO pin is active
(sink capability is reduced in shutdown and undervoltage
lockout mode) as long as the VIN1 pin voltage exceeds
typically 2.8V.
The comparators can be used to monitor input and output
voltages as well as die temperature. See the Typical Applications circuit collection for examples.
Output Tracking/Sequencing
Complex output tracking and sequencing between channels
can be implemented using the LT3692A’s SS and CMPO
pins. Figure 14 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
Independent soft-start for each channel is shown in Figure 16a. The output ramp time for each channel is set by
the soft-start capacitor as described in the soft-start section.
Ratiometric tracking is achieved in Figure 14b by connecting both SS pins together. In this configuration, the
SS pin source current is doubled (24µA) which must be
taken into account when calculating the output rise time.
By connecting a feedback network from VOUT1 to the SS2
pin with the same ratio that sets VOUT2 voltage, absolute
tracking shown in Figure 14c is implemented. The minimum value of the top feedback resistor (R1) should be set
such that the SS pin can be driven all the way to ground
with 1.4mA of sink current when VOUT1 is at its regulated
voltage. In addition, a small VOUT2 voltage offset will be
present due to the SS2 12µA source current. This offset
can be corrected for by slightly reducing the value of R2.
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LT3692A
Applications Information
Figure 14d illustrates output sequencing. When VOUT1 is
within 10% of its regulated voltage, CMPO1 releases the
SS2 soft-start pin allowing VOUT2 to soft-start. In this case
CMPO1 will be pulled up to 2V by the SS pin. If a greater
voltage is needed for CMPO1 logic, a pull-up resistor to
VOUT1 can be used. This will decrease the soft-start ramp
time and increase tolerance to momentary shorts.
For example, assume a maximum input of 36V:
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 14e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 1.4mA of sink current
during power-up and fault conditions.
Application Optimization
In multiple channel applications requiring large VIN to
VOUT ratios, the maximum frequency and resulting inductor size is determined by the channel with the largest
ratio. The LT3692A’s multi-frequency operation allows the
user to minimize component size for each channel while
maintaining constant frequency operation. The circuit in
Figure 15 illustrates this approach. A 2-stage step-down
approach coupled with multi-frequency operation will
further reduce external component size by allowing an
increase in frequency for the channel with the lower VIN
to VOUT ratio. The drawback to this approach is that the
output power capability for the first stage is determined by
the output power drawn from the second stage. The dual
step-down application in Figure 16 steps down the input
voltage (VIN1) to the highest output voltage then uses that
voltage to power the second output (VIN2). VOUT1 must be
able to provide enough current for its output plus VOUT2
maximum load. Note that the VOUT1 voltage must be above
VIN2’s minimum input voltage as specified in the Electrical
Characteristics (typically 2.8V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the CMP01 output.
VIN = 36V, VOUT1 = 3.3V at 2A and VOUT2 = 1.2V at 1A.
Frequency (Hz) =
L=
VOUT + VD
1
•
VIN – VSW + VD tON(MIN)
( VIN – VOUT ) • VOUT
VIN • f
Single Step-Down:
Frequency (Hz) =
1.2 + 0.6
1
•
≅ 350kHz
35V – 0.4 + 0.6 140ns
L1=
(36V – 3.3) • 3.3 ≥ 8.5µH
L2 =
(36V – 1.2) • 1.2 ≥ 3.3µH
36V • 350kHz
36V • 350kHz
2-Stage Step-Down:
Frequency (Hz) =
3.3 + 0.6
1
•
≅ 750kHz
36V – 0.4 + 0.6 140ns
L1=
(36V – 3.3) • 3.3 ≥ 4.0µH
L2 =
(3.3 – 1.2) • 1.2 ≥ 1.0µH
36V • 750kHz
3.3 • 750kHz
2-Stage Step-Down Multi-Frequency:
RDIV = 100k, FREQ1 = 550kHz, FREQ2 = 2200kHz.
L1=
(36V – 3.3) • 3.3 ≥ 5.4µH
L2 =
(3.3 – 1.2) • 1.2 ≥ 0.47µH
36V • 550kHz
3.3 • 2200K Hz
In addition, RILIM2 = 33.2k reduces the peak current limit
on channel 2 to 2A, which reduces inductor size and catch
diode requirements.
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LT3692A
Applications Information
Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
PG1
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
5ms/DIV
LT3692A
FB1
CMPI1
0.72V
+
–
0.1µF
CMPO1
12µA
0.72V
+
–
FB1
CMPI1
2.5V
12µA
0.72V
SS1
2.5V
PG2
12µA
0.72V
SS2
12µA
PG1
0.72V
+
–
R4
FB2
CMPI2
2.5V
PG2
12µA
0.72V
SS2
R8
0.22µF
(14a)
PG1
VOUT2
R6
R5
CMPO2
R3
R2
CMPO1
+
–
0.1µF
R4
FB2
CMPI2
FB1
CMPI1
2.5V
VOUT2
R5
CMPO2
R1
SS1
R6
VOUT1
R3
R2
CMPO1
+
–
0.1µF
FB2
CMPI2
SS2
R1
PG1
R4
LT3692A
VOUT1
R3
R2
VOUT2
2.5V
10ms/DIV
LT3692A
R1
SS1
PG2
10ms/DIV
VOUT1
2.5V
VOUT2
0.5V/DIV
PG2
PG2
12µA
VOUT1
0.5V/DIV
PG1
PG1
CMPO2
+
–
R6
R5
PG2
R7
(14b)
(14c)
Output Sequencing
Controlled Power Up and Down
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
PG1/PG2
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
PG1
SS1/2
PG2
10ms/DIV
10ms/DIV
LT3692A
LT3692A
VOUT1
VOUT1
R1
FB1
CMPI1
2.5V
12µA
0.72V
SS1
+
–
0.1µF
R1
R2
2.5V
CMPO1
R4
12µA
SS2
0.72V
+
–
CMPO2
0.72V
SS1
+
–
VOUT2
2.5V
12µA
PG1
R5
FB2
CMPI2
FB1
CMPI1
+
–
R2
CMPO1
PG1
VOUT2
R4
R6
R5
FB2
CMPI2
2.5V
PG2
R3
12µA
SS2
0.72V
+
–
0.22µF
R6
R5
CMPO2
PG2
3692a F14
(14d)
(14e)
Figure 14. SS Pin Configurations
24
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LT3692A
Applications Information
VIN1
5.5V TO 36V
4.7µF
4.7µF
VIN2
VIN1
SHDN1
BST1
VOUT1
1.2V
3A
300kHz
4.7µH
0.47µF
SW1
SW2
IND1
IND2
4.7µH
0.47µF
VOUT2
3.3V
2A
600kHz
100k
LT3692A
VOUT2
VOUT1
100µF
×3 8.06k
100k
SHDN2
BST2
100pF
4.02k
FB1
PG1
CMPI2
CMPO1
CMPO2
SS1
DIV
33pF
49.9k
ILIM2
VC2
RT/SYNC
820pF
7.50k
15.8k
47µF
8.06k
PG2
SS2
ILIM1
VC1
0.1µF
24.9k
FB2
CMPI1
CLKOUT
TJ
GND
ILIM1
CLOCKOUT
600kHz
680pF
33pF
10nF
61.9k
0.1µF
13.0k
3692a F15
Figure 15. 3.3V and 1.2V Dual Step-Down Multi-Frequency Converter
VIN1
5.5V TO 36V
4.7µF
VIN2
VIN1
SHDN1
BST1
SHDN2
BST2
0.22µF
VOUT1
3.3V
2.5A
550kHz
100k
47µF
4.7µH
24.9k
IND1
IND2
LT3692A
VOUT2
VOUT1
FB1
8.06k
PG
33pF
CMPI2
CMPO1
CMPO2
100k
SS2
ILIM2
VC2
RT/SYNC
680pF
13k
DIV
68.1k
102k
0.5µH
4.02k
FB2
CMPI1
SS1
ILIM1
VC1
0.1µF
0.1µF
SW2
SW1
CLKOUT
GND
TJ
FB1
100pF
VOUT2
1.2V
1A
47µF 2.2MHz
8.06k
CLKOUT
2.2MHz
10nF
220pF
0.1µF
22pF
40.2k
33.2k
3692a F16
Figure 16. 3.3V and 1.2V 2-Stage Dual Step-Down Multi-Frequency Converter
3692afc
For more information www.linear.com/3692A
25
LT3692A
Applications Information
Shorted and Reverse Input Protection
If the inductor is chosen so that it won’t saturate excessively,
an LT3692A step-down regulator will tolerate a shorted
output. There is another situation to consider in systems
where the output will be held high when the input to the
LT3692A is absent. This may occur in battery charging
applications or in battery back-up systems where a battery
or some other supply is diode OR-ed with the LT3692A’s
output. If the VIN1/2 pin is allowed to float and the SHDN
pin is held high (either by a logic signal or because it is
tied to VIN), then the LT3692A’s internal circuitry will pull
its quiescent current through its SW pin. This is fine if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the VIN pin is grounded while the output
is held high, then parasitic diodes inside the LT3692A can
pull large currents from the output through the SW pin
and the VIN1/2 pin. Figure 17 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
PARASITIC DIODE
D4
VIN1/2
VIN
SW
VOUT1/2
LT3692A
VIN LT3692A SW
GND
(18a)
VIN LT3692A SW
GND
(18b)
VIN LT3692A SW
GND
(18c)
3692a F18
Figure 18. Subtracting the Current When the Switch Is On (18a)
from the Current When the Switch Is Off (18b) Reveals the Path of
the High Frequency Switching Current (18c). Keep this Loop Small.
The Voltage on the SW and BST Traces Will Also Be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit
Is Shielded with a Local Ground Plane
3692a F17
Figure 17. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output
26
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LT3692A
Applications Information
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 18
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents flow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit board and their connections should be made on that
layer. Place a local, unbroken ground plane below these
components, and tie this ground plane to system ground
at one location, ideally at the ground terminal of the output capacitor C2. Route all small signal analog returns
to the ground connection at the bottom of the package.
Additionally, the SW and BST traces should be kept as
short as possible.
Thermal Considerations
The PCB must also provide heat sinking to keep the LT3692A
cool. The exposed metal on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to other copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3692A.
DC1403A TSSOP LAYOUT
Place additional vias near the catch diodes. Adding more
copper to the top and bottom layers and tying this copper
to the internal planes with vias can further reduce thermal
resistance. The topside metal and component outlines
in Figure 19 illustrate proper component placement and
trace routing.
The LT3692A’s powerful 3.8A switches allow the converter
to source large output currents. Depending on the converter’s operating conditions, the resulting internal power
dissipation can raise the junction temperature beyond
its maximum rating. Operating conditions include input
voltages, output voltages, switching frequencies, output
currents, and the ambient environmental temperature,
etc. An estimation of the junction temperature rise above
ambient temperature helps determine whether a given
design may exceed the maximum junction ratings for
specific operating conditions. However, temperature rise
depends on PCB design and the proximity to other heat
sources. The final converter design must be evaluated
on the bench.
An estimation of the junction temperature rise begins by
determining which circuit components dissipate power.
In order to simplify the power loss estimation, only the
inductors, catch diodes, and the LT3692A will be considered
QFN LAYOUT
Figure 19. PCB Top Layer and Component Placement for TSSOP and QFN Packages
For more information www.linear.com/3692A
3692a F19
3692afc
27
LT3692A
Applications Information
as heat sources. After the operating conditions have been
determined, the individual power losses are calculated by:
V
PowerD1,2 = 1− OUT •IOUT • VFD
VIN
PowerIND1,2 = RIND •IOUT2
V
PowerCH1,2 = 0.1• OUT •IOUT2 + 2•10 –3
VIN
•VIN +
IOUT • VOUT • VBOOST
40• VIN
+
VIN IOUT
VIN •IOUT •FSW •10−6 •
+
3
0.3
where:
FSW = Switching Frequency in kHz
RIND = Inductor Resis tance
VFD = Catch Diode Forward Voltage Drop
VBOOST = Switch Boost Voltage
TRISETSSOP ≈ 10 • (PowerD1 + PowerD2 ) +
12.3 • (PowerIND1 + Power IND2) + 17.5 •
(PowerCH1 + PowerCH2 )
The estimated junction temperature rise above ambient
for the LT3692A QFN layout (see Figure 19) is:
TRISEQFN ≈ 8.5 • (Power D1+ Power D2) +
13 • (Power IND1+ Power IND2) + 23 •
(PowerCH1 + PowerCH2 )
For example, the typical application circuits listed in Table 4
are used to calculate the individual power loss contributions in Table 5. Table 6 shows the estimated power loss
and junction temperature rise above ambient temperature.
28
Table 4. LT3692A Operating Conditions
FSW
VOUT1
IOUT1
VIN
(V)
(kHz)
(V)
(A)
30
300/600
1.2
2
12
1000
3.3
2.5
24
500
5
2
12
500
5
3
VOUT2
(V)
3.3
3.3
3.3
3.3
IOUT2
(A)
2
2.5
2
3
Table 5. LT3692A Power Loss Contributions
PD1
PD2
PL1
PL2
(W)
(W)
(W)
(W)
0.86
0.80
0.24
0.24
0.82
0.82
0.25
0.25
0.71
0.78
0.24
0.24
0.79
0.98
0.54
0.54
PCH1
(W)
0.38
0.62
0.54
0.81
PCH2
(W)
0.72
0.62
0.48
0.59
Table 6. Estimated System Power Loss and IC Temperature Rise
TRISE TSSOP (°C)
TRISE QFN (°C)
PLOSS (W)
CALCULATED MEASURED CALCULATED MEASURED CALCULATED MEASURED
For the LT3692A demo board (see Figure 19) using the
TSSOP package, the estimated junction temperature rise
above ambient temperature is found by:
Note that the larger TSSOP package demonstrates better
thermal performance than the compact QFN package on
the LT3692A demo circuit boards. For LT3692A applications that favor thermal performance, the TSSOP package
is the preferred package option.
3.2
3.4
3.0
4.2
3.2
3.5
3.1
4.7
41.9
44.3
38.5
55.4
44.9
48.8
35.3
52.0
45.8
49
42.2
61.2
49.1
54.8
42.3
63
The power loss and temperature rise equations provided
in the Thermal Considerations section serve as a good
starting point for estimating the junction temperature
rise. However, the LT3692A is a very versatile converter.
The combination of independent input voltages, output
voltages, output currents, switching frequencies, and
package selections for the LT3692A dictate that no power
loss estimation scheme can accommodate every possible
operating condition. As such, it is absolutely necessary to
evaluate a converter’s performance at the bench.
The power dissipation in the other power components such
as boost diodes, input and output capacitors, inductor
core loss, and trace resistances cause additional copper
heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal
Considerations section.
3692afc
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LT3692A
Applications Information
Die Temperature and Thermal Shutdown
Generating a Negative Regulated Voltage
The LT3692A TJ pin outputs a voltage proportional to the
internal junction temperature. The TJ pin typically outputs
250mV for 25°C and has a slope of 10mV/°C. Without the
aid of external circuitry, the TJ pin output is valid from 20°C
to 150°C (200mV to 1.5V) with a maximum load of 100µA.
The simple charge pump circuit in Figure 21 uses the
CLKOUT pin output to generate a negative voltage, eliminating the need for an external regulated supply. Surface
mount capacitors and dual-package Schottky diodes
minimize the board area needed to implement the negative voltage supply.
Full Temperature Range Measurement
To extend the operating temperature range of the TJ output below 20°C, connect a resistor from the TJ pin to a
negative supply as shown in Figure 20. The negative rail
voltage and TJ pin resistor may be calculated using the
following equations:
VNEG
2 • TEMP(MIN)°C
≤
100
R1≤
VNEG
33µA
where:
330pF
D4
CLKOUT
GND
0.1µF
D3
3692 F21
Figure 21. Circuit to Generate the Negative Voltage Rail to
Extend the TJ Pin Operating Range
VNEG = Regulated negative voltage supply.
For example:
TEMP(MIN)°C = –40°C
VNEG ≤ –0.8V
VNEG = –1, R1 ≤ |VNEG|/33µA = 30.2kΩ
TJ
LT3692A
30k
D3, D4: ZETEX BAT54S
TEMP(MIN)°C is the minimum temperature where a
valid TJ pin output is required.
LT3692A
TJ
As a safeguard, the LT3692A has an additional thermal
shutdown threshold set at a typical value of 163°C for each
channel. Each time the threshold is exceeded, a power-on
sequence for that channel will be initiated. The sequence
will then repeat until the thermal overload is removed.
It should be noted that the TJ pin voltage represents
a steady-state temperature and should not be used to
guarantee that maximum junction temperatures are
not exceeded. Instantaneous power along with thermal
gradients and time constants may cause portions of the
die to exceed maximum ratings and thermal shutdown
thresholds. Be sure to calculate die temperature rise for
steady state (>1Min) as well as impulse conditions.
R1
VNEG
GND
+
3692 F20
Figure 20. Circuit to Extend the TJ Pin Operating Range
3692afc
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29
LT3692A
Applications Information
CLKOUT Capacitive Loading
A minor drawback to generating a negative rail from the
CLKOUT pin is that the charge pump adds capacitance to
the CLKOUT pin, resulting in an output synchronization
clock signal phase delay. Figures 22 and 23 show the impact of capacitive loading on the CLKOUT signal rise and
fall times. Note that a typical 10:1 150MHz oscilloscope
probe contributes significant capacitance to the CLKOUT
node, necessitating a low capacitance probe for accurate
measurements. Applications requiring CLKOUT to generate
the negative supply voltage and provide the synchronization clock to other regulators may benefit from buffering
CLKOUT prior to the charge pump circuitry.
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED LT3692A
RT/SYNC PIN
FET PROBE: 2pF
500mV/DIV
40ns/DIV
FREQUENCY: 1.000MHz
3692a F22
Figure 22. CLKOUT Rise Time
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 100
shows how to generate a dual (+ and –) output supply
using a buck regulator.
SCOPE PROBE: 15pF
CHARGE PUMP
SYNCHRONIZED
LT3692A RT/SYNC PIN
500mV/DIV
FET PROBE: 2pF
20ns/DIV
FREQUENCY: 1.000MHz
3692a F23
Figure 23. CLKOUT Fall Time
30
3692afc
For more information www.linear.com/3692A
VIN
6V TO 36V
For more information www.linear.com/3692A
0.1µF
VOUT1
5V 1.5A
500kHz
100k
47µF
4.7µF
33pF
8.06k
680pF
10.0k
100pF
0.47µF
61.9k
42.2k
6.8µH
VIN2
IND2
SW2
SHDN2
BST2
102k
DIV
GND
TJ
CLKOUT
ILIM1
VC1
RT/SYNC
SS2
ILIM2
VC2
SS1
CMPO2
CMPO1
FB2
CMPI2
CMPI1
FB1
LT3692A
VOUT2
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
10nF
16.9k
1.5µH
33pF
330pF
11.0k
8.06k
100pF
0.1µF
49.9k
PG
100k
8.06k
10k
CLOCKOUT
2MHz
22µF
VOUT2
2.5V 1A
2MHz
8.06k
4.02k
VOUT3
1.2V 1A
1MHz
49.9k
33pF
8.06k
100µF
0.1µF
4.02k
9.76k
470pF
100pF
1.5µH
1µF
VIN2
IND2
SW2
SHDN2
BST2
61.9k
DIV
FB2
ILIM2
VC2
SS2
CMPO2
CMPI2
TJ
CLKOUT
GND
RT/SYNC
ILIM1
VC1
SS1
CMPO1
CMPI1
FB1
LT3692A
VOUT2
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
Quad Output 5V, 2.5V, 1.8V and 1.2V Multi-Frequency Synchronized, 2-Stage Converter
with Output Sequencing, Absolute Tracking and Current Limiting
10nF
10k
1.5µH
15.0k
220pF
100pF
0.1µF
8.06k
33pF
1µF
3692a TA02
49.9k
VOUT4
1.8V 1A
47µF 2MHz
LT3692A
Typical Applications
3692afc
31
LT3692A
TYPICAL APPLICATIONS
3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter
VIN
5.5V TO 36V
4.7µF
VIN2
VIN1
SHDN1
BST1
8.2µH
0.47µF
VOUT1
3.3V 2.5A
400kHz 100µF
SHDN2
BST2
SW1
SW2
IND1
IND2
100pF
24.9k
FB1
FB2
CMPI1
CMPI2
CMPO1
CMPO2
SS1
DIV
33pF
16.5k
ILIM2
VC2
RT/SYNC
470pF
47.5k
102k
10k
47µF
100pF
100k
VOUT2
1.8V
1A
1600kHz
8.06k
PG
SS2
ILIM1
VC1
100k
0.22µF
LT3692A
VOUT2
VOUT1
8.06k
0.1µF
1µH
CLKOUT
GND
TJ
0.1µF
CLOCKOUT
1600kHz
330pF
33pF
10nF
36.5k
40.2k
3692a TA03
32
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For more information www.linear.com/3692A
LT3692A
TYPICAL APPLICATIONS
12V to 3.3V and 2.5V Converter with Start-Up Current Limiting
VIN
12V
4.7µF
4.7µF
VIN2
VIN1
SHDN1
BST1
2.2µH
0.22µF
VOUT1
2.5V
3A
1MHz
SHDN2
BST2
SW1
SW2
IND1
IND2
0.22µF
LT3692A
VOUT2
VOUT1
47µF
8.06k
100pF
16.9k
FB1
FB2
CMPI1
CMPI2
CMPO1
CMPO2
ILIM2
VC2
ILIM1
VC1
0.1µF
RT/SYNC
330pF
DIV
33pF
0.1µF
21.0k
28.0k
24.9k
100pF
8.06k
47µF
VOUT2
3.3V
3A
1MHz
SS2
SS1
120k
2.2µH
CLKOUT
GND
TJ
CLOCKOUT
1MHz
33pF
0.1µF
330pF
10nF
24.9k
0.1µF
120k
3692a TA04
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For more information www.linear.com/3692A
33
LT3692A
TYPICAL APPLICATIONS
3.3V/5A Single Output with UVLO/OVLO and Power Good
VIN
5.5V TO 18V
60V TRANSIENT
4.7µF
×2
13k
174k
7.15k
37.4k
SHDN2
BST1
CMPI2
CMPO2
51.1k
ILIM1
ILIM2
820pF
33pF
SW1
CLOCKOUT
1MHz
SS1
VOUT2
SS2
VC1
BST2
SW2
CLKOUT
10nF
20k
28k
DIV
47µF
×2
GND
FB1
CMPI1
FB2
VOUT
3.3V
5A
2MHz EFFECTIVE RIPPLE
0.22µF
3.3µH
IND2
RT/SYNC
TJ
0.1µF
0.22µF
3.3µH
IND1
LT3692A
VOUT1
VC2
Q1
2N3904
34
VIN2
VIN1
SHDN1
24.9k
8.06k
CMPO1
100k
PG
3692a TA05
3692afc
For more information www.linear.com/3692A
LT3692A
TYPICAL APPLICATIONS
Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter
VIN1
12V
4.7µF
47.5k
13k
2.2µF
VIN2
VIN1
SHDN1
SHDN1
SHDN2
BST1
CMPO1
CMPO2
SW1
VIN2
5V
2A MAX
0.22µF
2.2µH
IND1
LT3692A
SS2
VOUT1
SS1
0.1µF
64.9k
36.5k
33pF
680pF
21.0k
CLOCKOUT
2MHz
61.9k
61.9k
ILIM1
VOUT2
ILIM2
VC1
BST2
SW2
VC2
0.22µF
2.2µH
IND2
CLKOUT
RT/SYNC
DIV
FB1
CMPI1
FB2
TJ
CMPI2
10nF
47µF
×2
GND
VOUT
3.3V
4A
24.9k
8.06k
3692a TA06
3692afc
For more information www.linear.com/3692A
35
LT3692A
TYPICAL APPLICATIONS
5V and 1.8V Dual 2-Stage Converter
VIN1
6V TO 36V
4.7µF
VIN2
VIN1
SHDN1
BST1
4.7µH
0.22µF
VOUT1
5V
1A
1MHz
SHDN2
BST2
SW1
SW2
IND1
IND2
1µH
0.22µF
LT3692A
VOUT2
VOUT1
22µF
100k
42.2k
8.06k
PG
FB1
CMPI2
CMPO1
CMPO2
SS1
0.1µF
49.9k
10k
ILIM2
VC2
RT/SYNC
DIV
33pF
61.9k
61.9k
FB1
47µF
100pF
8.06k
SS2
ILIM1
VC1
680pF
10k
FB2
CMPI1
VOUT2
1.8V
1A
2MHz
CLKOUT
GND
TJ
ILIM1
CLOCKOUT
2MHz
33pF
0.1µF
330pF
10nF
39.2k
3692a TA07
36
3692afc
For more information www.linear.com/3692A
100k
0.1µF
PG1
VOUT1
12V 0.5A
1MHz
37.6k
33pF
470pF
8.06k
22µF
0.47µF
VIN
15V TO 36V
28k
113k
1k
10µH
OFF ON
4.7µF
IND2
SW2
SHDN2
BST2
VIN2
FB2
DIV
GND
TJ
CLKOUT
ILIM2
VC2
ILIM1
VC1
RT/SYNC
SS2
CMPO2
CMPI2
SS1
CMPO1
CMPI1
FB1
LT3692A
VOUT2
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
24.9k
10nF
FB1
3.3µH
SHDN1
33pF
16.0k
330pF
8.06k
0.22µF
100k
47µF
For more information www.linear.com/3692A
133k
0.1µF
0.1µF
SS2
VOUT3
1.2V 3A
1MHz
OUT2
MOD
GND
SET
OUT1
U1
LTC6908-1
V+
VOUT2
3.3V 2A
1MHz
VOUT2
100k
8.06k
100µF
0.22µF
33pF
150pF
4.99k
1nF
SS2
4.02k
1.5µH
SHDN1
1µF
IND2
SW2
SHDN2
BST2
VIN2
GND
TJ
CLKOUT
DIV
RT/SYNC
FB2
CMPI2
CMPO2
SS2
ILIM2
VC2
CMPI1
CMPO1
SS1
ILIM1
VC1
FB1
LT3692A
VOUT2
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
12V, 3.3V, 2.5V, 1.2V Quad Output with External Synchronization, Output Sequencing and Tracking Application
10nF
SS2
16.9k
2.2µH
SHDN1
33pF
8.06k
VOUT2
3692a TA08
100k
47µF
VOUT4
2.5V 3A
1MHz
330pF
11.2k
100pF
0.22µF
1µF
LT3692A
TYPICAL APPLICATIONS
37
3692afc
LT3692A
TYPICAL APPLICATIONS
5V, 3.3V, 2.5V, 1.8V Synchronized Quad Output
VOUT1
5V
1A
2.2µF
SVIN
PVIN2
PVIN
DDR
4.7µF
×2
RUN LT3612
MODE
RT
VIN2
VIN1
SHDN1
BST1
6.8µH
0.22µF
100pF
42.2k
8.06k
SW1
SW2
IND1
IND2
FB1
FB2
CMPI1
CMPI2
CMPO1
SS1
CMPO2
SS2
ILIM2
VC2
ILIM1
VC1
0.1µF
RT/SYNC
330pF
DIV
33pF
60.4k
24.9k
16k
270k
FB
VOUT2
3.3V
100µF 2A
ITH
TRACK/SS
SGND
PGND
SVIN
PVIN2
60.4k
SHDN2
BST2
6.8µH
2.2µF
0.22µF
LT3692A
VOUT2
VOUT1
47µF
3.3µH
SW
PGOOD
VIN1
7V TO 36V
TJ
0.1µF
RUN LT3612
100k
ILIM1
VC1
MODE
100°C
TEMP FLAG
SS1
RT
3.3µH
SW
PGOOD
47µF
FB1
CLKOUT
GND
PVIN
DDR
191k
FB
VOUT3
2.5V
100µF 2A
ITH
TRACK/SS
SGND
PGND
SVIN
PVIN2
60.4k
CLOCKOUT
600kHz
2.2µF
28k
73.2k
R14
49.9k
PVIN
DDR
PGOOD
RUN LT3612
MODE
RT
SGND
3.3µH
SW
121k
FB
VOUT4
1.8V
100µF 2A
ITH
TRACK/SS
60.4k
PGND
0.1µF
3692 TA09
38
3692afc
For more information www.linear.com/3692A
LT3692A
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3692afc
For more information www.linear.com/3692A
39
LT3692A
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
40
0.25 ± 0.05
0.50 BSC
3692afc
For more information www.linear.com/3692A
LT3692A
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
9/11
Added H-grade
2 to 4
B
4/12
Clarified the synchronization maximum frequency and Typical Application.
1
Clarified the Electrical Characteristics table.
4
Clarified the DIV Voltage Threshold vs Temperature graph.
7
Replaced 90mV with 100mV.
12
Clarified Table 1.
13
Replaced DIV resistor values in the applications schematics.
C
3/13
25, 31, 32
Added VIN1 Quiescent Current vs SHDN1 Voltage Graph
6
Clarified SHDN1/2 Pin Function Description
10
Clarified SHDN pin operation in Applications Information operation in general description
11
Clarified SHDN pin operation description in Applications Information
21
3692afc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
Forofmore
information
www.linear.com/3692A
41
LT3692A
Typical Application
FMEA Fault Tolerant 3.3V/2A and 5V/2A Dual Converter
VIN1
6V TO 36V
(60V TRANSIENT)
4.7µF
SHDN2
6.8µH
0.22µF
VOUT1
5V
2A
500kHz
VIN1
SHDN1
BST1
4.7µF
100k
VIN2
SHDN2
BST2
SW1
SW2
IND1
IND2
5.6µH
0.22µF
VOUT2
3.3V
2A
500kHz
LT3692A
VOUT2
VOUT1
4.22k
47µF
249k
806Ω
PG1
SS2
ILIM2
FB1
CMPI2
CMPO1
CMPO2
SS1
820pF
12.7k
10nF
ILIM1
VC1
DIV
100µF
806Ω
249k
PG2
SS2
ILIM2
VC2
RT/SYNC
33pF
2.49k
FB2
CMPI1
CLKOUT
GND
TJ
CLOCKOUT
500kHz
13.0k
10nF
680pF
15.4k
33pF
22nF
49.9k
3692a TA10
Related Parts
PART NUMBER
DESCRIPTION
LT3692
36V with Transient Protection to 60V, Dual 3.5A, 2.5MHz, High Efficiency VIN = 3V to 36V, Transients to 60V, VOUT(MIN) = 0.8V,
IQ = 4mA, ISD
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