LT3710
Secondary Side
Synchronous Post Regulator
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FEATURES
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■
■
■
■
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DESCRIPTIO
The LT®3710 is a high efficiency step-down switching
regulator intended for auxiliary outputs in single secondary winding, multiple output power supplies.
Generates a Regulated Auxiliary Output in Isolated
DC/DC Converters
0.8V ±1.5% Accurate Voltage Reference
Dual N-Channel MOSFET Synchronous Drivers
High Switching Frequency: Up to 500kHz
Programmable Current Limit Protection
Programmable Soft-Start
Automatic Frequency Synchronization
Small 16-Pin Thermally Enhanced TSSOP Package
The LT3710 drives dual synchronous N-channel MOSFETs
and achieves high efficiency. With leading edge modulation, it operates well with either primary side peak current
or voltage mode control. It is synchronized to the falling
edge of the transformer secondary winding and can be
used in both single-ended and double-ended isolated
power converter topologies. A high speed operational
amplifier is incorporated to achieve optimum compensation and fast transient response. A user selectable discontinuous conduction mode improves light load efficiency.
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APPLICATIO S
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■
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48V Isolated DC/DC Converters
Multiple Output Supplies
Offline Converters
The LT3710 is available in a thermally enhanced TSSOP-16
exposed pad power package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
VOUT1
3.3V
AT 10A
L1
VIN
36V
TO 72V
VCC
BIAS
10k
VCC BOOST
VDD
•
•
CMDSH-3
SYNC GBIAS
VCOMP
10pF
CG
4.7µF
LT3710
VFB
CS
680pF
FG
CSET
Q1
TG
L2
1.8µH
0.1µF
0.006Ω
SW
ISNS
LTC1698
10k
180pF
TG BG
LT3781
SG
•
•
+
Q2
ILCOMP BG
0.01µF
SS
B340A
VOUT2
1.8V
AT 10A
COUT2
4700pF
VAOUT
BGS
SYNC
3.3k
3.01k
220Ω
33nF
VFB
PGND
CL– CL+
2.32k
3710 F01
OPTODRV
VC
+
–
VREF
GND
VFB
ISOLATION
BOUNDARY
COUT2: POSCAP, 680µF/4V
L2: SUMIDA CEP125-IR8MC-H
Q1, Q2: SILICONIX Si7440DP
PLEASE REFER TO FIGURE 3
IN THE APPLICATIONS SECTION
FOR THE COMPLETE SCHEMATIC
Figure 1. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
3710f
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LT3710
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC Supply Voltage .................................................. 26V
BOOST Pin Voltage With Respect to SW pin ........... 10V
BOOST Pin Voltage With Respect to GND pin .......... 35V
SYNC Pin Voltage .................................................... 30V
Operating Junction Temperature Range
(Notes 2, 3) ...................................... – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
BOOST
1
16 GBIAS
TGATE
2
15 BGATE
SW
3
14 PGND
CSET
4
SYNC
5
12 CL–
ILCOMP
6
11 CL+
SS
7
10 VAOUT
VFB
8
9
Note: If higher than 30V on SYNC pin is needed, add a 10k resistor in series with the pin.
17
LT3710EFE
13 VCC
FE PART
MARKING
BGS
FE PACKAGE
16-LEAD PLASTIC TSSOP
3710EFE
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD IS SGND (PIN 17) MUST BE
CONNECTED TO PGND AND SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs
unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Overall
Supply Voltage (VCC)
●
8
24
V
Supply Current (IVCC)
VAOUT ≤ 1.2V (Switching Off)
7
12
mA
Boost Pin Current
VBOOST = VSW + 8V, 0V ≤ VSW ≤ 24V
TGATE High
TGATE Low
2
2
3
3
mA
mA
0.8
0.812
0.820
V
V
0.2
0.5
µA
Voltage Amplifier VA
Reference Voltage (VREF)
●
FB Pin Input Current
0.788
0.780
VFB = VREF
VAOUT High
4.5
V
VAOUT Low
0.8
V
VAOUT Source Current
●
100
Open-Loop Gain
300
100
Gain Bandwidth Product
dB
10
Soft-Start Current
µA
MHz
18
µA
70
85
mV
8
15
mV
5
12
50
0
Current Limit Amplifier CA1
Current Limit Threshold at (VCL+ – VCL–)
Common Mode Voltage from 0V to VCC – 2.5V
BGATE Off Threshold at (VCL+ – VCL–), BGS Pin Float
Common Mode Voltage from 0V to VCC – 2.5V
Switching Off Threshold at ILCOMP
VILCOMP
Input Current (CL+, CL–)
VCL+ = VCL–
●
0.15
100
V
µA
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LT3710
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs
unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
280
240
340
kHz
kHz
400
500
kHz
kHz
Oscillator
Switching Frequency
CS = 500pF (No SYNC)
CS = 333pF (No SYNC)
●
●
170
240
Synchronization Frequency Range
CS = 500pF
CS = 333pF
●
●
245
345
CSET Ramp Valley Voltage
CS = 1000pF (No SYNC)
CSET Peak-to-Peak Voltage
CS = 1000pF (No SYNC)
2.4
V
Synchronization Pulse Threshold on SYNC Pin
Falling Edge VSYNC
2.5
V
Maximum Duty Cycle
VFB = VREF – 5mV, CS > 500pF
●
85
90
%
VGBIAS
IGBIAS < 25mA
●
7.5
8.0
VTGATE High (VTGATE – VSW)
ITGATE < 50mA, VBOOST = VGBIAS – 0.5V
●
5
VBGATE High
IBGATE < 50mA
●
5
VTGATE Low (VTGATE – VSW)
ITGATE < – 50mA
●
VBGATE Low
IBGATE < – 50mA
●
Peak Gate Drive Current
10nF Load
1
A
Gate Drive Rise and Fall Time
1nF Load
25
ns
0.90
1.15
1.4
V
Gate Drivers (TGATE, BGATE)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3710E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the – 40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
8.5
V
6
7
V
6
7.5
V
0.5
V
0.5
V
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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TYPICAL PERFOR A CE CHARACTERISTICS
VGBIAS vs IGBIAS over Junction
Temperature
Voltage Amplifier VA Gain and
Phase
ICC vs VCC (Switching Off)
8.1
13
120
TA = 25°C
–40°C
–0
TA = 25°C
12
11
7.9
10
9
8
–50
(–111°)
PHASE
40
–100
7
7.8
125°C
7.7
GAIN
80
GAIN (dB)
ICC (mA)
25°C
PHASE (DEG)
VGBIAS (V)
8.0
0
10
IGBIAS (mA)
0
6
20
26
3710 G01
5
–150
0dB, 10MHz
–20
8
10
12
14
16 18
VCC (V)
20
22
24
3710 G02
10
100
1k
10k 100k 1M
FREQUENCY (Hz)
–180
10M 100M
3710 G03
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LT3710
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TYPICAL PERFOR A CE CHARACTERISTICS
∆VREF vs VCC, ∆FREQ vs VCC
VREF vs Temperature
0.801
CSET = 500pF
2
0.800
1
∆VREF
VREF (V)
∆VREF (mV)
CSET = 500pF
3 TA = 25°C
0
1
∆FREQ
0
–1
10
15
VCC (V)
20
∆FREQ (kHz)
–1
0.799
0.798
–40
25
–20
0
25
50
75
JUNCTION TEMPERATURE (°C)
3710 G04
3710 G05
Frequency vs Temperature
195
125
CSET vs Switching Frequency
500
CSET = 500pF
TA = 25°C
0.95
400
FREQUENCY (kHz)
200
205
210
MAXIMUM DUTY CYCLE
0.90
0.85
300
0.80
0.75
200
MAXIMUM DUTY CYCLE
SWITCHING FREQUENCY (kHz)
1.00
CSET
0.70
215
–40
–20
0
25
50
75
JUNCTION TEMPERATURE (°C)
100
200
125
400
600
CSET (pF)
800
3710 G06
1000
3710 G07
Current Limit Amplifier CA1 Gain
at VCC = 11V, VCL– = 5V
GBIAS vs IGBIAS (Charging 2.2µF)
8
12
VCC = 11V
7 VCLN = 5V
TA = 25°C
10
6
200
8
5
150
6
100
4
300
VGBIAS
IGBIAS
50
VGBIAS (V)
IGBIAS (mA)
250
VAOUT (V)
CGBIAS = 2.2µF
4
CSET PEAK
3
2
2
0
1
CSET VALLEY
0
0
500µs
TIME
1ms
3710 G08
0
50
60
70
80
VCL+ – VCL– (mV)
90
3710 G09
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LT3710
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PI FU CTIO S
BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin
is used to bootstrap and supply the topside power switch
gate drive circuitry. In normal operation VBOOST is powered
from the internally generated 8V GBIAS, VBOOST = VSW +
8.2V when TGATE is on.
TGATE (Pin 2): Topside (Boosted) N-Channel MOSFET
Driver. When TGATE is on, the voltage is equal to VSW + 6V.
SW (Pin 3): Switch Node Connection to Inductor.
CSET (Pin 4): Oscillator Timing Pin. The capacitor on this
pin sets the PWM switching frequency.
SYNC (Pin 5): Synchronization Input. This pin should be
connected to the secondary side output of the power
transformer with a series resistor. A filtering capacitor of
10pF is recommended.
ILCOMP (Pin 6): Current Limit Amplifier Compensation
Node. At current limit, CA1 pulls down on this pin to
regulate the output current.
SS (Pin 7): Soft-Start. A capacitor on this pin sets the
output ramp up rate. The typical time for SS to reach the
programmed level is (C • 0.8V)/10µA.
VFB (Pin 8): Voltage Amplifier Inverting Input. A resistor
divider to this pin sets the output voltage. Nominal voltage
at this pin is 0.8V.
BGS (Pin 9): Bottom Gate Switching Control. CA2 monitors the inductor current and prohibits BGATE from turning on when the inductor current is low (below 8mV across
the current sense resistor RS1) to allow discontinous
mode operation. Grounding this pin disables comparator
CA2.
VAOUT (Pin 10): Voltage Amplifier Output.
CL+ (Pin 11): Current Limit Amplifier Positive Input. The
threshold is set at 70mV.
CL– (Pin 12): Current Limit Amplifier Negative Input.
When used, CL– is connected to the output capacitor side
of the current + sense resistor and CL+ is connected to the
inductor side of the current sense resistor.
VCC (Pin 13): Supply of the IC. For proper bypassing, a low
ESR capacitor is required.
PGND (Pin 14): Ground of the Bottom Side N-Channel
MOSFET Driver.
BGATE (Pin 15): Bottom Side N-Channel MOSFET Driver.
GBIAS (Pin 16): 8V Regulator Output for Boostrapping
VBOOST . A bypass capacitor of at least 2µF is needed.
Exposed Pad (Pin 17): Connect to PGND (Pin 14).
3710f
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RS
10k
C5
500pF
CSET
CS
10pF
SYNC
D1
R7
4
5
2.5V
+
–
SGND
+
C8
2µF
R8
17
E4
13
A7
8V
A1
+
+
–
A2
ONE
SHOT
RESET
E2
R
OSC
S
SHUTDOWN
NOTE: EXPOSED PAD (PIN 17) IS SGND
AND MUST BE CONNECTED TO PGND (PIN 14).
D2
Q1
VCC
–
D5
PWM
1.6V
3.5V
2.5V
SS
SW
BGATE
+
VS
+
+
+
CA1
–
+
+
–
+
–
+
–
70mV
+
8mV
A11
A6
A10
A3
–
+
5V
CA2
+
I1
10µA
A5
A4
VA
2V
+
+
–
I2
200µA
–
A8
7
D7
D6
7V
SS
C7
5nF
D4
+
8V
VREF
0.8V
R2
+
R1
8
10
6
12
11
9
14
15
16
3
2
1
VFB
VAOUT
ILCOMP
CL–
CL+
BGS
PGND
BGATE
C3
2µF
GBIAS
SW
TGATE
BOOST
D3
R5
2k
C1
500pF
C2
0.3µF
IL
L1
C6
100pF
R6
5k
M2
M1
RS1
3710 BD
R4
R3
C4
2nF
IO
VOUT2
COUT
100µF
LT3710
BLOCK DIAGRA
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LT3710
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OPERATIO
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series.
until the ramp signal intersects the feedback error amplifier output VAOUT. The top MOSFET M1 turns on, pulling
the switch node voltage to VS. The inductor current of the
LT3710 circuit is then charged by VS – VOUT2. The effective
on time of this buck circuit ends when the secondary
voltage becomes zero. The next cycle repeats.
By generating the auxiliary output(s) from the secondary
winding of the main output, the LT3710 allows for parallel
processing of the output power. This minimizes the main
output inductor size and directly regulates the auxiliary
output. With synchronous rectification, the system efficiency is greatly improved.
The ideal equation for duty cycle of the LT3710 is:
Refering to the Block Diagram, the LT3710 basic functions
include a voltage amplifier, VA, to regulate the output
voltage to within typically 1.5%, a voltage mode PWM with
trailing edge synchronization and leading edge modulation, a current limit amplifier, CA1, and high speed synchronous switch drivers.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage VS. The internal oscillator is reset, turning off the
top MOSFET M1 and turning on the bottom MOSFET M2.
During this portion of the cycle, the inductor current is
discharged by the output voltage VOUT2. The transformer
secondary voltage VS will go high during this portion of the
cycle. Since M1 is off, the switch node voltage VSW
remains zero. The inductor current continues to be discharged by the output voltage VOUT2. This condition lasts
D2 = VOUT2/VSP
where VOUT2 is the auxiliary output voltage, VSP is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage VSW, as defined in
Figure 2.
VRESET
T
D1T
TRANSFORMER
SECONDARY VOLTAGE
VS
VSP
SYNC SIGNAL VRESET
RAMP VCSET
VAOUT
TGATE
BGATE
IL
T
SWITCH NODE VSW
D2 T
VSP
3710 F02
Figure 2. Leading Edge Modulation,
Trailing Edge Synchronization
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APPLICATIO S I FOR ATIO
Synchronization and Oscillation Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to keep the transformer primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
fOSC < (fSL • 0.8)
fSL is the low limit of the system switching frequency and
0.8 is the tolerance of fOSC.
For example, a system of 200KHz with 15% tolerance,
then fSL = 200k • 85% = 170kHz; and fOSC < (170k • 0.8),
fOSC should be set below 136kHz.
Once fOSC is determined, CSET can be calculated by
CSET = (107250pf/fOSC(kHz)) – 50pF.
For fOSC = 100kHz, CSET = 1022.5pF.
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LT3710
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APPLICATIO S I FOR ATIO
Output N-Channel MOSFET Drivers
The LT3710 employs high speed N-channel MOSFET
synchronous drivers to achieve high system efficiency.
GBIAS is the 8V regulator output to bias and supply the
drivers and should be properly bypassed with a low ESR
capacitor to ground plane. A Schottky catch diode is
required on the switch node.
Light Load Operation
If the BGS pin is grounded, the LT3710 stays in continuous
mode independent of load condition except in soft-start
operation (see Soft-Start section). If the BGS pin is left
open, under light load and VRS1 drops below 8mV, BGATE
will be turned off(see comparator CA2 of Block Diagram)
and the LT3710 goes into discontinous mode operation.
Current Limit
Current limit is set by the 70mV threshold across CL+ and
CL –, the inputs of the amplifier CA1. By connecting an
external resistor RS1(see Block Diagram), the current
limit is set for 70mV/RS1. R6 and C6 stablize the current
limit loop. If current limit is not used, both CL+ and CL –
should be grounded and the BGS pin should also be
grounded to disable comparator CA2.
Soft-Start and Shutdown
During soft-start, VSS is the reference voltage that controls
the output voltage and the output ramps up following VSS.
The effective range of VSS is from 0V to VREF. The typical
time for the output to reach the programmed level is
(C • 0.8V)/10µA.
During start up, BGATE will stay off until VSS gets up to
1.6V. This prevents the bottom MOSFET from turning on
if the output is precharged.
To shut down the LT3710, the SS pin should be pulled
below 50mV by a VN2222 type N-channel transistor. Note
that during shutdown BGATE will be locked off when VSS
drops below 0.6V. This prevents the bottom MOSFET from
discharging the output, which would cause the output to
undershoot below ground.
Layout Considerations
For maximum efficiency, the switching rise and fall times
are less than 20ns. To prevent radiation, the power
MOSFETs, SW pin and input bypass capacitor leads should
be kept as short as possible. A ground plane should be
used under the switching circuitry to prevent interplane
coupling and to act as a thermal spreading path. Note that
the bottom metal of the package is the heat sink, as well as
the IC signal ground, and must be soldered to the ground
plane.
Output Voltage Programming
The feedback reference voltage is 0.8V. The output voltage
can be easily programmed by the resistor divider, R3 and
R4, as shown in the Block Diagram.
R3
VOUT2 = 0.8 • 1 +
R4
Filtering on the SYNC Input
It is necessary to add RC filtering on the SYNC input of the
LT3710 to eliminate the negative glitch at the turn on of the
top MOSFET. When the top MOSFET M1 turns on, the
transformer secondary current instantly changes from the
original first output inductor current to the sum of two
output inductor currents. The high di/dt on the transformer leakage inductance causes the transformer secondary voltage VS to drop for a short interval. If the leakage
inductance is large enough, the VS dip will be lower than
the synchronization threshold (about 2.5V), falsely triggering the synchronization. The top MOSFET is turned off
immediately. As a result, the output voltage will not be
regulated properly.
A filter circuit is needed to ensure proper operation. A
small RC filter with RS = 10k and CS = 10pF are typical.
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LT3710
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APPLICATIO S I FOR ATIO
Output Inductor Selection
The key parameters for choosing the inductor include
inductance, RMS and saturation current ratings and DCR.
The inductance must be selected to achieve a reasonable
value of ripple current, which is determined by:
VOUT2 • (1 − D2)
∆IL =
f •L
Typically, the inductor ripple current is designed to be
20% to 40% of the maximum output current.
The RMS current rating must be high enough to deliver the
maximum output current. A sufficient saturation current
rating should prevent the inductor core from saturating.
These two current ratings can be determined by:
∆ILMAX2
IRMS ≥ IO +
12
∆I
ISAT ≥ IO + LMAX
2
2
where IO is the maximum output current and ∆ILMAX is the
maximum peak-to-peak inductor ripple current.
To optimize the efficiency, we usually choose the inductor
with the minimum DCR if the inductance and current
ratings are the same.
Power MOSFET Selection
The LT3710 drives two external N-channel MOSFETs to
deliver high currents at high efficiency. The gate drive
voltage is typically 6.5V. The key parameters for choosing MOSFETs include drain to source voltage rating VDSS
and RDS(ON) at 6.5V gate drive. Note that the transformer
secondary voltage waveform will overshoot at its rising
edge due to the ringing between transformer leakage
inductance and parasitic capacitance. The VDSS of both
top and bottom MOSFETs must be sufficiently higher
than the maximum overshoot. It is recommended that an
RC snubber or a voltage clamping circuitry be placed
across the transformer secondary winding to limit the VS
overshoot.
The RDS(ON) of the MOSFETs should be selected to deliver
the required current at the desired efficiency as well as to
meet the thermal requirement of the MOSFET package.
The conduction power losses of the MOSFETs are:
PM1 ≅ IO2 • RDS(ON)M1 • D2
PM2 ≅ IO2 • RDS(ON)M2 • (1 – D2)
where IO is the maximum output current of LT3710 circuit,
RDS(ON)M1 and RDS(ON)M2 are the on-resistance for the top
and bottom MOSFETs, respectively. The RDS(ON) must be
determined with 6.5V gate drive and the expected operating temperature.
A good number of high performance power MOSFET
selections are available from Siliconix, International Rectifier and Fairchild. If the VDSS and RDS(ON) ratings are the
same, the MOSFETs with the lowest gate charge QG should
be chosen to minimize the power loss associated with the
MOSFET gate drives, the switching transitions and the
controller bias supply.
Output Capacitor Selection
The selection of the output capacitor is determined by the
output ripple and load transient requirements. In low
output voltage applications, always choose capacitors
with low ESR. The output ripple voltage is approximated
by:
1
∆VOUT ≈ ∆IL ESR +
8fC OUT
where ∆IL is the inductor peak-to-peak ripple current.
A partial list of low ESR high performance capacitor types
includes SP capacitors from Panasonic and Cornell Dubilier,
POSCAPs and OS-CON capacitors from Sanyo, T510 and
T520 surface mount capacitors from Kemet.
Design Example
Figure 3 shows an application example for the LT3710. It
is a dual output, high efficiency, isolated DC/DC power
supply with 36V to 72V input, 3.3V/10A and 1.8V/10A
outputs. The basic power stage topology is a 2-transistor
3710f
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ON/OFF
FZT
853
1.24k
1
2
13
20
1nF
1µF
5VREF
5
6
52.3k
1%
FSET
0.1µF
SHDN 5VREF
OVLO
VCC VBST
BAS21
DO1608C-105
19
18
15
11
82pF
3
7
4.7nF
4
8
5
7
6
5VREF
0.1µF
8
4 3
1•
4
2
VOUT1
0.01µF
14
5
12
11
10Ω
16 2
6
VAUX
LTC1698
MARGIN
OVPIN
VFB
3
4
10
PGND GND PWRGD ICOMP
0.1µF
OPTODRV
SYNC
1µF
13
7
9
8
+
B0540W
Si7440DP
470µF
4V
POSCAP
2.5µH
SUMIDA CEP125-2R5
+
1.24k
1%
2.43k
1%
1.78k
1%
3.01k
1%
NOTE UNLESS NOTED:
ALL CAPS 25V
ALL RESISTORS 0.1W, 5%
Q1, Q2 SILICONIX Si7456DP
0.22µF
B0540W
22nF
470Ω
1nF
CMPZ5240B
10V
10Ω
1nF
100V
2k
1nF
100V
SEC
VDD ISNS ISNSGND FG CG VCOMP
1
4.7µF
FZT690B
2.2nF
250VAC
Si7440DP
×2
5
7
VCCS
1µF
4.7k
15
3
4.7nF
1k
220pF
1
•8
4
2
MUR120S
7
T2
PULSE
P2033
0.025Ω
1/2W
Q2
BAT54
3.3Ω
1k
3.3nF
3k
10Ω
10
9
PGND 12
SG
14
BAS21
THERM SYNC SGND SS VC VFB
LT3781
TG BSTREF BG SENSE
10k
BAS21
BAT54
ZVN3310F
BAT54
330pF
MUR120S
Q1
T1
PULSE
PA0191
1
•
470µF
4V
POSCAP
Figure 3a. 36V to 72V DC to 3.3V/10A and 1.8V/10A (or 2.5V/10A) Dual Output Isolated Power Supply-Basic Circuit (Part 1 of 2, See Next Page)
4.7µF
0.1µF
10k
1N4148
270k
73.2k
11V
MMSZ5241B
20k
B0540W
VIN–
1.5µF
100V
1.5µF
100V
•
•
3710 F03a
VOUT1
TRIM
VOUT
RTN
VOUT1+
3.3V
AT 10A
U
U
10
W
VIN+
APPLICATIO S I FOR ATIO
U
1.2µH
COILCRAFT
D01813P-122HC
LT3710
3710f
LT3710
U
U
W
U
APPLICATIO S I FOR ATIO
forward converter with synchronous rectification. The
primary side controller uses an LT3781, a current mode
2-transistor forward controller with built-in MOSFET drivers. On the secondary side, an LTC1698 is used to provide
the voltage feedback for the 3.3V output, as well as the gate
drive for the synchronous MOSFETs. The error amplifier
output is fed into the optocoupler and then relayed to
LT3781 on the primary side to complete the 3.3V regulation. The 1.8V output is generated by the LT3710 circuit.
A planar transformer PA0191 built by Pulse Engineering is
employed as the power transformer in this design. This
transformer is constructed on a PQ20 core with a nine turn
primary winding, two turn secondary winding and seven
turn auxiliary winding for the LT3781 bias supply. Because
10pF
10k
SEC
7
0.01µF
VCCS
1µF
13
4
C37 680pF
14
6
180pF
10k
17
SS
GBIAS
TGATE
VCC
LT3710
CSET
Si7440DP
CMDSH-3
BOOST
SYNC
The switching frequency of the circuit is about 230kHz.
1500V input to output isolation is provided. Additional
features of this design include primary side on/off control,
±5% secondary side trimming on the 3.3V output, input
overvoltage protection and undervoltage lockout. The
complete design will mount within a standard half brick PC
board with about half inch height.
0.1µF
16V
4.7µF
16V
1
5
the maximum secondary voltage VSP is about 16V, 30V
MOSFETs are chosen with the consideration that the
secondary voltage overshoot is typically 20% to 30% of
VSP. In this particular design, Si7440DP is selected due to
its low RSD(ON), 30V VDSS rating and its compact and
thermally enhanced PowerPak SO-8 package.
SW
BGATE
PGND
BGS
ILCOMP
CL+
16
1.8µH
SUMIDA 0.006Ω
CEP125-IR8 1%
10Ω
2
3
15
CMDSH-3
9
+
Si7440DP
B340A
11
680µF
4V
POSCAP
+
VOUT2
1.8V/10A
680µF
4V
POSCAP
12
CL–
PGND
VAOUT
VFB
10
8
0.033µF
0.01µF
3.3k
330pF
4700pF
3.01k
1%
220Ω
2.32k
1%
3710 F03b
Figure 3b. 36V to 72V DC to 3.3V/10A and 1.8V/10A Dual Output Isolated Power Supply (Part 2 of 2, See Previous Page)
3710f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT3710
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 ±0.10
9
2.74
(.108)
4.50 ±0.10
SEE NOTE 4
2.74 6.40
(.108) BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.09 – 0.20
(.0036 – .0079)
0.65
(.0256)
BSC
0.45 – 0.75
(.018 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.195 – 0.30
(.0077 – .0118)
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1339
High Power Synchronous DC/DC Controller
Operation Up to 60V Maximum
LT1425
Isolated Flyback Switching Regulator
General Purpose with External Application Resistor
LT1431
Programmable Reference
0.4% Initial Voltage Tolerance
LT1680
High Power DC/DC Step-Up Controller
Operation Up to 60V Maximum
LT3781
Dual Transistor Synchronous Forward Controller
Operation Up to 72V Maximum
LT1725
General Purpose Isolated Flyback Controller
Drives External Power MOSFET with External ISENSE Resistor
LT1737
High Power Isolated Flyback Controller
Sense Output Voltage Directly from Primary-Side Winding
LT1950
PWM Controller for Flyback, Forward and SEPIC
Applications
15W to 500W, Isolated and Nonisolated Power Supply 50% Smaller
Transformer, Protects MOSFET
LT3804
Secondary Side Dual Output Controller
with Optodriver
Regulates Two Outputs, Optocoupler Feedback Driver and Second Output
Synchronous Driver Controller
3710f
12
Linear Technology Corporation
LT/TP 0803 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
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