LT3763
60V High Current
Step-Down LED Driver Controller
DESCRIPTION
FEATURES
n
n
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Accurately Control Input and Output Current
3000:1 True Color PWM™ Dimming
±1.5% Voltage Regulation Accuracy
±6% Current Regulation Accuracy
6V to 60V Input Voltage Range
Wide Output Range Up to 55V
2V, VSS = VFBIN = 2V, VC = 1.2V
SENSE+ Pin Current
VSENSE+ = VSENSE– = 4V
SENSE– Pin Current
VSENSE
+=V
SENSE
– = 4V, V
CTRL1 = 1.5V
mV
–20
µA
–40
µA
Internal VCC Regulator (INTVCC Pin)
Regulation Voltage
ILOAD = 10mA
Current Limit
VINTVCC = 0V
l
4.8
5
5.2
V
60
mA
42
ns
44
ns
50
ns
NMOS FET Driver
Non-Overlap Time TG to BG
Non-Overlap Time BG to TG
Minimum On-Time BG
(Note 4)
Minimum On-Time TG
(Note 4)
55
ns
Minimum Off-Time BG
(Note 4)
140
ns
High Side Driver Switch On-Resistance
Gate Pull-Up
Gate Pull-Down
VCBOOST – VSW = 5V
2.2
1.3
Ω
Ω
Low Side Driver Switch On-Resistance
Gate Pull-Up
Gate Pull-Down
VINTVCC = 5V
2.2
1
Ω
Ω
Switching Frequency
RT = 40kΩ
RT = 221kΩ
l
930
180
1000
200
1070
220
kHz
kHz
Soft-Start
Charging Current
11
µA
750
nA
Voltage Regulation Amplifier
Input Bias Current
VFB = 1.3V
850
gm
Feedback Regulation Voltage
VSENSE+ = VSENSE– = VCTRL1 = 2V
µA/V
l
1.188
1.206
1.224
l
1.137
1.16
1.183
V
FAULT Comparator
Upper FAULT Threshold (FB Rising)
Upper FAULT Threshold Hysteresis
40
Lower FAULT Threshold (FB Falling)
l
Lower FAULT Threshold Hysteresis
FAULT Pull-Down Current
VFAULT = 2V, VFB = 0V
0.24
0.25
V
mV
0.265
V
40
mV
8
mA
Input Voltage Regulation
FBIN Pin Current
VFBIN = 1.5V
150
nA
Sense Voltage
(VSENSE+ – VSENSE–)
VFBIN = 1.22V, VSENSE– = 4V
VFBIN = 1.26V, VSENSE– = 4V
10
45
mV
mV
Rev. C
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3
LT3763
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VISMON Regulated to 1V, VSENSE– = 10V
VISMON Regulated to 200mV, VSENSE– = 10V
45
5
50
10
55
15
mV
mV
VIVINMON Regulated to 1V, VIVIN+ = 12V
VIVINMON Regulated to 200mV, VIVIN+ = 12V
46
6
50
10
54
14
mV
mV
45
50
55
mV
Output Current Monitor
Sense Voltage
(VSENSE+ – VSENSE–)
Input Current Monitor
Sense Voltage
(VIVIN+ – VIVIN–)
Input Current Limit Sense Voltage
(VIVIN+ – VIVIN–)
l
PWM Driver
PWM_OUT Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
VINTVCC = 5V
PWM to PWM_OUT Propagation Delay
Rising
Falling
VINTVCC = 5V
2.2
0.9
Ω
Ω
11
38
ns
ns
Current Control Loop gm Amp
Offset Voltage
VSENSE– = 4V, VCTRL1 = 0V
Input Common Mode Range
VCM(LOW)
VCM(HIGH)
(Note 5)
VCM(HIGH) Measured from VIN to VCM, VSENSE+ = VSENSE–
l
–3
0
3
0
1.4
Output Impedance
V
V
3.5
gm
l
Differential Gain
375
475
1.7
mV
MΩ
625
µA/V
V/mV
Overvoltage
FB Overvoltage Protection (VFB Maximum)
1.515
V
Overcurrent
Overcurrent Protection
(VSENSE+ – VSENSE– Maximum)
VSENSE– = 0V, RT = 221kΩ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3763E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3763I is guaranteed to meet performance specifications over the
–40°C to 125°C operating junction temperature range. The LT3763H is
guaranteed over the –40°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C.
85
mV
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The minimum on- and off-times are guaranteed by design and are
not tested.
Note 5: The minimum common mode voltage is guaranteed by design and
is not tested.
Rev. C
4
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LT3763
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Threshold (Falling)
EN/UVLO Current
1.52
1.46
5.5
5.0
4.5
4.0
60
42
24
6
42
60
100
10
1
0.1
VIN (V)
3763 G01
6VIN
12VIN
60VIN
VREF (V)
2.01
2.0
2.00
42
VIN (V)
1.3
1.2
1.1
TA = 150°C
TA = 25°C
TA = –50°C
1.0
1.99
–50 –25
60
0
3763 G04
25 50 75 100 125 150
TEMPERATURE (°C)
0.9
6
24
RT Current Limit
42
60
VIN (V)
3763 G05
3763 G06
INTVCC Current Limit
SS Current
16
70
6
5
64
52
4
VINTVCC (V)
SS CURRENT (µA)
14
58
12
3
2
10
46
40
–50 –25
VREF Current Limit
1.4
2.5
24
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G03
1.5
2.02
TA = 150°C
TA = 25°C
TA = –50°C
0
3763 G02
VREF Voltage
2.03
6
0.001
–50 –25
VREF CURRENT LIMIT (mA)
24
6
Quiescent Current (Non-Switching)
1.5
6VIN
12VIN
60VIN
0.01
3.0
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (nA)
EN/UVLO CURRENT (µA)
EN/UVLO THRESHOLD (V)
1.58
VIN (V)
RT CURRENT LIMIT (µA)
10000
1000
1.64
1.40
Quiescent Current (Shutdown)
6.0
1.70
1
0
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G07
8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G08
0
0
10
20
30
40
IINTVCC (mA)
50
60
3763 G09
Rev. C
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5
LT3763
TYPICAL PERFORMANCE CHARACTERISTICS
6.0
VIN UVLO
4.2
VBOOST – VSW UVLO Thresholds
4.5
4.1
4.0
4.0
3.9
0
3.0
3.7
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
INTVCC Load Regulation
Overvoltage Threshold
4.95
13
TIMEOUT (µs)
VFB (V)
1.51
1.49
10
20
30
40
IINTVCC (mA)
50
1.45
–50 –25
60
0
100
OUTPUT CURRENT (%)
80
40
20
Regulated Current vs VFB
150
75
50
25
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G16
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G15
Maximum Output Voltage
125
60
0
3763 G14
Overcurrent Threshold
0
10
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G13
100
0
–50 –25
12
11
1.47
OUTPUT CURRENT (%)
VINTVCC (V)
Overvoltage Timeout
14
1.53
5.05
0
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G12
1.55
5.00
0
3763 G11
5.10
VSENSE+ – VSENSE– (mV)
2.5
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G10
4.90
3.5
FALLING
3.8
3.0
–50 –25
6VIN
12VIN
60VIN
4.0
RISING
VINTVCC (V)
VIN (V)
VBOOST – VSW (V)
5.0
INTVCC UVLO
0
0
0.5
1.0
1.5
VIN – VOUT (V)
2.0
2.5
3763 G17
100
50
0
–50
1.16
1.17
1.18
1.19
VFB (V)
1.20
1.21
3763 G18
Rev. C
6
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LT3763
TYPICAL PERFORMANCE CHARACTERISTICS
TG Driver RDS(ON)
4
3
BG Driver RDS(ON)
3
RDS(ON) (Ω)
PULL-UP
RDS(ON) (Ω)
Nonoverlap Time
80
2
PULL-DOWN
1
0
–50 –25
0
PULL-UP
2
1
PULL-DOWN
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
NONOVERLAP TIME (ns)
4
0
BG TO TG
40
TG TO BG
20
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G19
60
0
3763 G20
3763 G21
Minimum On-Time
Minimum Off-Time
200
25 50 75 100 125 150
TEMPERATURE (°C)
Oscillator Frequency
80
1.2
120
HG
80
40
HG
60
0.9
FREQUENCY (MHz)
LG
MINIMUM ON-TIME (ns)
MINIMUM OFF-TIME (ns)
1MHz
160
LG
40
20
0.6
500kHz
0.3
200kHz
0
–50 –25
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
3763 G22
1.0
Current Regulation Accuracy
1.0
VCTRL1 = 1.5V
VIN = 12V
50
0.5
20
VCTRL1 = 0.75V
VIN = 12V
0.5
ACCURACY (%)
ACCURACY (%)
30
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G24
Current Regulation Accuracy
Regulated Sense Voltage
40
0
3763 G23
60
VSENSE+ – VSENSE– (mV)
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
–0.5
0
–0.5
10
0
0
0.5
1.0
VCTRL1 (V)
1.5
2.0
3763 G25
–1.0
0
2
4
6
VOUT (V)
8
10
3763 G26
–1.0
0
2
4
6
VOUT (V)
8
10
3763 G27
Rev. C
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7
LT3763
TYPICAL PERFORMANCE CHARACTERISTICS
PWM Driver Delay
PWM Driver RDS(ON)
4
40
FALLING
DELAY (ns)
PULL-UP
2
1
0
–50 –25
0
30
20
RISING
10
PULL-DOWN
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
VSENSE+ – VSENSE– (mV)
3
RDS(ON) (Ω)
C/10 Threshold
20
50
0
FAULT Threshold
0
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G30
FAULT Hysteresis
Output Current Sense
75
2.0
1.5
UPPER
0.8
0.4
50
VISMON (V)
HYSTERESIS (mV)
1.2
VFB (V)
FALLING
5
3763 G29
1.6
0
0.5
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
Input Current Sense
Input Current Limit
8
53
0.5
51
49
100
45
–50 –25
3763 G33
VIN = 12V
VOUT = 5V
ILIMIT = 20A
4
2
47
25
50
75
VIVINP – VIVINN (mV)
100
6
VOUT (V)
VIVINP – VIVINN (mV)
1.0
25
50
75
VSENSE+ – VSENSE– (mV)
Output Voltage Load Regulation
55
2.0
1.5
0
3763 G32
3763 G31
0
1.0
25
LOWER
0
–50 –25
VIVINMON (V)
RISING
10
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G28
0
15
0
25 50 75 100 125 150
TEMPERATURE (°C)
3763 G34
3763 G35
0
0
6
12
ILOAD (A)
18
24
3763 G36
Rev. C
8
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LT3763
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Load Regulation
Efficiency vs Load Current
VIN = 48V
VOUT = 24V
ILIMIT = 10A
EFFICIENCY (%)
VOUT (V)
24
16
8
0
Efficiency vs Load Current
100
100
95
95
EFFICIENCY (%)
32
90
85
0
3
6
ILOAD (A)
12
9
80
90
85
VIN = 12V
VOUT = 5V
0
6
12
ILOAD (A)
3763 G37
80
24
18
VIN = 48V
VOUT = 24V
0
3
3763 G38
Shutdown and Recovery
6
ILOAD (A)
9
12
3763 G39
15A Load Step
VOUT
5V/DIV
SS
2V/DIV
VOUT
20mV/DIV
AC-COUPLED
EN/UVLO
5V/DIV
IL
10A/DIV
IL
5A/DIV
1ms/DIV
3763 G40
500µs/DIV
Solar Powered SLA Battery
Charging
PWM Dimming
IL
500mA/DIV
VSW
50V/DIV
PWM
10V/DIV
10µs/DIV
3763 G41
3763 G42
FAULT
10V/DIV
VIN
500mV/DIV
AC-COUPLED
IL
2A/DIV
VOUT
50mV/DIV
AC-COUPLED
50s/DIV
3763 G43
Rev. C
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9
LT3763
PIN FUNCTIONS
BG (Pin 1): BG is the bottom FET gate drive signal that
controls the state of the external low side power FET. The
driver pull-up impedance is 2.2Ω, and pull-down impedance is 1Ω. Do not force any voltage on this pin.
INTVCC (Pin 2): The INTVCC pin provides a regulated 5V
output for charging the BOOST capacitor. INTVCC also provides the power for the digital and switching subcircuits.
Do not force any voltage on this pin. Bypass with at least
a 22µF capacitor to ground. INTVCC is current-limited to
50mA. Shutdown operation disables the output voltage
drive.
VIN (Pin 3): Input Supply Pin. Must be locally bypassed
with at least a 4.7µF low ESR capacitor to ground as close
as possible to the exposed pad of the package.
EN/UVLO (Pin 4): Enable Pin. The EN/UVLO pin acts as
an enable pin and turns on the internal current bias core
and sub-regulators at 1.705V and turns off at 1.52V. The
pin does not have any pull-up or pull-down, requiring a
voltage bias for normal operation. Full shutdown occurs
at approximately 0.5V. If unused, the Enable pin may be
tied to VIN.
VREF (Pin 5): Buffered 2V Reference Capable of 0.5mA
Drive. Bypass with at least 1µF capacitor to ground.
IVINP (Pin 7): IVINP is the noninverting input of the input
current sense amplifier. This pin connects to the input
supply VIN and the input current sense resistor.
IVINMON (Pin 8): IVINMON is the buffered output of the
input current sense amplifier. This pin enables monitoring
of the averaged supply current with an output voltage of
20 • (VIVINP – VIVINN). The capacitive loading to this pin
should be less than 1nF.
FAULT (Pin 9): Output Voltage Fault Detection Pin for
Shorted or Open LEDs. Internal comparators pull down
this pin when the FB pin voltage is lower than 0.25V or
higher than 1.16V and when the inductor current is less
than ten percent of the maximum value. This pin should
be pulled up to INTVCC with a resistance higher than 10k.
FBIN (Pin 10): The FBIN pin enables peak power tracking
for solar powered chargers and other similar applications
by controlling the output current of the system based on
the input voltage. This pin should be tied to VREF if this
feature is not used.
FB (Pin 11): The feedback pin is used for voltage regulation and overvoltage protection. The feedback voltage is
regulated to 1.206V. When the feedback voltage exceeds
1.515V, the overvoltage lockout prevents switching.
IVINN (Pin 6): IVINN is the inverting input of the input
current sense amplifier. This pin connects to the drain of
the high side N-channel power FET and the input current
sense resistor.
Rev. C
10
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LT3763
PIN FUNCTIONS
GND (Pin 12, Pin 23, Pin 28, Exposed Pad Pin 29):
Ground. The exposed pad must be soldered to the PCB.
CTRL2 (Pin 13): Thermal Control Input to Reduce the
Regulated Output Current.
CTRL1 (Pin 14): The CTRL1 pin sets the regulated output
current. The maximum control voltage is 1.5V. Above 1.5V,
there is no change in the regulated current.
SS (Pin 15): The Soft-Start Pin. Place an external capacitor
to ground to limit the regulated current during start-up
conditions. The soft-start pin has an 11µA charging current. When the voltage at this pin is lower than voltages at
CTRL1 and CTRL2, it overrides both signals and determines
the regulated current.
SENSE– (Pin 16): SENSE– is the noninverting input of the
error amplifier for the current regulation loop. The reference
current, based on CTRL1, CTRL2, SS or FBIN determines
the regulated voltage between SENSE+ and SENSE–.
SENSE+ (Pin 17): SENSE+ is the inverting input of the
error amplifier for the current regulation loop. This pin
is connected to an external current sense resistor. The
voltage drop between SENSE+ and SENSE– is measured
against the voltage drop across an internal resistor at the
input to the current regulation loop.
VC (Pin 18): A resistor and capacitor connected in series
to the VC pin provide the necessary compensation for the
stability of the average current loop. Typical values are 5k
to 60k for the resistor and 2.2nF to 10nF for the capacitor.
ISMON (Pin 19): ISMON is the buffered output of the
output current sense amplifier. This voltage output enables
monitoring the averaged output current of the LED driver
with a voltage of 20 • (VSENSE+ – VSENSE–). The capacitive
loading to this pin should be less than 1nF.
RT (Pin 20): A resistor from the RT pin to ground sets the
switching frequency between 200kHz and 1MHz. When
using the SYNC function, set the frequency to be at least
20% lower than the SYNC pulse frequency. This pin is
current-limited to 55µA. Do not leave this pin open.
SYNC (Pin 21): Frequency Synchronization Pin. This pin
allows the switching frequency to be synchronized to an
external clock. The RT resistor should be chosen to operate the internal clock at 20% slower than the SYNC pulse
frequency. This pin should be grounded when not in use.
PWM (Pin 22): The input pin for PWM dimming of LEDs.
When low, all switching is terminated and the PWM_OUT
pin is low. This pin should be connected to INTVCC when
not in use.
PWM_OUT (Pin 24): This pin can drive an external FET
for PWM dimming of LEDs. The pull-up and pull-down
impedances of the driver are 2.2Ω and 0.9Ω, respectively.
Do not force any voltage on this pin.
TG (Pin 25): TG is the top FET gate drive pin that controls
the state of the external high side power FET. The driver
pull-up impedance is 2.2Ω, and pull-down impedance is
1.3Ω. Do not force any voltage on this pin.
SW (Pin 26): The SW pin is used internally as the lower
rail for the floating top FET gate driver. Externally, this node
connects the two power FETs and the inductor.
BOOST (Pin 27): The BOOST pin provides a floating 5V
regulated supply for the top FET gate driver. An external
schottky diode is required from the INTVCC pin to the
BOOST pin to charge the BOOST capacitor when the SW
pin is near ground.
Rev. C
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11
LT3763
BLOCK DIAGRAM
RSENSE_IN
2.5mΩ
VIN
RFILTA
1k
CFILT
1µF
7
CIN2
47µF
RFILTB
1k
CIN1
4.7µF
CVCC
22µF
6
IVINP
3
IVINN
2
VIN
R
INPUT
CURRENT
MONITORING
gm = 400µA/V
LOW SIDE
DRIVER
OSCILLATOR
14
IVINMON
CTRL1
1.5V
BG
SYNC
–
8
TG
SW
+
–
2V REFERENCE
SYNCHRONOUS
CONTROLLER
Q
CBOOST
200nF
BOOST
+
VREF
INTERNAL
REGULATOR
AND UVLO
S
HIGH SIDE
DRIVER
CURRENT
MIRROR
VC
PWM_OUT
PWM
+
C/10
COMPARATOR
ISMON
+
–
–
VOLTAGE
REGULATOR AMP
gm = 850µA/V
0.25V
CTRL2
24
RC
47.5k
CC
4.7nF
L1
1µH
19
17
16
RFB1
47.5k
RS
2.5mΩ
VOUT
COUT
200µF
×2
11
RFB2
12.1k
1.16V
–
INTVCC
FAULT
DETECTION
COMPARATORS
–
RT
82.5k
22
1.206V
+
1.206V
FB
–
+
+
10
18
50k
11µA
SS
FBIN
20
OUTPUT
MONITORING
SENSE–
13
21
0.1V
SENSE+
3k
CSS
10nF
1
+
gm = 475µA/V
RO = 3.5M
VCM(HIGH) = VIN – 1.4V
–
–
+
1.5V
–
–
gm AMP
+
90k
15
26
1.5V
RT
+
+CONTROL
BUFFER
–
25
–
CREF
2.2µF
5
EN/UVLO
+
4
27
INTVCC
FAULT
RFAULT
47.5k
9
GND (12, 23, 28, 29)
3763 BD
Figure 1. Block Diagram
Rev. C
12
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LT3763
OPERATION
The LT3763 utilizes fixed frequency, average current mode
control to accurately regulate the inductor current independently from the output voltage. This is an ideal solution
for applications requiring a regulated current source. The
control loop will regulate the current in the inductor at
an accuracy of ±6%. If the output reaches the regulation
voltage determined by the resistor divider from the output
to the FB pin, the inductor current will be reduced by the
voltage regulation loop. In voltage regulation, the output
voltage has an accuracy of ±1.5%. For additional operation information, refer to the Block Diagram in Figure 1.
The current control loop has two main inputs, determined
by the voltages at the analog control pins, CTRL1 and
CTRL2. The lower voltage between CTRL1 and CTRL2
determines the regulated output current. The voltages at
CTRL1 and CTRL2 are buffered to produce a reference
current set by the voltage across an internal 90k resistor.
This reference current produces a reference voltage that
the average current mode control loop uses to regulate
the inductor current as a voltage drop across the external
sense resistor, RS. The outputs of the internal buffers are
clamped at 1.5V, limiting the control range of the CTRL1
and CTRL2 pins from 0V to 1.5V—corresponding to a
0mV to 51mV range on RS.
The FBIN pin provides a third input to the current control
loop. This input is dedicated to regulating the input voltage by controlling the inductor current. Inductor current
regulation commences when the voltage at the FBIN pin
rises higher than 1.206V. Above 1.206V, the inductor current
is linearly increased, providing the maximum current, as
determined by the voltages at the CTRL pins, when FBIN
is at and above 1.26V. When input voltage regulation is
not needed, FBIN should be tied to VREF to allow the CTRL
pins to control the inductor current.
The 2V reference provided on the VREF pin allows the
use of a resistor voltage divider to the CTRL1 and CTRL2
pins. The current supplied by the VREF pin should be less
than 0.5mA.
The error amplifier for the average current mode control
loop has a common mode lockout that regulates the inductor current so that the error amplifier is never operated out
of the common mode range. The common mode range is
from ground to 1.4V below the VIN supply rail.
The LT3763 prevents excessive inductor current by triggering overcurrent limit when the inductor current produces
a voltage greater than 85mV across the SENSE+ and
SENSE– pins. The current is limited on a cycle-by-cycle
basis; switching shuts down as soon as the overcurrent
level is reached. Overcurrent is not soft-started.
The regulated output voltage is set with a resistor divider
from the output to the FB pin. The reference for the FB
pin is 1.206V. If the output voltage level is high enough to
engage the voltage loop, the regulated inductor current will
be reduced. If the voltage at the FB pin reaches 1.515V, an
internal overvoltage flag is set, shutting down switching
for a brief period.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.52V, the internal reset flag is asserted and switching is
terminated. Full shutdown is guaranteed below 0.5V with
a quiescent current of less than 2µA. The EN/UVLO pin has
185mV of hysteresis built in, and a 5µA current source is
connected to this pin that allows any amount of hysteresis
to be added with a series resistor or resistor divider from
VIN. Alternatively, this pin can be tied directly to VIN to
reduce the number of off-chip components.
During start-up, the SS pin is held low until the internal
reset goes low and PWM goes high the first time after
a reset event. Once the reset is cleared, the capacitor
connected to the soft-start pin is charged with an 11μA
current source. Initially, the internal buffers for the CTRL1,
CTRL2, and FBIN voltages are limited by the voltage at the
soft-start pin, and the inductor current reference slowly
increases to the level determined by the lowest voltage
of those three pins.
The rising threshold for thermal shutdown is set at 165°C
with –5°C hysteresis. During thermal shutdown, all switching is terminated, and the part is in reset mode (forcing
the SS pin low).
The switching frequency is determined by a resistor at
the RT pin. This pin is limited to 55µA, which limits the
switching frequency to approximately 2MHz when the
RT pin is shorted to ground. The LT3763 may also be
synchronized to an external clock through the use of the
For more information www.analog.com
Rev. C
13
LT3763
OPERATION
SYNC pin which has precise thresholds at 2.175V and
1.5V for rising and falling edges, respectively.
LT3763 also features a PWM driver for LED dimming.
PWM_OUT is high when the PWM pin voltage is higher than
2.175V, and low when PWM is lower than 1.5V. Switching
is terminated when PWM is lower than 1.5V. PWM should
be tied to INTVCC when the PWM function is not needed.
The FAULT pin is pulled down to ground when the voltage
at FB becomes less than 0.25V which indicates a shortcircuit condition. It is also pulled down to indicate an
open-circuit condition when the voltage becomes greater
than 1.16V and the inductor current is less than ten percent
of the maximum (C/10), or equivalently, when the voltage between SENSE+ and SENSE– is less than 5mV. To
avoid jitter when recovering from a fault condition, 50mV
hysteresis is employed in the comparators. Additionally,
when the inductor current is lower than C/10, the C/10
comparator disables the low side MOSFET regardless of
the voltage at FB.
The integrated input current and output current monitoring functions of the LT3763 allow users to acquire system
information such as the input power and output power. The
outputs of the current monitors, IVINMON and ISMON,
range from 0V to 1V when the inputs vary from 0V to
50mV. When using 2.5mΩ sense resistors, for example,
these current monitoring amplifiers sense from 0A to
20A. To filter out the switching portion of the currents
and measure the average current information, the input
pins of the input current monitor, IVINP and IVINN, should
connect to the sense resistor through two 1k resistors
and a capacitor directly between the IVINP and IVINN
pins. The capacitance value can be adjusted according to
the switching frequency and the ripple magnitude. The
output current monitor employs an internal filter to reduce
ripple, and it does not require an external filter, but if one
is added, the corner frequency should be higher than the
switching frequency.
The LT3763 also includes an input current limiting function to regulate the input current to a value determined by
the RSENSE_IN resistor. When the voltage drop across the
RSENSE_IN resistor approaches 50mV, the inductor current
is reduced and regulated so that 50mV is maintained across
the IVINP and IVINN pins.
APPLICATIONS INFORMATION
Programming Inductor Current
The analog voltage at the CTRL1 pin is buffered and produces a reference voltage, VCTRL, across an internal resistor.
The regulated average inductor current is determined by:
VCTRL
30 •RS
IO =
where RS is the external sense resistor and IO is the average inductor current, which is equal to the output current.
Figure 2 shows the maximum output current versus RS.
The maximum power dissipation in the resistor will be:
PRS
MAXIMUM OUTPUT CURRENT (A)
30
25
20
15
10
5
0
0
2
4
6
8 10 12 14 16 18 20
RS (mΩ)
3763 F02
Figure 2. RS Value Selection for Regulated Output Current
2
0.05V )
(
=
RS
Figure 3 plots the power dissipation in RS, and Table 1
lists several resistance values and the corresponding
maximum inductor current and sense-resistor power dissipation. Susumu, Panasonic and Vishay offer accurate
sense resistors.
Rev. C
14
For more information www.analog.com
LT3763
POWER DISSIPATION (W)
APPLICATIONS INFORMATION
1.4
Table 2. Recommended Inductor Manufacturers
1.2
VENDOR
WEBSITE
1.0
Coilcraft
www.coilcraft.com
Sumida
www.sumida.com
Vishay
www.vishay.com
0.8
0.6
Würth Electronics
www.we-online.com
0.4
NEC-Tokin
www.nec-tokin.com
0.2
0
Switching MOSFET Selection
0
2
4
6
8 10 12
RS (mΩ)
14 16 18 20
3763 F03
Figure 3. Power Dissipation in RS
Table 1. Sense Resistor Values
MAXIMUM OUTPUT
CURRENT (A)
RESISTOR, RS (mΩ) POWER DISSIPATION (W)
1
50
0.05
5
10
0.25
10
5
0.50
25
2
1.25
Inductor Selection
Size the inductor so that the peak-to-peak ripple current
is approximately 30% of the output current.
The following equation sizes the inductor for best performance:
⎛ VIN • VO – VO 2 ⎞
L=⎜
0.3 • fSW •IO • VIN ⎟⎠
⎝
where VO is the output voltage, VIN is the input voltage,
IO is the maximum regulated current in the inductor and
fSW is the switching frequency.
The overcurrent comparator terminates switching when
the voltage between the SENSE+ and SENSE– pins exceeds
85mV. The saturation current for the inductor should be
at least 20% higher than the maximum regulated current.
Recommended inductor manufacturers are listed in Table 2.
The following parameters are critical in determining the
best switching MOSFETs for a given application: total gate
charge (QG), on-resistance (RDS(ON)), gate to drain charge
(QGD), gate-to-source charge (QGS), gate resistance (RG),
breakdown voltages (maximum VGS and VDS) and drain
current (maximum ID). The following guidelines provide
information to make the selection process easier, and
Table 3 lists some recommended parts and manufacturers.
For both switching MOSFETs the rated drain current should
be greater than the maximum inductor current. Use the
following equation to calculate the peak inductor current:
⎛ V • V – V 2⎞
IMAX =IO + ⎜ IN O O ⎟
⎝ 2 • fSW •L • VIN ⎠
The rated drain current is temperature dependent, and
most data sheets include a table or graph of the rated
drain current versus temperature.
The rated VDS should be higher than the maximum input
voltage (including transients) for both MOSFETs. As for the
rated VGS, the signals driving the gates of the switching
MOSFETs have a maximum voltage of 5V with respect to the
source. However, during start-up and recovery conditions,
the gate-drive signals may be as low as 3V. Therefore, to
ensure that the LT3763 recovers properly, the maximum
threshold voltage should be less than 2V, and for a robust
design, ensure that the rated VGS is greater than 7V.
Power losses in the switching MOSFETs are related to the
on-resistance, RDS(ON); gate resistance, RG; gate-to-drain
charge, QGD and gate-to-source charge, QGS. Power lost to
the on-resistance is an Ohmic loss, I2RDS(ON), and usually
dominates for input voltages less than 15V. Power lost
while charging the gate capacitance dominates for voltages
Rev. C
For more information www.analog.com
15
LT3763
APPLICATIONS INFORMATION
PLOSS = ohmic loss + transition loss
⎛V
⎞
PLOSS ≈ ⎜ O •IO 2 RDS(ON) • ρT⎟ +
⎝ VIN
⎠
7
6
MOSFET POWER LOSS (W)
greater than 15V. When operating at higher input voltages,
efficiency can be optimized by selecting a high side MOSFET
with higher RDS(ON) and lower QG. The total power loss in
the high side MOSFET can be approximated by:
5
TRANSITIONAL
3
2
1
⎛ V •I
⎞
⎞
⎛
⎞ ⎛ (QGD +QGS ) •
⎜ ⎜ IN OUT ⎟ • ⎜
⎟ • fSW ⎟
⎜ ⎝ 5V ⎠ ⎝ ( 2 •RG +RPU +RPD )⎠
⎟⎠
⎝
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The trade-off
between RDS(ON), QG, and QGS for the high side MOSFET
is evident in the following example. VO is equal to 4V.
These two N-channel MOSFETs are rated for a VDS of 40V
and mounted in the same package, but with 8× different
RDS(ON) and 4.5× different QG and QGD:
0
OHMIC
0
10
20
40
30
INPUT VOLTAGE (V)
3763 F04a
Figure 4a. Power Loss Example for M1
2.5
MOSFET POWER LOSS (W)
where rT is a dimensionless temperature dependent
factor in the MOSFET’s on-resistance. Using 70°C as the
maximum ambient operating temperature, rT is roughly
equal to 1.3. RPD and RPU are the LT3763 high side gate
driver output impedances: 1.3Ω and 2.2Ω, respectively.
TOTAL
4
2.0
1.5
TOTAL
1.0
TRANSITIONAL
0.5
0
M1: RDS(ON) = 2.3mΩ, QG = 45.5nC,
OHMIC
0
10
20
30
40
INPUT VOLTAGE (V)
3763 F04b
QGS = 13.8nC, QGD = 14.4nC, RG = 1Ω
Figure 4b. Power Loss Example for M2
M2: RDS(ON) = 18mΩ, QG = 10nC,
QG, must be charged and discharged each switching cycle,
so the power lost to the charging of the gates is:
QGS = 4.5nC, QGD = 3.1nC, RG = 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Observe
that whereas the RDS(ON) of M1 is eight times lower, the
power loss at low input voltages is about equal to that of
M2, and at high voltages, it is four times higher.
Power loss within the low side MOSFET is almost entirely
from the RDS(ON) of the FET. Select the low side FET with
the lowest RDS(ON) while keeping the total gate charge QG
to 30nC or less.
Another power loss related to switching MOSFET selection
is the power lost driving the gates. The total gate charge,
PGATE = VIN • (QGLG + QGHG) • fSW
where QGLG is the low side gate charge and QGHG is the
high side gate charge.
The majority of this loss occurs in the internal LDO within
the LT3763:
PLOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fSW
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3763. Some recommended MOSFETs
are listed in Table 3.
Rev. C
16
For more information www.analog.com
LT3763
APPLICATIONS INFORMATION
TOP FET
BOTTOM FET MANUFACTURER
end of every pulse as the decreasing inductor current flows
into the output capacitor. Use of a small output capacitor
may trigger overvoltage protection through the FB pin.
60
4
20
RJK0853DPB
24
4
5
RJK0368DPA
RJK0853DPB Renesas
RJK0332DPB www.renesas.com
CBOOST Capacitor Selection
48 10 to 35 10
RJK0851DPB
VIN VOUT IOUT
(V) (V)
(A)
RJK0851DPB
12 2 to 4
10
FDMS8680
FDMS8672AS Fairchild
www.fairchildsemi.com
26
4
20
Si7884BDP
24
4
40 PSMN4R0-30YL RJK0346DPA NXP/Philips
www.nxp.com
36
12
10 BSC100N06LS3 BSC100N06LS3 www.infineon.com
SiR470DP
Vishay
www.vishay.com
Input Capacitor Selection
The input capacitor should be sized at least 2µF for every
1A of output current and placed very close to the high side
MOSFET. The loop created by the input capacitor, high side
MOSFET, low side MOSFET should be minimized. It should
have a ripple current rating equal to half of the maximum
output current. Additionally, a small 4.7µF ceramic capacitor should be placed between VIN and ground as close as
possible to the VIN pin and the exposed pad of the package
for optimal noise immunity.
It is recommended that several low ESR (equivalent series resistance) ceramic capacitors be used as the input
capacitance, although other capacitors with higher density
may be required to reduce board area. Only X5R or X7R
capacitors maintain their capacitance over a wide range
of operating voltages and temperatures.
Output Capacitor Selection
The output capacitors need to have very low ESR to reduce
output ripple. A minimum of 20µF/A of load current should
be used in most designs. The capacitors also need to be
surge rated to the maximum output current. To achieve
the lowest possible ESR, several low ESR ceramic capacitors should be used in parallel. Many lower output voltage
applications benefit from the use of high density POSCAP
capacitors, which are easily destroyed when exposed to
overvoltage conditions. To prevent this, select POSCAP
capacitors that have a voltage rating that is at least 50%
higher than the regulated voltage.
Note that when dimming, the output voltage increases at the
The CBOOST capacitor must be sized no bigger than 220nF
and more than 50nF to ensure proper operation of the
LT3763. Use 220nF for high current switching MOSFETs
with high gate charge.
INTVCC Capacitor Selection
The bypass capacitor for the INTVCC pin should be larger
than 22µF to ensure stability, and it should be connected
as close as possible to the exposed pad underneath
the package. It is recommended that the ESR be lower
than 50mΩ to reduce noise within the LT3763. For driving MOSFETs with gate charges larger than 44nC, use
0.5µF/nC of total gate charge.
Soft-Start
Unlike conventional voltage regulators, the LT3763 utilizes
the soft-start function to control the regulated inductor
current instead of the output voltage. The charging current
is 11µA and reduces the set current as long as the SS pin
voltage is lower than CTRL1 and CTRL2.
Output Current Regulation
To adjust the regulated load current, an analog voltage is
applied to the CTRL1 pin. Figure 5 shows the regulated
voltage across the sense resistor for control voltages up to
60
50
VSENSE+ – VSENSE– (mV)
Table 3. Recommended Switching FETs
40
30
20
10
0
0
0.5
1.0
VCTRL1 (V)
1.5
2.0
3763 F05
Figure 5. Sense Voltage vs CTRL Voltage
Rev. C
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17
LT3763
APPLICATIONS INFORMATION
2V. Figure 6 shows the CTRL1 voltage created by a voltage
divider from VREF to ground. When sizing the resistor divider,
please be aware that the VREF pin should have a total load
current less than 0.5mA, and that above 1.5V, the control
voltage has no effect on the regulated inductor current.
Setting CTRL1 to 0V does not automatically stop switching. To disable switching, set PWM pin voltage below 1.5V.
Input Current Monitoring
Users can monitor the input current at the IVINMON pin,
which produces 0V to 1V as the voltage between IVINP and
IVINN varies from 0mV to 50mV, as shown in Figure 7. Due
to the switching of the high side FET, the input current is
noisy and monitoring the average input current requires an
external filter with 1k resistors connecting IVINP and IVINN
to the input current sense resistor RSENSE_IN. Choose the
capacitor for this filter according to the switching frequency
so that the noise is reduced by at least a factor of 100. If
the frequency is 500kHz, for example, 1µF is sufficient,
and higher switching frequencies will require a smaller
capacitor. A resistor and capacitor may be connected to
IVINMON to further filter the noise. With both input and
output current monitoring, the LT3763 enables users to
calculate the overall efficiency of the circuit including the
losses in the external components.
Output Current Monitoring
The LT3763 provides users the capability to monitor the
output current as a voltage provided at the ISMON pin.
The voltage will linearly increase from 0V to 1V as the
voltage between SENSE+ and SENSE– increases from 0mV
to 50mV as shown in Figure 8. If, for example, a 2.5mΩ
resistor is chosen for RS, then a 1V output at ISMON will
indicate a 20A output current. A resistor and capacitor
may be connected to ISMON to filter noise.
Voltage Regulation and Overvoltage Protection
The LT3763 uses the FB pin to regulate the output voltage and to provide an overvoltage lockout to avoid high
voltage conditions. The regulated output voltage is programmed using a resistor divider from the output to the
FB pin (Figure 9). When the output voltage approaches
2.0
VREF
LT3763
1.5
VISMON (V)
R2
CTRL1
R1
3763 F06
1.0
0.5
Figure 6. Analog Control of Inductor Current
0
2.0
VIVINMON (V)
1.5
0
25
50
75
VSENSE+ – VSENSE– (mV)
100
3763 F08
Figure 8. Output Current Monitoring Voltage vs Output
Current Sense Voltage
1.0
VOUT
0.5
LT3763
R2
FB
0
0
25
50
75
VIVINP – VIVINN (mV)
R1
100
3763 F09
3763 F07
Figure 7. Input Current Monitoring Voltage
vs Input Current Sense Voltage
18
Figure 9. Output Voltage Regulation and
Overvoltage Protection Feedback Connections
For more information www.analog.com
Rev. C
LT3763
APPLICATIONS INFORMATION
the programmed level (1.206V at the FB pin), the voltage
error amplifier overrides CTRL1 to set the inductor current and regulate VOUT. When the output voltage exceeds
125% of the regulated voltage level (1.515V at the FB pin),
the internal overvoltage flag is set, terminating switching.
The regulated output voltage must be greater than 1.5V
and is set by the equation:
⎛ R2 ⎞
VOUT = 1.206V ⎜ 1+ ⎟
⎝ R1⎠
Programming Switching Frequency
The LT3763 has an operational switching frequency range
between 200kHz and 1MHz. This frequency is programmed
with an external resistor from the RT pin to ground. Do not
leave this pin open under any condition. The RT pin is also
current-limited to 55µA. See Table 4 and Figure 10 for resistor values and the corresponding switching frequencies.
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz)
RT (kΩ)
1.00
40.2
0.75
53.6
0.50
82.5
0.30
143
0.20
221
Fault Detection
Low Current Detection
When the inductor current decreases to ten percent of the
maximum current, the C/10 comparator will also disable
the low side gate driver, so the converter will become
non-synchronous and automatically transition into discontinuous conduction mode when the inductor current
is low enough relative to the ripple.
The low current condition is an essential part of battery
charging applications. The LT3763 works well in this application delivering a constant current to the battery as it
charges and then automatically reducing the current to a
trickle charge as the battery voltage approaches its fully
charged value. In this application, the signal at FAULT
triggered by the low current detection comparator serves
as an indicator that the trickle charge phase of charging
the battery has begun.
Switching Frequency Synchronization
The nominal switching frequency of the LT3763 is determined by the resistor from the RT pin to ground and may
be set from 200kHz to 1MHz. The internal oscillator may
also be synchronized to an external clock through the SYNC
pin. The external clock applied to the SYNC pin must have
a logic low below 1.5V and a logic high above 2.175V. The
input frequency must be 20% higher than the frequency
that would otherwise be determined by the resistor at the
RT pin. Input signals outside of these specified parameters
will cause erratic switching behavior and subharmonic
oscillations. Synchronization is tested at 500kHz with
a 221k RT resistor. Operation under other conditions is
guaranteed by design. When synchronizing to an external
1.2
1.0
FREQUENCY (MHz)
The LT3763 detects that the load has had an open-circuit
or short-circuit event indicated by pulling the FAULT pin to
ground. These conditions are detected by comparing the
voltage at the FB pin to two internal reference voltages.
A short-circuit is defined as VFB lower than 0.25V. In an
open-circuit condition, the regulated inductor current will
charge the output capacitor, the voltage at FB will begin
to increase, and the voltage error amplifier will begin to
reduce the inductor current. The open-circuit condition will
be indicated at FAULT when FB is higher than 1.16V and
the inductor current is less than ten percent (C/10) of the
maximum value set by the sense resistor RS. The output
voltage will be regulated as determined by the resistor
divider to the FB pin.
0.8
0.6
0.4
0.2
0.0
0
50
100
150
RT (kΩ)
200
250
3763 F10
Figure 10. Frequency vs RT Resistance
Rev. C
For more information www.analog.com
19
LT3763
APPLICATIONS INFORMATION
clock, please be aware that there will be a fixed delay from
the input clock edge to the edge of the signal at the SW pin.
The SYNC pin must be grounded if the synchronization to
an external clock is not required. When SYNC is grounded,
the switching frequency is determined by the resistor RT.
PWM Driver
The LT3763 includes a PWM driver for users who want to
control the dimming of LEDs connected to the output. The
driver will pull up the gate of an external N-channel MOSFET
connected to the PWM_OUT pin when the voltage at the
PWM pin rises above 2.175V and pull down the gate when
the voltage falls below 1.5V. When VPWM is lower than 1.5V,
switching is terminated and VC is disconnected from the
current regulation amplifier. When VPWM is above 2.175V,
the inductor current is regulated to the current programmed
by the voltage at the CTRL1, CTRL2, or FBIN pins.
The pull-up driver impedance is 2.2Ω, and the pull-down
driver impedance is 0.9Ω. The PWM dimming pulse-width
should be longer than two switching cycles.
VOUT
LOAD
PWM
+
1.5V
–
PWM_OUT
3763 F11
Figure 11. PWM Driver Operation
PWM Operation
When the voltage at PWM is low, all switching of the high
and low side MOSFETS is terminated, and the inductor
current will decrease to zero. After PWM increases above
the logic threshold, the inductor current ramps up to the
regulated value. The ramp time, tD, can be estimated using
the following equation:
tD =
L •IO
VIN – VO
which assumes that the output capacitor does not discharge
significantly in the time that PWM is low.
20
When the PWM functionality is not desired, the PWM pin
should be tied to INTVCC so as not to disable switching.
PWM MOSFET Selection
The rated VDS for the PWM MOSFET need only be higher
than the maximum output voltage. Although this permits a
MOSFET choice with a smaller QG specification than that of
the switching MOSFETs, it will have little effect on efficiency,
because the PWM switching frequency will be much lower
than that of the switching MOSFETs. Power lost charging the
gate of the PWM MOSFET will naturally be much lower than
the power lost charging the switching MOSFETs. RDS(ON)
conduction losses in the PWM MOSFET will also be much
smaller if the duty cycle of the PWM signal is very low.
Like the drivers for the switching MOSFETs, the PWM
driver draws power from the INTVCC pin, and the choice
of MOSFET should follow the same recommendations for
threshold voltage (less than 2V) and rated VGS (at least 7V).
Thermal Shutdown
The internal thermal shutdown within the LT3763 engages
at 165°C and terminates switching and discharges the
soft-start capacitor. When the part has cooled to 160°C,
the internal reset is cleared and the soft-start capacitor is
allowed to charge.
Shutdown and UVLO
The LT3763 has an internal UVLO that terminates switching, resets all synchronous logic, and discharges the softstart capacitor for input voltages below 4V. The LT3763
also has a precision shutdown at 1.52V on the EN/UVLO
pin. Partial shutdown occurs at 1.52V and full shutdown
is guaranteed below 0.5V with less than 2µA IQ in the full
shutdown state. Below 1.52V, an internal current source
provides 5µA of pull-down current to allow for programmable UVLO hysteresis. The following equations determine
the voltage-divider resistors for programming the UVLO
voltage and hysteresis as configured in Figure 12.
VHYST VUVLO
–
5µA 51µA
⎛ 1.52V •R2 ⎞
R1= ⎜
⎟
VUVLO – 1.52V ⎠
⎝
R2 =
For more information www.analog.com
Rev. C
LT3763
APPLICATIONS INFORMATION
VIN
Average Current Mode Control Compensation
VIN
LT3763
The use of average current mode control allows for precise
regulation of the inductor current and load current. Figure
14 shows the average current mode control loop used in
the LT3763, where the regulation current is programmed
by a current source and a 3k resistor.
R2
EN/UVLO
R1
3763 F12
Figure 12. UVLO Configuration
Load Current Derating Using the CTRL2 Pin
The LT3763 is designed specifically for driving high power
loads. In high current applications, derating the maximum current based on operating temperature prevents
damage to the load. In addition, many applications have
thermal limitations that will require the regulated current
to be reduced based on load temperature and/or board
temperature. To achieve this, the LT3763 uses the CTRL2
pin to reduce the effective regulated current in the load,
which is otherwise programmed by the analog voltage at
the CTRL1 pin. The load/board temperature derating is
programmed using a resistor divider with a temperature
dependant resistance (Figure 13). When the load/board
temperature rises, the CTRL2 voltage will decrease. When
the CTRL2 voltage is lower than voltage at the CTRL1 pin,
the regulated current is reduced.
RV
RV
VREF
R2
LT3763
RNTC
RNTC
RX
RNTC
RNTC
RX
CTRL2
R1
(OPTION A TO D)
3763 F13
A
B
C
D
Figure 13. Load Current Derating vs Temperature
Using NTC Resistor
To design the compensation network, the maximum compensation resistor needs to be calculated. In current mode
controllers, the ratio of the sensed inductor current ramp
MODULATOR
VCTRL • 11µA/V
3k
L
RS
+
LOAD
gm
ERROR AMP
RC
–
3763 F14
CC
Figure 14. LT3763 Average Current Mode Control Scheme
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off time.
Since the closed loop gain at the switching frequency
produces the error signal slope, the output impedance of
the error amplifier will be the compensation resistor, RC.
Use the following equation as a good starting point for
compensation component sizing:
RC =
1kΩ •1V •L
2nF
, CC =
•T
VO •RS • TSW
µs SW
Rev. C
For more information www.analog.com
21
LT3763
APPLICATIONS INFORMATION
where TSW is the switching period, L is the inductance
value, VO is the output voltage and RS is the sense resistor.
For most applications, a 4.7nF compensation capacitor
is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 5 for recommended compensation values.
capacitors and switching MOSFETS should be minimized.
Placing the sense resistor as close as possible to the SENSE+
and SENSE– pins also helps avoid noise issues. Due to sense
resistor ESL (equivalent series inductance), 10Ω resistors
in series with the SENSE+ and SENSE– pins with a 33nF capacitor placed between the SENSE pins are recommended.
Utilizing a good ground plane underneath the switching
components will minimize interplane noise coupling. To
dissipate the heat from the switching components, use a
large area for the switching node while keeping in mind
that this negatively affects the radiated noise.
Board Layout Considerations
Average current mode control is relatively immune to the
switching noise associated with other types of control
schemes. Nevertheless, the high di/dt loop formed by input
Table 5. Recommended Compensation Component Values (VCTRL2 = 2V)
VIN (V)
VO (V)
VCTRL1 (V)
IL (A)
fSW (kHz)
L (µH)
RS (mΩ)
RC (kΩ)
CC (nF)
12
4
12
4
0.75
5
500
2.2
5
54.9
4.7
1.50
10
500
2.2
5
54.9
4.7
12
60
5
1.50
20
250
2.2
2.5
44.2
8.2
30
0.15
1
500
10
5
15.4
4.7
60
30
1.20
8
500
10
5
15.4
4.7
Rev. C
22
For more information www.analog.com
LT3763
TYPICAL APPLICATIONS
20A, Pulse Width Modulated, Single LED Driver
RSENSE_IN
2.5mΩ
VIN
10V TO 30V
REN1
84.5k
RFILTA
1k
REN2
15.4k
CFILT
1µF
IVINP
RFILTB
1k
IVINN
VIN
TG
EN/UVLO
CREF
2.2µF
RHOT
45.3k
LT3763
RNTC
470k
M1
CBOOST
220nF
VREF
CTRL2
50k
CIN2
100µF
CIN1
4.7µF
BOOST
L1
1.5µH
SW
VOUT
6V, 20A MAXIMUM
COUT
220µF
×2
INTVCC
RFAULT
47.5kΩ
BG
CTRL1
RS
2.5mΩ
D1
CVCC
22µF
M2
RSA
10Ω
RSB
10Ω
GND
50Ω
1nF
50Ω
1nF
FBIN
SENSE+
IVINMON
PWMOUT
ISMON
M3
FAULT
PWM
SYNC
RT
RT
82.5k
CS
33nF
SENSE–
FB
SS
CSS
10nF
VC
RC
59k
CC
4.7nF
L1: COILCRAFT XAL1010-152
M1: RENESAS RJK0365
M2: RENESAS RJK0453
M3: IR IRFH6200
RS: VISHAY WSL25122L500FEA
RFB1
47.5k
RFB2
12.1k
3763 TA02
PWM Dimming
PWM
10V/DIV
VSW
50V/DIV
IL
5A/DIV
5µs/DIV
3763 TA02b
Rev. C
For more information www.analog.com
23
LT3763
TYPICAL APPLICATIONS
1A, Five LED Driver
RSENSE_IN
50mΩ
VIN
32V TO 60V
RFILTA
1k
CFILT
1µF
IVINP
ENABLE
CREF
2.2µF
RFILTB
1k
IVINN
VIN
EN/UVLO
RHOT
45.3k
TG
VREF
LT3763
CTRL2
FBIN
SENSE–
IVINMON
SYNC
RT
RFAULT
47.5kΩ
CVCC
22µF
M2
RSA
10Ω
CSS
10nF
RC
59k
CC
4.7nF
RSB
10Ω
D2
D3
D4
CS
33nF
D5
RFB1
287k
FB
VC
COUT
10µF
×2
D1
FAULT
SS
VOUT
30V, 1A MAXIMUM
RS
50mΩ
PWMOUT
ISMON
PWM
RT
82.5k
L1
100µH
GND
SENSE+
INTVCC
M1
SW
BG
CTRL1
CBOOST
50nF
BOOST
INTVCC
RNTC
470k
50k
CIN2
4.7µF
CIN1
1µF
L1: COILCRAFT MSS1278-104
M1, M2: RENESAS RJK1054
RS: VISHAY WSL2512R0500FEA
RFB2
12.1k
3763 TA03
Rev. C
24
For more information www.analog.com
LT3763
TYPICAL APPLICATIONS
3.3A, Six-Cell (36V) SLA Battery Charger
RSENSE_IN
15mΩ
VIN
48V
RFILTA
1k
CFILT
1µF
IVINP
ENABLE
CREF
2.2µF
RFILTB
1k
IVINN
CIN1
1µF
VIN
EN/UVLO
TG
VREF
LT3763
CBOOST
220nF
BOOST
CVCC
22µF
M2
GND
PWMOUT
ISMON
PWM
FB
SS
VC
CSS
10nF
RSA
10Ω
RSB
10Ω
12V
+
RFB1
402k
FAULT
SYNC
RT
COUT
10µF
+
CS
33nF
SENSE–
IVINMON
VOUT
45V, 3.3A MAXIMUM
12V
SENSE+
FBIN
RS
15mΩ
12V
RFAULT
47.5kΩ
BG
RT
82.5k
L1
12µH
+
INTVCC
INTVCC
M1
SW
CTRL2
CTRL1
CIN2
47µF
RC
8.06k
CC
4.7nF
L1: WÜRTH 744771112
M1, M2: INFINEON BSC100N06LS3
M3: VISHAY VN2222LL
RS: VISHAY WSL2512R0150
RFB2
12.1k
RFB3
178k
M3
3763 TA04
36V SLA Battery Charging
FAULT
10V/DIV
IL
2A/DIV
VOUT
50mV/DIV
AC-COUPLED
50s/DIV
3763 TA04b
Rev. C
For more information www.analog.com
25
LT3763
TYPICAL APPLICATIONS
20A, Synchronized, 5V Regulator
RSENSE_IN
2.5mΩ
VIN
7V TO 30V
REN1
44.2k
CFILT
1µF
RFILTA
1k
REN2
15.4k
IVINP
RFILTB
1k
IVINN
VIN
EN/UVLO
CREF
2.2µF
RHOT
45.3k
TG
VREF
LT3763
CTRL2
FBIN
SENSE–
IVINMON
RT
121k
COUT
220µF
×2
RFAULT
47.5kΩ
CVCC
22µF
RFB1
38.3k
FAULT
FB
SS
CSS
10nF
VC
RC
59k
CC
4.7nF
RFB2
12.1k
L1: COILCRAFT XAL1010-152
M1: RENESAS RJK0365
M2: RENESAS RJK0453
RS: VISHAY WSL25122L500FEA
3763 TA05
Efficiency vs Load Current
100
VIN = 12V
VOUT = 5V
ILIMIT = 20A
6
95
EFFICIENCY (%)
VOUT (V)
RSB
10Ω
CS
33nF
Output Voltage Load Regulation
8
RSA
10Ω
M2
PWMOUT
ISMON
PWM
SYNC
RT
500kHz
VOUT
RS
2.5mΩ 5V, 20A MAXIMUM
GND
SENSE+
3V
0V
L1
1.5µH
SW
BG
CTRL1
M1
CBOOST
220nF
BOOST
INTVCC
RNTC
470k
INTVCC
CIN2
100µF
CIN1
4.7µF
4
90
2
85
0
80
0
6
12
ILOAD (A)
18
24
3763 TA05b
VIN = 12V
VOUT = 5V
0
6
12
ILOAD (A)
18
24
3763 TA05c
Rev. C
26
For more information www.analog.com
LT3763
TYPICAL APPLICATIONS
350W White LED Driver
VIN
48V
REN1
374k
REN2
124k
IVINP
IVINN
VIN
EN/UVLO
TG
VREF
CREF
2.2µF
BG
CTRL1
SENSE+
FBIN
SENSE–
RT
200k
RFAULT
100k
CVCC
22µF
M2
×2
LUMINUS
PT-121
CS
1nF
RFB1
931k
FAULT
SYNC
RT
400kHz
FB
SS
VC
CSS
10nF
RC
5k
CC
5nF
Maximum Output Voltage
3763 TA06
Efficiency vs LED Current
100
30
95
EFFICIENCY (%)
VOUT (V)
RFB2
30.9k
L1: COILTRONICS HC2-6R0
M1, M2: RENESAS RJK0851
RS: VISHAY WSL25125L000
40
20
10
0
VOUT
37V, 10A MAXIMUM
RS
5mΩ
PWMOUT
ISMON
PWM
INTVCC
L1
6µH
COUT
10µF
×6
GND
IVINMON
M1
×2
SW
INTVCC
50k
CBOOST
220nF
BOOST
LT3763
CTRL2
3V
0V
CIN2
100µF
CIN1
4.7µF
90
85
VIN = 48V
ILIMIT = 10A
0
3
6
ILED (A)
9
12
80
3763 TA06b
VIN = 48V
VOUT = 35V
0
3
6
ILED (A)
9
12
3763 TA06c
Rev. C
For more information www.analog.com
27
LT3763
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV I 0211
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev. C
28
For more information www.analog.com
LT3763
REVISION HISTORY
REV
DATE
DESCRIPTION
A
05/13
Clarified switching frequency resistor values
3
Clarified offset voltage conditions
4
Clarified programming resistor value
4
Clarified end of 7th paragraph
13
Clarified CBOOST capacitor
17
Clarified programming resistor value and Figure 10
19
Clarified schematic
B
C
10/15
10/19
PAGE NUMBER
25, 27, 30
Revised UVLO hysteresis equation
20
Corrected inductor part number
25
Clarified schematic
30
EC Table Fault Comparator Lower Fault Threshold (FB Falling) Specification; Max Number Changed from 0.26V to 0.265V
3
Incorrect Table Number, Table Heading and Text Reference; Change Table 6 to Table 5
22
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
29
LT3763
TYPICAL APPLICATION
70W, Solar Energy Harvester Compatible with Maximum Power Point Regulation
RSENSE_IN
10mΩ
PANEL VOLTAGE
UP TO 60V
37V VIN REG POINT
RFILTA
1k
CFILT
1µF
IVINP
ENABLE
CREF
2.2µF
RFILTB
1k
IVINN
CIN1
4.7µF
VIN
EN/UVLO
TG
VREF
RHOT
45.3k
LT3763
CTRL2
CBOOST
100nF
BOOST
VREF
CTRL1
RFAULT
47.5kΩ
SENSE+
M2
PWMOUT
ISMON
PWM
COUT
50µF
RSA
10Ω
RSB
10Ω
RFB1
121k
FAULT
SYNC
RT
RT
82.5k
CVCC
22µF
CS
33nF
SENSE–
IVINMON
INTVCC
VOUT
RS
10mΩ 14V MAXIMUM
GND
FBIN
RFBIN2
12.1k
L1
12µH
12V
BG
RFBIN1
348k
M1
SW
INTVCC
RNTC
470k
CIN2
100µF
FB
SS
CSS
10nF
VC
RC
26.1k
CC
4.7nF
L1: COILCRAFT MSS1278-123
M1, M2: INFINEON BSC100N06LS3
M3: VISHAY VN2222LL
RS: VISHAY WSL2512R0100FEA
RFB2
12.1k
RFB3
182k
M3
3763 TA07
Solar Powered SLA Battery
Charging
FAULT
10V/DIV
VIN
500mV/DIV
AC-COUPLED
IL
2A/DIV
VOUT
50mV/DIV
50s/DIV
3763 TA07b
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT3743
Synchronous Step-Down LED Driver Controller
92% Efficiency, IOUT to 20A, VIN: 5.5V to 36V, IQ = 2mA, ISD < 1µA, 4mm × 5mm
QFN-28, TSSOP-28E
LT3741
Synchronous Step-Down LED Driver Controller
94% Efficiency, IOUT to 20A, VIN: 6V to 36V, IQ = 1.8mA, ISD < 1µA, 4mm × 4mm
QFN-20, TSSOP-20E
LT3791
Synchronous Buck-Boost LED Driver Controller
98.5% Efficiency, IOUT to 25A, VIN: 4.7V to 60V, TSSOP-38E
Rev. C
30
10/19
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