LT3992
Monolithic Dual Tracking
3A Step-Down Switching Regulator
Description
Features
Wide Input Range:
– Operation from 3V to 60V
n Independent Supply, Shutdown, Soft-Start, UVLO,
Programmable Current Limit and Programmable
Power Good for Each 3A Regulator
n Die Temperature Monitor
n Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2MHz with Synchronized
Clock Output
n Independent Synchronized Switching Frequencies
Optimize Component Size
n Antiphase Switching
n Outputs Can Be Paralleled
n Flexible Output Voltage Tracking
n Low Dropout: 95% Maximum Duty Cycle
n 5mm × 5mm QFN Package
n FMEA Compliant 38-Pin Exposed Pad TSSOP Package
The LT®3992 is a dual current mode PWM step-down
DC/DC converter with two internal 4.6A switches. Independent input voltage, shutdown, feedback, soft-start,
UVLO current limit and comparator pins for each channel
simplify complex power supply tracking and sequencing
requirements.
n
To optimize efficiency and component size, both converters have a programmable maximum current limit and are
synchronized to either a common external clock input, or
a resistor settable fixed 250kHz to 2MHz internal oscillator.
A frequency divider is provided for channel 1 to further
optimize component size. At all frequencies, a 180° phase
relationship between channels is maintained, reducing voltage ripple and component size. A clock output is available
for synchronizing multiple regulators.
Minimum input to output voltage ratios are improved by
allowing the switch to stay on through multiple clock cycles
only switching off when the boost capacitor needs recharging. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent current to 3V
C3
SW
LT3992
IND
VOUT
VBST – VSW = VOUT
VBST(MAX) = VIN + VOUT
BST
IND
VOUT
VOUT < 3V
GND
VBST – VSW = VX
VBST(MAX) = VX
VX(MIN) = VIN + 3V
(7c)
VOUT < 3V
GND
3992 F07
(7d)
Figure 7. BST Pin Considerations
The minimum input voltage of an LT3992 application is
limited by the minimum operating voltage (typically 2.9V)
and by the maximum duty cycle as outlined above. For
proper start-up, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3992 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages, and on the arrangement of the boost
circuit. The Typical Performance Characteristics section
shows plots of the minimum load current to start and to
run as a function of input voltage for 3.3V outputs. In many
cases the discharged output capacitor will present a load
to the switcher which will allow it to start. The plots show
the worst-case situation where VIN is ramping very slowly.
Use a Schottky diode for the lowest start-up voltage.
Outputs Greater Than 6V
For outputs greater than 6V, add a resistor of 1k to 2.5k
across the inductor to damp the discontinuous ringing of
the SW node, preventing unintended SW current. The 24V
output circuit in the Typical Applications section shows
the location of this resistor.
Frequency Compensation
The LT3992 uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3992 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
VC pin. Generally a capacitor and a resistor in series to
ground determine loop gain. In addition, there is a lower
value capacitor in parallel. This capacitor is not part of
the loop compensation but is used to filter noise at the
switching frequency.
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LT3992
Applications Information
Synchronization
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the compensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
The RT/SYNC pin can also be used to synchronize the
regulators to an external clock source. Driving the RT/SYNC
resistor with a clock source triggers the synchronization
detection circuitry. Once synchronization is detected, the
rising edge of SW1 will be synchronized to the rising edge
of the RT/SYNC signal and the rising edge of SW2 synchronized to the falling edge of the RT/SYNC signal (see
Figures 10 and 11). During synchronization, a 0V to 2.4V
square wave with the same frequency and duty cycle as
the synchronization signal is output via the CLKOUT pin
with a typical propagation delay of 250ns. In addition, an
internal AGC loop will adjust slope compensation to avoid
subharmonic oscillation. If the synchronization signal is
halted, the synchronization detection circuitry will timeout
in typically 10µs at which time the LT3992 reverts to the
free-running frequency based on the RT/SYNC pin voltage.
The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the
stability using a transient load.
Figure 8 shows an equivalent circuit for the LT3992 control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that
the output capacitor integrates this current, and that the
capacitor on the VC pin (CC) integrates the error amplifier
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor in series with CC.
The synchronizing clock signal input to the LT3992 must
have a frequency between 200kHz and 2MHz, a duty cycle
between 20% and 80%, a low state below 0.5V and a high
state above 1.6V. Synchronization signals outside of these
parameters will cause erratic switching behavior. If the
RT/SYNC pin is held above 1.6V at any time, switching
will be disabled.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
capacitor (CPL) across the feedback divider may improve
the transient response.
If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must remain below 1V until the synchronization circuitry
is active for proper start-up operation.
LT3992
CURRENT MODE
POWER STAGE
gm = 4.8mho
OUTPUT
gm = 400µmho
3.6M
RC
CF
CC
+
–
VC
ERROR
AMP
R1
CPL
ESR
FB
C1
+
0.806V
R2
C1
CERAMIC
TANTALUM
OR
POLYMER
3992 F08
Figure 8. Model for Loop Response
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LT3992
Applications Information
If the synchronization signal powers up in an undetermined
state (VOL, VOH, Hi-Z), connect the synchronization clock
to the LT3992 as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3992
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
If the synchronization signal powers up in a low impedance
state (VOL), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the startup frequency.
If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
RT/SYNC pin to ground will set the start-up frequency.
VOUT1
LT3992
PG1
RT/SYNC
tP
SW1
tP
tP/2
SW2
tP
tP/2
CLKOUT
tDCLKOSW1
tDCLKOSW2
tP/2
tP
RT/SYNC
3992 F10
tDRTSYNC
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%
tP
VCC
SYNCHRONIZATION
CIRCUITRY
SW1
CLK
tP
3992 F09
SW2
tPON
Figure 9. Synchronous Signal Powered from Regulator’s Output
tP
CLKOUT
tDCLKOSW1
tDCLKOSW2
tPON
tP
RT/SYNC
3992 F11
tDRTSYNCH
tDRTSYNCH
Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
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LT3992
Applications Information
Reducing Input Ripple Voltage
Shutdown and Undervoltage/Overvoltage Lockout
Synchronizing the switches to the rising and falling edges
of the synchronization signal provides the unique ability to
reduce input ripple currents in systems where VIN1 and VIN2
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3992 with a 71%
duty cycle synchronization signal.
Typically, undervoltage lockout (UVLO) is used in situations where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source current increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where these problems might occur.
SW1
SW2
An internal comparator will force both channels into shutdown below the minimum VIN1 of 2.9V. This feature can be
used to prevent excessive discharge of battery-operated
systems. In addition to the VIN1 undervoltage lockout, both
channels will be disabled when SHDN1 is less than 1.32V.
Programmable UVLO may be implemented using an input
voltage divider and one of the internal comparators (see
the Typical Applications section).
INPUT
RIPPLE V
RT/SYNC
3992 F12
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
When the SHDN pin is taken above 1.32V, its respective
channel is allowed to operate. When the SHDN pin is
driven below 1.32V, its channel is placed in a low quiescent
current state. There is no hysteresis on the SHDN pins.
Keep the connections from any series resistors to the SHDN
pins short and make sure that the interplane or surface
capacitance to switching nodes is minimized.
SW1
SW2
Soft-Start
INPUT
RIPPLE V
RT/SYNC
3992 F13
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
The output of the LT3992 regulates to the lowest voltage
present at either the SS pin or an internal 0.806V reference.
A capacitor from the SS pin to ground is charged by an
internal 12µA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
tRAMP =
CSS • 0.806V
12µA
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 12µA current source
starts to charge the SS pin.
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LT3992
Applications Information
When the SS pin voltage is below 110mV, the VC pin is
pulled low which disables switching. This allows the SS
pin to be used as an individual shutdown for each channel.
As the SS pin voltage rises above 110mV, the VC pin is
released and the output is regulated to the SS voltage.
When the SS pin voltage exceeds the internal 0.806V
reference, the output is regulated to the reference. The
SS pin voltage will continue to rise until it is clamped at
typically 2.15V.
when the threshold is exceeded. The CMPO pin is active
(sink capability is reduced in shutdown and undervoltage
lockout mode) as long as the VIN1 pin voltage exceeds
typically 2.9V.
The comparators can be used to monitor input and output
voltages as well as die temperature. See the Typical Applications circuit collection for examples.
Output Tracking/Sequencing
In the event of a VIN1 undervoltage lockout, the soft-start
latch is set for both channels, triggering a full start-up
sequence. If a channel’s SHDN pin is driven below 1.32V,
its overvoltage lockout is enabled, or the internal die
temperature for its power switch exceeds its maximum
rating during normal operation, the soft-start latch is set
for that channel.
Complex output tracking and sequencing between channels
can be implemented using the LT3992’s SS and CMPO
pins. Figure 14 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
In addition, if the load exceeds the maximum output switch
current, the output will start to drop causing the VC pin
clamp to be activated. As long as the VC pin is clamped,
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output is
loaded by 1Ω the SS pin will drop to 0.46V, regulating the
output at 4.6V ( 4.6A • 1Ω ). Once the overload condition
is removed, the output will soft start from the temporary
voltage level to the normal regulation point.
Ratiometric tracking is achieved in Figure 14b by connecting both SS pins together. In this configuration, the
SS pin source current is doubled (24µA) which must be
taken into account when calculating the output rise time.
Since the SS pin is clamped at typically 2.15V and has to
discharge to 0.806V before taking control of regulation,
momentary overload conditions will be tolerated without
a soft-start recovery. The typical time before the SS pin
takes control is:
t SS(CONTROL) =
CSS •1.2V
0.9mA
Open-Collector Comparators
The CMPO pin is the open-collector output of an internal
comparator. The comparator compares the CMPI pin voltage to 90% of the reference voltage (0.72V) with 80mV
of hysteresis.
The CMPO pin has a typical sink capability of 250µA when
the CMPI pin is below the threshold and can withstand 60V
Independent soft-start for each channel is shown in Figure 14a. The output ramp time for each channel is set by
the soft-start capacitor as described in the soft-start section.
By connecting a feedback network from VOUT1 to the SS2
pin with the same ratio that sets VOUT2 voltage, absolute
tracking shown in Figure 14c is implemented. The minimum value of the top feedback resistor (R1) should be set
such that the SS pin can be driven all the way to ground
with 0.9mA of sink current when VOUT1 is at its regulated
voltage. In addition, a small VOUT2 voltage offset will be
present due to the SS2 12µA source current. This offset
can be corrected for by slightly reducing the value of R2.
Figure 14d illustrates output sequencing. When VOUT1 is
within 10% of its regulated voltage, CMPO1 releases the
SS2 soft-start pin allowing VOUT2 to soft-start. In this case
CMPO1 will be pulled up to 2V by the SS pin. If a greater
voltage is needed for CMPO1 logic, a pull-up resistor to
VOUT1 can be used. This will decrease the soft-start ramp
time and increase tolerance to momentary shorts.
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 14e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 0.9mA of sink current
during power-up and fault conditions.
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LT3992
Applications Information
Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
5ms/DIV
LT3992
FB1
CMPI1
+
–
0.1µF
12µA
0.72V
+
–
FB1
CMPI1
2.5V
12µA
0.72V
SS1
+
–
CMPO2
R2
2.5V
PG2
12µA
0.72V
SS2
12µA
PG1
0.72V
R4
R5
FB2
CMPI2
2.5V
PG2
12µA
0.72V
SS2
R8
0.22µF
(14a)
PG1
VOUT2
R6
CMPO2
+
–
+
–
R3
R2
CMPO1
0.1µF
R4
FB2
CMPI2
FB1
CMPI1
2.5V
VOUT2
R5
R1
SS1
R6
VOUT1
R3
CMPO1
0.1µF
FB2
CMPI2
SS2
R1
PG1
R4
LT3992
VOUT1
R3
R2
CMPO1
VOUT2
2.5V
10ms/DIV
LT3992
R1
0.72V
PG2
10ms/DIV
VOUT1
2.5V
VOUT2
0.5V/DIV
PG2
PG2
SS1
PG1
PG1
PG1
12µA
VOUT1
0.5V/DIV
CMPO2
+
–
R6
R5
PG2
R7
(14b)
(14c)
Output Sequencing
Controlled Power Up and Down
VOUT1
0.5V/DIV
VOUT1
0.5V/DIV
PG1/PG2
VOUT2
0.5V/DIV
VOUT2
0.5V/DIV
PG1
SS1/2
PG2
10ms/DIV
10ms/DIV
LT3992
LT3992
VOUT1
VOUT1
R1
FB1
CMPI1
2.5V
12µA
0.72V
SS1
+
–
0.1µF
R1
R2
2.5V
CMPO1
R4
12µA
SS2
0.72V
+
–
CMPO2
0.72V
SS1
+
–
VOUT2
2.5V
12µA
PG1
R5
FB2
CMPI2
FB1
CMPI1
+
–
R2
CMPO1
PG1
VOUT2
R4
R6
R5
FB2
CMPI2
2.5V
PG2
R3
12µA
SS2
0.72V
+
–
0.22µF
R6
R5
CMPO2
PG2
3992 F14
(14d)
(14e)
Figure 14. SS Pin Configurations
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LT3992
Applications Information
Application Optimization
For example, assume a maximum input of 60V:
In multiple channel applications requiring large VIN to
VOUT ratios, the maximum frequency and resulting inductor size is determined by the channel with the largest
ratio. The LT3992’s multi-frequency operation allows the
user to minimize component size for each channel while
maintaining constant frequency operation. The circuit in
Figure 15 illustrates this approach. A 2-stage step-down
approach coupled with multi-frequency operation will
further reduce external component size by allowing an
increase in frequency for the channel with the lower VIN
to VOUT ratio. The drawback to this approach is that the
output power capability for the first stage is determined by
the output power drawn from the second stage. The dual
step-down application in Figure 16 steps down the input
voltage (VIN1) to the highest output voltage then uses that
voltage to power the second output (VIN2). VOUT1 must be
able to provide enough current for its output plus VOUT2
maximum load. Note that the VOUT1 voltage must be above
VIN2’s minimum input voltage as specified in the Electrical
Characteristics (typically 2.9V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the CMP01 output.
VIN = 60V, VOUT1 = 3.3V at 1.5A and VOUT2 = 12V at 1.5A.
Frequency (Hz) =
L=
VOUT + VD
1
•
VIN – VSW + VD tON(MIN)
( VIN – VOUT ) • VOUT
VIN • f
Single Step-Down:
3.3+ 0.6
1
•
≅ 350kHz
60V – 0.4+ 0.6 180ns
(60V – 3.3) • 3.3 ≥ 9µH
L1=
60V • 350kHz
(60V – 12) •12 ≥ 27µH
L2 =
60V • 350kHz
Frequency (Hz) =
2-Stage Step-Down:
12+ 0.6
1
•
≅ 1MHz
60V – 0.4+ 0.6 180ns
(60V – 12) •12 ≥ 10µH
L1=
60V •1MHz
Frequency (Hz) =
L2 =
(12 – 3.3) • 3.3 ≥ 2.4µH
12 •1MHz
2-Stage Step-Down Multi-Frequency:
RDIV = 61.9k, FREQ1 = 900kHz, FREQ2 = 1800kHz.
L1=
(60V – 12) •12 ≥ 11µH
L2 =
(12 – 3.3) • 3.3 ≥ 1.3µH
60V • 900kHz
12 •1800kH z
In addition, RILIM2 = 52.3k reduces the peak current limit
on Channel 2 to 2.5A, which reduces inductor size and
catch diode requirements.
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LT3992
Applications Information
VIN1
15V TO 60V
4.7µF
4.7µF
VIN2
VIN1
SHDN1
VOUT1
3.3V
1.5A
200kHz
22µH
0.47µF
BST2
SW1
SW2
IND1
LT3992
VOUT1
100µF
×2
100k
24.9k
8.06k
SHDN2
BST1
FB1
PG1
1000pF
CMPO1
CMPO2
SS2
ILIM2
VC2
60.4k
13k
DIV
10k
0.22µF
113k
FB2
CMPI2
RT/SYNC
33pF
22µH
VOUT2
CMPI1
SS1
ILIM1
VC1
0.1µF
IND2
VOUT1
CLKOUT
TJ
GND
100k
PG2
ILIM1
CLKOUT
400kHz
10nF
61.9k
47µF
8.06k
VOUT2
12V
1.5A
400kHz
0.1µF
680pF
33pF
15k
3992 F15
Figure 15. 12V and 3.3V Dual Step-Down Multi-Frequency Converter
VIN1
15V TO 60V
4.7µF
VOUT2
VIN2
VIN1
SHDN1
22µH
0.1µF
VOUT1
12V
1A
400kHz
BST1
BST2
SW1
SW2
IND1
IND2
VOUT1
100k
10µF
8.06k
113k
SHDN2
LT3992
FB1
PG
0.1µF
60.4k
680pF
CMPO1
CMPO2
15k
DIV
48.7k
102k
24.9k
FB2
CMPI2
SS2
ILIM2
VC2
RT/SYNC
CLKOUT
GND
0.1µF
VOUT2
3.3V
2A
47µF 1600kHz
VOUT2
CMPI1
SS1
ILIM1
VC1
33pF
2.2µH
TJ
FB1
8.06k
ILIM1
CLKOUT
1600kHz
10nF
33pF
470pF
0.1µF
16k
3992 F16
Figure 16. 12V and 3.3V 2-Stage Multi-Frequency Step-Down Converter
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LT3992
Applications Information
Shorted and Reverse Input Protection
If the inductor is chosen so that it won’t saturate excessively, an LT3992 step-down regulator will tolerate a shorted
output. There is another situation to consider in systems
where the output will be held high when the input to the
LT3992 is absent. This may occur in battery charging
applications or in battery back-up systems where a battery
or some other supply is diode OR-ed with the LT3992’s
output. If the VIN1/2 pin is allowed to float and the SHDN
pin is held high (either by a logic signal or because it is
tied to VIN), then the LT3992’s internal circuitry will pull its
quiescent current through its SW pin. This is fine if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the VIN pin is grounded while the output
is held high, then parasitic diodes inside the LT3992 can
pull large currents from the output through the SW pin
and the VIN1/2 pin. Figure 17 shows a circuit that will run
only when the input voltage is present and that protects
against a shorted or reversed input.
at one location, ideally at the ground terminal of the output capacitor C2. Route all small signal analog returns
to the ground connection at the bottom of the package.
Additionally, the SW and BST traces should be kept as
short as possible.
VIN LT3992 SW
GND
(18a)
VIN LT3992 SW
GND
(18b)
VIN LT3992 SW
PARASITIC DIODE
D4
VIN1/2
GND
VIN
SW
VOUT1/2
(18c)
LT3992
3992 F17
Figure 17. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 18
shows the high di/dt paths in the buck regulator circuit.
Note that large switched currents flow in the power switch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit board and their connections should be made on that
layer. Place a local, unbroken ground plane below these
components, and tie this ground plane to system ground
3992 F18
Figure 18. Subtracting the Current When the Switch Is On (18a)
from the Current When the Switch Is Off (18b) Reveals the Path of
the High Frequency Switching Current (18c). Keep this Loop Small.
The Voltage on the SW and BST Traces Will Also Be Switched; Keep
These Traces As Short As Possible. Finally, Make Sure the Circuit
Is Shielded with a Local Ground Plane
Thermal Considerations
The PCB must also provide heat sinking to keep the LT3992
cool. The exposed metal on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to other copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3992.
Place additional vias near the catch diodes. Adding more
copper to the top and bottom layers and tying this copper
to the internal planes with vias can further reduce thermal
resistance. The topside metal and component outlines
in Figure 19 illustrate proper component placement and
trace routing.
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25
LT3992
Applications Information
3992 F19
Figure 19. PCB Top Layer and Component Placement for TSSOP and QFN Packages
The LT3992’s powerful 4.6A switches allow the converter
to source large output currents. Depending on the converter’s operating conditions, the resulting internal power
dissipation can raise the junction temperature beyond
its maximum rating. Operating conditions include input
voltages, output voltages, switching frequencies, output
currents, and the ambient environmental temperature,
etc. An estimation of the junction temperature rise above
ambient temperature helps determine whether a given
design may exceed the maximum junction ratings for
specific operating conditions. However, temperature rise
depends on PCB design and the proximity to other heat
sources. The final converter design must be evaluated
on the bench.
as heat sources. After the operating conditions have been
determined, the individual power losses are calculated by:
⎛ V ⎞
PowerD1,2 = ⎜ 1− OUT ⎟ •IOUT • VFD
VIN ⎠
⎝
An estimation of the junction temperature rise begins by
determining which circuit components dissipate power.
In order to simplify the power loss estimation, only the
inductors, catch diodes, and the LT3992 will be considered
where:
26
PowerIND1,2 = RIND •IOUT 2
V
PowerCH1,2 = 0.1• OUT •I OUT 2 + 2•10 –3
VIN
IOUT • VOUT • VBOOST
•VIN +
+
40• VIN
⎛ VIN IOUT ⎞
VIN •IOUT • fSW •10 −6 • ⎜
+
⎝ 2.5 0.25 ⎟⎠
fSW = Switching Frequency in kHz
RIND =Inductor Resis tance
VFD = Catch Diode Forward Voltage Drop
VBOOST = Switch Boost Voltage
3992fa
For more information www.linear.com/LT3992
LT3992
Applications Information
For the LT3992 demo board using the TSSOP package,
the estimated junction temperature rise above ambient
temperature is found by:
TRISETSSOP ≈ 10•(PowerD1 +PowerD2 )+
12.3•(PowerIND1 +Power IND2)+17.5•
(PowerCH1 +PowerCH2 )
The estimated junction temperature rise above ambient
for the LT3992 QFN layout is:
TRISEQFN ≈ 8.5•(Power D1+Power D2)+
13•(Power IND1+Power IND2)+ 23•
(PowerCH1 +PowerCH2 )
For example, the typical application circuits listed in Table 4
are used to calculate the individual power loss contributions in Table 5. Table 6 shows the estimated power loss
and junction temperature rise above ambient temperature.
Note that the larger TSSOP package demonstrates better
thermal performance than the compact QFN package on
the LT3992 demo circuit boards. For LT3992 applications
that favor thermal performance, the TSSOP package is
the preferred package option.
Table 4
APPLICATION
VIN1 VIN2
(V) (V)
fSW
CH1
fSW
CH2
VOUT1 IOUT1 VOUT2 IOUT2
(V)
(A)
(V)
(A)
Front Page
48
12
400
1600
12
1.5
5
2
Back Page
48
48
300
300
5
2
3
2
Table 5
APPLICATION
PD1
(W)
PD2
(W)
PL1
(W)
PL2
(W)
PCH1
(W)
PCH2
(W)
Front Page
0.54
0.56
0.23
0.28
0.99
0.79
Back Page
0.88
0.92
0.28
0.2
0.95
0.91
Table 6
PLOSS (W)
TRISE TSSOP (°C)
TRISE QFN (°C)
rise. However, the LT3992 is a very versatile converter.
The combination of independent input voltages, output
voltages, output currents, switching frequencies, and
package selections for the LT3992 dictate that no power
loss estimation scheme can accommodate every possible
operating condition. As such, it is absolutely necessary to
evaluate a converter’s performance at the bench.
The power dissipation in the other power components such
as boost diodes, input and output capacitors, inductor
core loss, and trace resistances cause additional copper
heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal
Considerations section.
Die Temperature and Thermal Shutdown
The LT3992 TJ pin outputs a voltage proportional to the
internal junction temperature. The TJ pin typically outputs
250mV for 25°C and has a slope of 10mV/°C. Without the
aid of external circuitry, the TJ pin output is valid from 20°C
to 150°C (200mV to 1.5V) with a maximum load of 100µA.
Full Temperature Range Measurement
To extend the operating temperature range of the TJ output below 20°C, connect a resistor from the TJ pin to a
negative supply as shown in Figure 20. The negative rail
voltage and TJ pin resistor may be calculated using the
following equations:
2 • TEMP(MIN)°C
100
|V |
R1 ≤ NEG
33µA
where:
VNEG ≤
TEMP(MIN)°C is the minimum temperature where a
valid TJ pin output is required.
VNEG = Regulated negative voltage supply.
APPLICATION
CALC
MEAS
CALC
MEAS
CALC
MEAS
Front Page
3.38
3.2
48.3
46.1
56.8
53.3
For example:
Back Page
4.14
4.2
56.4
53.0
64.3
62.9
TEMP(MIN)°C = –40°C
The power loss and temperature rise equations provided
in the Thermal Considerations section serve as a good
starting point for estimating the junction temperature
VNEG ≤ –0.8V
VNEG = –1, R1 ≤ |VNEG|/33µA = 30.2kΩ
3992fa
For more information www.linear.com/LT3992
27
LT3992
Applications Information
LT3992
TJ
R1
VNEG
GND
+
3992 F20
Figure 20. Circuit to Extend the TJ Pin Operating Range
TJ
LT3992
30k
330pF
Other Linear Technology Publications
D4
CLKOUT
GND
D3, D4: ZETEX BAT54S
0.1µF
D3
the CLKOUT pin, resulting in an output synchronization
clock signal phase delay. Figures 22 and 23 show the impact of capacitive loading on the CLKOUT signal rise and
fall times. Note that a typical 10:1 150MHz oscilloscope
probe contributes significant capacitance to the CLKOUT
node, necessitating a low capacitance probe for accurate
measurements. Applications requiring CLKOUT to generate
the negative supply voltage and provide the synchronization clock to other regulators may benefit from buffering
CLKOUT prior to the charge pump circuitry.
3992 F21
Figure 21. Circuit to Generate the Negative Voltage Rail to
Extend the TJ Pin Operating Range
Generating a Negative Regulated Voltage
The simple charge pump circuit in Figure 21 uses the
CLKOUT pin output to generate a negative voltage, eliminating the need for an external regulated supply. Surface
mount capacitors and dual-package Schottky diodes
minimize the board area needed to implement the negative voltage supply.
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note DN100
shows how to generate a dual (+ and –) output supply
using a buck regulator.
500mV/DIV
As a safeguard, the LT3992 has an additional thermal
shutdown threshold set at a typical value of 163°C for each
channel. Each time the threshold is exceeded, a power on
sequence for that channel will be initiated. The sequence
will then repeat until the thermal overload is removed.
It should be noted that the TJ pin voltage represents
a steady-state temperature and should not be used to
guarantee that maximum junction temperatures are
not exceeded. Instantaneous power along with thermal
gradients and time constants may cause portions of the
die to exceed maximum ratings and thermal shutdown
thresholds. Be sure to calculate die temperature rise for
steady state (>1Min) as well as impulse conditions.
CLKOUT Capacitive Loading
A minor drawback to generating a negative rail from the
CLKOUT pin is that the charge pump adds capacitance to
28
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED LT3992
RT/SYNC PIN
FET PROBE: 2pF
40ns/DIV
FREQUENCY: 1.000MHz
3992 F22
Figure 22. CLKOUT Rise Time
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED
LT3992 RT/SYNC PIN
500mV/DIV
FET PROBE: 2pF
20ns/DIV
FREQUENCY: 1.000MHz
3992 F23
Figure 23. CLKOUT Fall Time
3992fa
For more information www.linear.com/LT3992
VOUT1
5V
1.5A
300kHz
0.1µF
100k
33pF
11.8k
1000pF
8.06k
34.8k
42.2k
15µH
4.7µF
For more information www.linear.com/LT3992
102k
DIV
GND
TJ
CLKOUT
ILIM1
VC1
RT/SYNC
SS2
ILIM2
VC2
SS1
CMPO2
CMPO1
FB2
VOUT2
IND2
CMPI2
LT3992
SW2
SHDN2
BST2
VIN2
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
10nF
16.9k
2.2µH
33pF
100pF
0.1µF
16.9k
470pF
8.06k
1µF
47µF
42.2k
100k
8.06k
10k
0.1µF
CLOCKOUT
1200kHz
PG
VOUT2
2.5V
1A
1200kHz
8.06k
4.02k
VOUT3
1.2V
1A
1200kHz
42.2k
8.06k
100µF
0.1µF
33pF
4.02k
2.2µH
10k
470pF
100pF
1µF
DIV
SS2
ILIM2
VC2
TJ
CLKOUT
GND
RT/SYNC
ILIM1
VC1
SS1
CMPO2
CMPI2
FB2
VOUT2
IND2
SW2
SHDN2
BST2
VIN2
LT3992
CMPO1
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
10nF
10k
2.2µH
33pF
0.1µF
100pF
15k
470pF
8.06k
1µF
3992 TA02
42.2k
VOUT4
1.8V
47µF 1A
1200kHz
Typical Applications
47µF
0.47µF
VIN
7V TO 60V
Quad Output 5V, 2.5V, 1.8V and 1.2V Multi-Frequency Synchronized, 2-Stage
Converter with Output Sequencing, Absolute Tracking and Current Limiting
LT3992
29
3992fa
LT3992
TYPICAL APPLICATIONS
24V and 5V 2-Stage Dual Step-Down Converter
VIN1
25V TO 60V
4.7µF
VOUT2
VIN2
VIN1
SHDN1
BST1
22µH
0.1µF
VOUT1
24V
0.5A
1MHz
2k
SW1
SW2
IND1
IND2
VOUT1
100k
10µF
8.06k
232k
PG
SHDN2
BST2
LT3992
33pF
FB1
42.2k
28k
42.2k
FB2
CMPI1
CMPI2
CMPO1
CMPO2
SS2
ILIM2
VC2
RT/SYNC
470pF
0.1µF
DIV
VOUT2
5V
2A
47µF 1MHz
VOUT2
SS1
ILIM1
VC1
0.1µF
4.7µH
CLKOUT
TJ
GND
FB1
CLKOUT
1MHz
10nF
28k
8.06k
33pF
0.1µF
680pF
10k
100k
3992 TA03
3.3V/5A Single Output with UVLO and Power Good
VIN
5V TO 18V
60V TRANSIENT
4.7µF
×2
130k
374k
SHDN2
CMPI2
BST1
CMPO2
SW1
ILIM1
IND1
ILIM2
820pF
CLKOUT
1MHz
33pF
LT3992
20k
28k
10nF
VOUT2
SS2
BST2
VC1
SW2
VC2
IND2
CLKOUT
FB1
RT/SYNC
CMPI1
DIV
0.22µF
4.7µH
0.22µF
4.7µH
24.9k
8.06k
FB2
GND
VOUT
3.3V
47µF 5A
2MHz EFFECTIVE RIPPLE
×2
VOUT1
SS1
TJ
0.1µF
60.4k
VIN2
VIN1
SHDN1
CMPO1
100k
PG
3992 TA04
30
3992fa
For more information www.linear.com/LT3992
LT3992
TYPICAL APPLICATIONS
Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter
VIN1
12V
4.7µF
1µF
47.5k
13k
0.1µF
CLKOUT
2MHz
33pF
64.9k
61.9k
SHDN2
CMPI2
BST1
CMPO2
SW1
SS1
IND1
LT3992
VOUT2
LIM2
BST2
VC1
SW2
VC2
IND2
CLKOUT
FB1
RT/SYNC
CMPI1
0.22µF
2.2µH
47µF
VOUT
3.3V
4A
0.22µF
2.2µH
24.9k
8.06k
FB2
TJ
21k
SHDN1
VOUT1
LIM1
DIV
61.9k
42.2k
VIN2
VIN1
SHDN1
SS2
680pF
VIN2
5V
GND
10nF
CMPO1
3992 TA05
5V and 1.8V Dual 2-Stage Converter
VIN1
7V TO 60V
1µF
4.7µF
VIN1
VIN2
SHDN1
BST1
SHDN2
BST2
SW2
SW1
15µH
0.22µF
VOUT1
5V
1A
400kHz
IND1
LT3992
100k
42.2k
8.06k
PG
FB1
CMPI2
CMPO1
CMPO2
21k
13k
ILIM2
VC2
RT/SYNC
DIV
33pF
48.7k
102k
VOUT2
1.8V
1A
47µF 1600kHz
100pF
FB1
8.06k
SS2
ILIM1
VC1
0.1µF
0.22µF
10k
FB2
CMPI1
SS1
820pF
2.2µH
VOUT2
VOUT1
22µF
IND2
CLKOUT
GND
TJ
ILIM1
CLOCKOUT
1600kHz
33pF
0.1µF
470pF
10nF
21k
3992 TA06
3992fa
For more information www.linear.com/LT3992
31
32
22.1k
VIN
13V TO 60V
0.1µF
33pF
7.5k
28k
10nF
CLKOUT
1MHz
ON OFF
1300pF
2.2µF
×2
VOUT1
IND1
BST1
SW1
VIN2
GND
CMPO2
DIV
CMPI2
CMPO1
TJ
RT/SYNC
CMPI1
FB2
FB1
IND2
BST2
SW2
LT3992 VOUT2
CLKOUT
VC2
VC1
SS2
SS1
ILIM2
ILIM1
SHDN2
SHDN1
VIN1
22µH
22µH
133k
8.06k
0.22µF
0.22µF
VOUT2
0.1µF
113k
For more information www.linear.com/LT3992
OUT1
OUT2
MOD
GND
SET
LTC6908-1
V+
PG
200k
VOUT1
12V
0.5A
1MHz
22µF
×2
VOUT2
1.2V
3A
500kHz
VOUT3
0.1µF
100k
8.06k
100µF
×2
33pF
0.1µF
4.02k
2.2µH
SHDN1
7.68k
1000pF
100pF
1µF
61.9k
DIV
SS2
ILIM2
VC2
TJ
CLKOUT
GND
RT/SYNC
ILIM1
VC1
SS1
CMPO2
CMPI2
FB2
VOUT2
IND2
SW2
SHDN2
BST2
VIN2
LT3992
CMPO1
CMPI1
FB1
VOUT1
IND1
SW1
SHDN1
BST1
VIN1
12V, 3.3V and 1.2V Triple Output with External Synchronization, Output Sequencing and Tracking
10nF
SS1
24.9k
2.2µH
SHDN1
33pF
1µF
16k
3992 TA07
470pF
8.06k
100pF
0.1µF
100k
VOUT3
3.3V
3A
100µF 1MHz
LT3992
TYPICAL APPLICATIONS
3992fa
LT3992
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
4.75 REF
38
9.60 – 9.80*
(.378 – .386)
4.75 REF
(.187)
20
6.60 ±0.10
4.50 REF
2.74 REF
SEE NOTE 4
6.40
2.74
REF (.252)
(.108)
BSC
0.315 ±0.05
1.05 ±0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1
0.25
REF
19
1.20
(.047)
MAX
0° – 8°
0.50
(.0196)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.05 – 0.15
(.002 – .006)
FE38 (AA) TSSOP REV C 0910
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3992fa
For more information www.linear.com/LT3992
33
LT3992
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
34
0.25 ± 0.05
0.50 BSC
3992fa
For more information www.linear.com/LT3992
LT3992
Revision History
REV
DATE
DESCRIPTION
A
04/13
Clarified Typical Switching Frequency
PAGE NUMBER
3
Clarified Block Diagram
10
Clarified Figure 1 call out in last paragraph
Clarified Applications Information
12
14, 16
3992fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT3992
35
LT3992
Typical Application
FMEA Fault Tolerant 5V/2A and 3.3V/2A Dual Converter
VIN1
6V TO 60V
4.7µF
SHDN2
VOUT1
5V
2A
300kHz
15µH
0.47µF
249k
100µF
806Ω
4.22k
100k
PG
SS2
ILIM2
33pF
SHDN1
SHDN2
BST1
BST2
SW1
SW2
IND1
VOUT1
FB1
LT3992
10nF
11.8k
IND2
VOUT2
FB2
CMPI1
CMPI2
CMPO1
CMPO2
SS1
ILIM1
VC1
SS2
ILIM2
VC2
RT/SYNC
1000pF
DIV
4.7µF
100k
VIN2
VIN1
CLKOUT
GND
TJ
7.15k
10µH
0.47µF
2.49k
100k
806Ω
100µF
249k
VOUT2
3.3V
2A
300kHz
PG2
CLKOUT
300kHz
10nF
1000pF
12.1k
33pF
100nF
60.4k
3992 TA08
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT3692/
LT3692A
36V, Dual 3.5A, 2.25MHz High Efficiency Step-Down
DC/DC Converter
VIN = 3V to 36V, VOUT(MIN) = 0.8V, IQ = 4mA, ISD < 10µA,
5mm × 5mm QFN-32, TSSOP-38E
LT3507/
LT3507A
36V, Triple 2.4A, 1.4A and 1.4A (IOUT), 2.5MHz, High
Efficiency Step-Down DC/DC Converter with LDO Controller
VIN = 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD = 1µA,
5mm × 7mm QFN-38
LT3508
36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz,
High Efficiency Step-Down DC/DC Converter
VIN = 3.7V to 37V, VOUT(MIN) = 0.8V, IQ = 4.6mA, ISD = 1µA,
4mm × 4mm QFN-24, TSSOP-16E
LT3680
36V, 3A, 2.4MHz High Efficiency Micropower Step-Down
DC/DC Converter
VIN = 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3693
36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter
VIN = 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.3mA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3480
36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation
VIN = 3.6V to 38V, Transients to 60V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3mm × 3mm DFN-10, MSOP-10E
LT3980
58V with Transient Protection to 80V, 2A (IOUT), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
VIN = 3.6V to 58V, Transients to 80V, VOUT(MIN) = 0.79V,
IQ = 75µA, ISD < 1µA, 3mm × 4mm DFN-16, MSOP-16E
LT3971
38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
LT3991
55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down
DC/DC Converter with Only 2.8µA of Quiescent Current
VIN = 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA,
3mm × 3mm DFN-10, MSOP-10E
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT3992
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LT3992
3992fa
LT 0413 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2012
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