LT4256-1/LT4256-2
Positive High Voltage
Hot Swap Controllers
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DESCRIPTIO
FEATURES
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TM
The LT®4256-1/LT4256-2 are high voltage Hot Swap
controllers that allow a board to be safely inserted and
removed from a live backplane. An internal driver drives an
external N-channel MOSFET switch to control supply
voltages ranging from 10.8V to 80V.
Allows Safe Board Insertion and Removal from a
Live Backplane
Controls Supply Voltage from 10.8V to 80V
Foldback Current Limiting
Overcurrent Fault Detection
Drives an External N-Channel MOSFET
Programmable Supply Voltage Power-Up Rate
Undervoltage Protection
Latch Off Operation Mode (LT4256-1)
Automatic Retry (LT4256-2)
Available in an 8-Pin SO Package
The LT4256-1/LT4256-2 features an adjustable analog
foldback current limit. If the supply remains in current limit
for more than a programmable time, the N-channel
MOSFET shuts off and the PWRGD output asserts low. The
LT4256-2 automatically restarts after a time-out delay.
The LT4256-1 latches off until the UV pin is cycled low.
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APPLICATIO S
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The PWRGD output indicates when the output voltage
rises above a programmed level. An external resistor
string from VCC provides programmable undervoltage
protection.
Hot Board Insertion
Electronic Circuit Breaker/Power Bussing
Industrial High Side Switch/Circuit Breaker
24V/48V Industrial/Alarm Systems
Ideally Suited for 12V, 24V and 48V Distributed
Power Systems
48V Telecom Systems
The LT4256 can be used as an upgrade to LT1641 designs.
See Table 1 on page 14 for upgraded specifications.
The LT4256-1 and LT4256-2 are available in an 8-pin SO
package that is pin compatible with the LT1641.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
48V, 2A Hot Swap Controller
0.02Ω
VIN
48V
IRF530
SMAT70A
CMPZ5241B
11V
(SHORT PIN)
8
VCC
64.9k
1
0.1µF
SENSE
GATE
UV
LT4256-1/
LT4256-2
8.06k
FB
PWRGD
5
GND
33nF
CL
7
10Ω
6
36.5k
100Ω
27k
GND
4
VIN
50V/DIV
10nF
VOUT
50V/DIV
INRUSH
CURRENT
500mA/DIV
4.02k
2
3
PWRGD
4256 TA01
TIMER
LT4256 Start-Up Behavior
VOUT
48V
2A
UV = 36V
PWRGD = 40V
PWRGD
50V/DIV
CL = 225µF
2.5ms/DIV
4256 TA02
425612fa
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LT4256-1/LT4256-2
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VCC) ................................ – 0.3 to 100V
SENSE, PWRGD ....................................... – 0.3 to 100V
GATE (Note 2) ................................ – 0.3V to VCC + 10V
Maximum Input Current (GATE) ......................... 200µA
FB, UV ........................................................ – 0.3 to 44V
TIMER ..................................................... – 0.3V to 4.3V
Maximum Input Current (TIMER) ....................... 100µA
Operating Temperature
LT4256C ................................................. 0°C to 70°C
LT4256I ............................................. – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
UV 1
8
VCC
FB 2
7
SENSE
PWRGD 3
6
GATE
GND 4
5
TIMER
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 110°C/W
ORDER PART
NUMBER
LT4256-1CS8
LT4256-1IS8
LT4256-2CS8
LT4256-2IS8
S8 PART MARKING
42561
42561I
42562
42562I
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL
PARAMETER
VCC
Operating Voltage
CONDITIONS
MIN
ICC
Operating Current
VUVLH
Undervoltage Threshold
VUVHYS
Hysteresis
IINUV
UV Input Current
VUVRTH
Fault Latch Reset Threshold Voltage
VSENSETRIP
SENSE Pin Trip Voltage (VCC – VSENSE)
FB = 0V
FB ≥ 2V
IINSNS
SENSE Pin Input Current
VSENSE = VCC
IPU
GATE Pull-Up Current
Charge Pump On, ∆VGATE = 7V
IPD
GATE Pull-Down Current
Any Fault, VGATE = 3V
∆VGATE
External N-Channel Gate Drive (Note 2)
VFB
FB Voltage Threshold
VFBHYS
FB Hysteresis Voltage
VOLPGD
PWRGD Output Low Voltage
IPWRGD
PWRGD Pin Leakage Current
VPWRGD = 80V
IINFB
FB Input Current
FB = 4.5V
ITIMERPU
TIMER Pull-Up Current
TIMER = 3V, During Fault
●
– 63
– 105
–147
µA
ITIMERPD
TIMER Pull-Down Current
TIMER = 3V
●
1.5
3
5
µA
VTHTIMER
TIMER Shut-Down Threshold
CTIMER = 10nF
●
4.3
4.65
5
V
DTIMER
Duty Cycle (RETRY Mode)
●
1.5
3
4.5
%
●
VCC Low-to-High Transition
●
TYP
10.8
MAX
UNITS
80
V
1.8
3.9
mA
3.96
4
4.04
V
0.25
0.4
0.55
V
–0.1
–1.5
–1
–3
µA
µA
UV ≥ 1.2V
UV = 0V
●
0.4
0.85
1.2
V
●
●
5.5
45
14
55
22
65
mV
mV
40
70
µA
– 32
– 63
µA
mA
●
–16
40
62
80
VGATE – VCC, 10.8V ≤ VCC ≤ 20V
20V ≤ VCC ≤ 80V
●
●
4.5
10
8.8
11.6
12.5
12.8
V
V
FB High-to-Low Transition
FB Low-to-High Transition
●
●
3.95
4.2
3.99
4.45
4.03
4.65
V
V
0.3
0.45
0.6
V
0.25
0.6
0.4
1
V
V
0.1
1
µA
–0.1
–1
µA
IO = 1.6mA
IO = 5mA
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LT4256-1/LT4256-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tPHLUV
UV Low to GATE Low
tPLHUV
UV High to GATE High
tPHLFB
FB Low to PWRGD Low
tPLHFB
FB High to PWRGD High
tPHLSENSE
(VCC – VSENSE) High to GATE Low
MIN
CGATE = 0
VCC – VSENSE = 275mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
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TYPICAL PERFOR A CE CHARACTERISTICS
4.1
UV THRESHOLDS (V)
3.9
3.8
3.7
H-L THRESHOLD
3.6
–25
0
25
50
TEMPERATURE (°C)
75
48
20
FB = 0V
0
–50
0
25
50
TEMPERATURE (°C)
75
100
4256 G04
µs
1.5
100
10
20
50
40
VCC (V)
30
60
70
PWRGD Output Voltage
vs IPWRGD
L-H THRESHOLD
5
4.3
4
4.2
4.1
3.9
–50
80
4256 G03
VPWRGD (V)
ICC (mA)
PWRGD THRESHOLDS (V)
75
µs
3
6
3
2
H-L THRESHOLD
4.0
0
25
50
TEMPERATURE (°C)
5
1
0
–25
4.4
–25
3.2
0.5
4.5
0.5
µs
4256 G02
VCC = 48V
1.0
2
2.0
PWRGD Thresholds
vs Temperature
1.5
0.8
1.0
15
ICC vs Temperature
2.0
µs
2.5
4256 G01
2.5
µs
9
3.0
FB > 2V
53
10
–50
100
3
6
3.5
ICC (mA)
SENSE PIN REGULATION VOLTAGE (mV)
L-H THRESHOLD
1.7
ICC vs VCC
58
4.0
UNITS
Specifications are at TA = 25°C unless
SENSE Pin Regulation Voltage
vs Temperature
UV Thresholds vs Temperature
MAX
Note 2: An internal clamp limits the GATE pin to a minimum of 10V above
VCC. Driving this pin to a voltage beyond the clamp voltage may damage
the part.
otherwise noted.
3.5
–50
TYP
–25
0
25
50
TEMPERATURE (°C)
1
75
100
4256 G05
0
0
2
4
6
8
IPWRGD (mA)
10
12
4256 G06
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LT4256-1/LT4256-2
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless
otherwise noted.
GATE Pin Pull-Up Current
vs Temperature
GATE Pin Pull-Down Current
vs Temperature
GATE PIN PULL-DOWN CURRENT (mA)
–10
–15
–20
–25
–30
–35
–40
–50
–25
0
25
50
TEMPERATURE (°C)
75
0.4
62
0.2
0
61
–0.2
60
IUV (µA)
–5
59
–0.8
–1.0
–1.2
56
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
–1.4
100
0
1
2
3
4
20
VUV (V)
30
40
4256 G08
TIMER Pin Currents
vs Temperature
14.0
10
13.5
5
VGATE – VCC VOLTAGE (V)
VCC = 18V
50
4256 G09
VGATE – VCC Voltage
vs Temperature
14
VGATE – VCC VOLTAGE (V)
–0.6
57
VGATE – VCC Voltage
vs Temperature
PULL-DOWN CURRENT
13.0
10
VCC = 12V
VCC = 10.8V
6
0
12.5
8
4
VCC = 20V
12.0
VCC = 48V
VCC = 80V
11.5
–80
PULL-UP CURRENT
–100
11.0
–120
2
0
–50
–0.4
58
4256 G07
12
UV Pin Current vs UV Pin Voltage
63
ITIMER (µA)
GATE PIN PULL-UP CURRENT (µA)
0
10.5
–25
0
25
50
TEMPERATURE (°C)
75
100
10.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
4256 G10
–140
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4256 G12
4256 G11
Timer Shutdown Threshold
vs Temperature
TIMER Pin Currents vs VCC
5.4
5.0
TIMER SHUTDOWN THRESHOLD (V)
PULL-DOWN CURRENT
2.5
0
ITIMER (µA)
100
–80
PULL-UP CURRENT
–100
–120
–140
10
20
30
50
40
VCC (V)
60
70
80
4256 G13
5.2
5.0
4.8
4.6
4.4
4.2
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
4256 G14
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LT4256-1/LT4256-2
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless
otherwise noted.
Gate Pull-Down Capability vs VCC
Below Minimum Operating Voltage
FB Pin Current vs FB Pin Voltage
60
0.1
50
0
40
IFB (µA)
IGATE (mA )
0.2
–0.1
30
–0.2
20
–0.3
10
–0.4
0
10
20
30
VFB (V)
40
50
4256 G15
0
0
2
4
6
VCC (V)
8
10
12
4256 G16
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LT4256-1/LT4256-2
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PI FU CTIO S
UV (Pin 1): Undervoltage Sense. UV is an input that
enables the output voltage. When UV is driven above 4V,
GATE will start charging and the output turns on. When
UV goes below 3.6V, GATE discharges and the output
shuts off.
Pulsing UV low for a minimum of 5µs after a current limit
fault cycle resets the fault latch (LT4256-1) and allows the
part to turn back on. This command is only accepted after
TIMER has discharged below 0.65V. To disable UV sensing, connect UV to a voltage beween 5V and 44V.
FB (Pin 2): Power Good Comparator Input. FB monitors
the output voltage through an external resistive divider.
When the voltage on FB is lower than the high-to-low
threshold of 3.99V, PWRGD is pulled low and released
when FB is pulled above the 4.45V low-to-high threshold.
The voltage present on FB affects foldback current limit
(see Figure 7 and related discussion).
PWRGD (Pin 3): Power Good Output. PWRGD is pulled
low whenever the voltage on FB falls below the 3.99V highto-low threshold voltage. It goes into a high impedance
state when the voltage on FB exceeds the low-to-high
threshold voltage. An external pull-up resistor can pull
PWRGD to a voltage higher or lower than VCC.
GND (Pin 4): Device Ground. This pin must be tied to a
ground plane for best performance.
TIMER (Pin 5): Timing Input. An external timing capacitor
from TIMER to GND programs the maximum time the part
is allowed to remain in current limit. When the part goes
into current limit, a 105µA pull-up current source starts to
charge the timing capacitor. When the voltage on TIMER
reaches 4.65V (typ), GATE pulls low; the TIMER pull-up
current will be turned off and the capacitor is discharged
by a 3µA pull-down current. When TIMER falls below 0.65V
(typ), GATE turns on again for the LT4256-2. UV must be
cycled low after TIMER has discharged below 0.65V (typ)
to reset the LT4256-1. If UV is not cycled low (LT4256-1),
GATE remains latched off and TIMER is discharged to near
GND. Under an output short-circuit condition, the
LT4256-2 cycles on and off with a 3% duty cycle.
GATE (Pin 6): High Side Gate Drive for the External NChannel MOSFET. An internal charge pump guarantees at
least 10V of gate drive for VCC supply voltages above 20V
and 4.5V of gate drive for VCC supply voltages between
10.8V and 20V. The rising slope of the voltage on GATE is
set by an external capacitor connected from GATE to GND
and an internal 32µA pull-up current source from the
charge pump output.
If the current limit is reached, the GATE voltage is adjusted
to maintain a constant voltage across the sense resistor
while the timing capacitor starts to charge. If the TIMER
voltage ever exceeds 4.65V, GATE is pulled low.
GATE is also pulled to GND whenever UV is pulled low, the
VCC supply voltage drops below the externally programmed
undervoltage threshold, or VCC drops below the internal
UVLO threshold (9.8V).
GATE is clamped internally to a maximum voltage of 11.6V
(typ) above VCC under normal operating conditions. Driving this pin beyond the clamp voltage may damage the
part. A Zener diode is needed between the gate and source
of the external MOSFET to protect its gate oxide under
instantaneous short-circuit conditions. See Applications
Information.
SENSE (Pin 7): Current Limit Sense Input. A sense
resistor is placed in the supply path between V CC and
SENSE. The current limit circuit regulates the voltage
across the sense resistor (VCC – SENSE) to 55mV while in
current limit when FB is 2V or higher. If FB drops below
2V, the regulated voltage across the sense resistor decreases linearly to 14mV when FB is 0V.
To defeat current limit, connect SENSE to VCC.
VCC (Pin 8): Input Supply Voltage. The positive supply
input ranges from 10.8V to 80V for normal operation.
ICC is typically 1.8mA. An internal circuit disables the
LT4256-1/LT4256-2 for inputs less than 9.8V (typ).
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LT4256-1/LT4256-2
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BLOCK DIAGRA
VCC
SENSE
8
7
VP
VP GEN
FB
2
–
14mV ~ 55mV
CURRENT
LIMIT
CHARGE
PUMP
AND
GATE
DRIVER
+
+
FOLDBACK
REF GEN
2V
GATE
3
PWRGD
5
TIMER
+
–
3.99V
UV
6
3.99V
–
1
VCC
–
INTERNAL
UV
9.8V
+
4V
–
UV
0.65V
+
LOGIC
+
TIMER LOW
–
VP
108µA
+
TIMER HIGH
4.65V
–
3µA
4
4256 BD
GND
425612fa
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LT4256-1/LT4256-2
TEST CIRCUIT
48k
PWRGD
FB
VCC
48V
+–
SENSE
GATE
UV
TIMER
GND
100pF
4256 F01
Figure 1
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TI I G DIAGRA S
4V
GATE
4.45V
3.6V
UV
3.99V
FB
tPLHUV
tPHLUV
VOUT +2V
VOUT +2V
tPLHFB
PWRGD
1V
tPHLFB
1V
4256 F03
4256 F02
Figure 2. UV to GATE Timing
Figure 3. VOUT to PWRGD Timing
VCC – SENSE
55mV
tPHLSENSE
VCC
GATE
4256 F04
Figure 4. SENSE to GATE Timing
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APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the connector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-1/LT4256-2 are designed to turn on a board’s
supply voltage in a controlled manner, allowing the board
to be safely inserted or removed from a live backplane. The
device also provides undervoltage as well as overcurrent
protection while a power good output signal indicates
when the output supply voltage is ready with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
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LT4256-1/LT4256-2
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APPLICATIO S I FOR ATIO
Q1
IRF530
R5
0.025Ω
VIN
48V
D2
SMAT70A
(SHORT PIN)
8
VCC
R1
64.9k
1
C3
0.1µF
7
SENSE
GATE
UV
6
LT4256-1/
LT4256-2
R2
8.06k
+
D1
CMPZ5241B
11V
FB
2
CL
VOUT
48V
1.6A
R8
36.5k
R6
10Ω
R7
100Ω
C1
10nF
R4
27k
R9
4.02k
5
GND
C2
33nF
TIMER
PWRGD
GND
4
3
PWRGD
4256 F05
UV = 36V
PWRGD = 40V
Figure 5. 1600mA, 48V Application
When the power pins first make contact, transistor Q1 is
held off. If the voltage on VCC is above the externally
programmed undervoltage threshold, VCC is above 9.8V,
and the voltage on TIMER is less than 4.65V (typ), transistor Q1 will be turned on (Figure 6). The voltage on GATE
rises with a slope equal to 32µA/C1 and the supply inrush
current is set at:
IINRUSH = CL • 32µA/C1
(1)
where CL is the total load capacitance.
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resistor R5 reaches VSENSETRIP, the inrush current will be
limited by the internal current limit circuitry. The voltage
on GATE is adjusted to maintain a constant voltage across
the sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high VFB
threshold, PWRGD goes high.
Undervoltage Detection
The LT4256-1/LT4256-2 uses UV to monitor the VCC
voltage to determine when it is safe to turn on the load and
allow the user the greatest flexibility for setting the threshold. Any time that UV goes below 3.6V, GATE will be pulled
low until UV goes above 4V again.
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of
UV’s hysteresis will be lost, making the LT4256-1/
IOUT
500mA/DIV
PWRGD
50V/DIV
VOUT
50V/DIV
GATE
50V/DIV
CL = 125µF
5ms/DIV
4256 F06
Figure 6. Start-Up Waveforms
LT4256-2 more susceptible to noise (VCC must be at least
9.8V when UV is at its 3.6V threshold). UV is filtered with
C3 to prevent noise spikes and capacitively coupled glitches
from shutting down the LT4256-1/LT4256-2 output
erroneously.
To calculate the UV threshold, use the following equations:
⎛V
⎞
R1 = R2 ⎜ THUVLH − 1⎟
⎝ 4V
⎠
(2)
20kΩ ≤ R1 + R2 ≤ 200kΩ
(3)
⎛ R1⎞
VTHUVLH = 3.6 ⎜ 1 + ⎟
⎝ R2 ⎠
(4)
where VTHUVLH is the desired UV threshold voltage when
VCC is rising (L-H), etc.
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LT4256-1/LT4256-2
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APPLICATIO S I FOR ATIO
VCC – VSENSE
RESPONSE TIME (µs)
12
55mV
10
8
6
4
2
14mV
0V
2V
FB
0
4256 F07
50
100
150
VCC – VSENSE (mV)
200
4256 F08
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
Figure 8. Response Time to Overcurrent
Figure 11 shows how the LT4256-1/LT4256-2 are commanded to shut off with a logic signal. This is accomplished by pulling the gate of the open-drain MOSFET, Q2,
(tied to the UV pin) high.
For a 0.025Ω sense resistor, the current limit is set at
2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 105.6W to
26.5W. See the Layout Considerations section for important information about board layout to minimize current
limit threshold error.
Short-Circuit Protection
The LT4256-1/LT4256-2 features a programmable foldback
current limit with an electronic circuit breaker that protects
against short circuits or excessive load currents. The
current limit is set by placing a sense resistor (R5)
between VCC and SENSE. The current limit threshold is
calculated as:
ILIMIT = 55mV/R5
(5)
where R5 is the sense resistor.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-1/LT4256-2 go into current limit when the
voltage on FB is 0V, the current limit circuit drives the
GATE pin to force a constant 14mV drop across the sense
resistor. As the output at FB increases, the voltage across
the sense resistor increases until the FB pin reaches 2V, at
which point the voltage across the sense resistor is held
constant at 55mV (see Figure 7).
The LT4256-1/LT4256-2 also features a variable
overcurrent response time. The time required for the part
to regulate the GATE voltage is a function of the voltage
across the sense resistor connected between VCC and
SENSE. This helps to eliminate sensitivity to current
spikes and transients that might otherwise unnecessarily
trigger a current limit response and increase MOSFET
dissipation. Figure 8 shows the response time as a function of the overdrive at SENSE.
TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, the TIMER pin is
pulled to GND by a 3µA current source. When the current
limit circuitry becomes active, a 108µA pull-up current
source is connected to TIMER and the voltage will rise with
a slope equal to 105µA/CTIMER as long as the circuitry
stays active. Once the desired maximum current limit time
is known, the capacitor value is:
C[nF] = 25 • t[ms]; C =
105µA
•t
4.65 V
(6)
425612fa
10
LT4256-1/LT4256-2
U
W
U
U
APPLICATIO S I FOR ATIO
IOUT
500mA/DIV
IOUT
500mA/DIV
TIMER
5V/DIV
TIMER
5V/DIV
VOUT
50V/DIV
VOUT
50V/DIV
GATE
50V/DIV
GATE
50V/DIV
10ms/DIV
4256 F09
10ms/DIV
4256 F10
Figure 9. LT4256-1 Current Limit Waveforms
Figure 10. LT4256-2 Current Limit Waveforms
When the TIMER pin reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3µA current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
start back up. This is accomplished by cycling UV to
ground and then back high (this command can only be
accepted after TIMER discharges back below the 0.65V
typical threshold, to prevent overheating transistor Q1).
TIMER must never be pulled high by a low impedance
because whenever TIMER rises above the upper threshold
(typically 4.65V) the pin characteristics change from a
high impedance current source to a low impedance.
Whenever GATE is commanded off by any fault condition,
it is discharged rapidly, turning off the external MOSFET.
The waveform in Figure 9 shows how the output latches off
following a current fault (LT4256-1). The drop across the
sense resistor is held at 55mV as the timer ramps up. Once
TIMER reaches its shutdown threshold (4.65V typically),
the circuit latches off.
The LT4256-1 latches off after a current limit fault. After
the LT4256-1 latches off, the part may be commanded to
Automatic Restart
The LT4256-2 will automatically restart after an overcurrent
fault. These waveforms are shown in Figure 10.
The LT4256-2 functionality is as follows: When an
overcurrent condition occurs, the GATE pin is servoed to
maintain a constant voltage across the sense resistor, and
the capacitor C2 at the TIMER pin will begin to charge.
When the voltage at the TIMER pin reaches 4.65V (typ),
the GATE pin is pulled low. When the voltage at the TIMER
pin ramps back down to 0.65V (typ), the LT4256-2 turns
on again. If the short-circuit condition at the output still
exists, the cycle will repeat itself indefinitely. The duty
cycle under short-circuit conditions is 3% which prevents
Q1 from overheating.
425612fa
11
LT4256-1/LT4256-2
U
U
W
U
APPLICATIO S I FOR ATIO
(SHORT PIN)
D2
SMAT70A
8
R1
64.9k
VN2222
C3
Q2
0.01µF
SENSE
GATE
UV
5
C2
33nF
TIMER
CL
R8
36.5k
R7
100Ω
C1
10nF
FB
GND
R6
10Ω
6
LT4256-1/
LT4256-2
R2
8.06k
VOUT
48V
4A
D1
CMPZ5241B
11V
7
VCC
1
OFF SIGNAL
FROM MPU
Q1
IRF530
R5
0.010Ω
VIN
48V
PWRGD
GND
4
2
R9
4.02k
R4
51k
3
4256 F07
UV = 36V
PWRGD = 40V
Figure 11. How to Use a Logic Signal to Control LT4256 Turn-On/-Off
R5
100mΩ
VIN
D2
SMAT70A
(SHORT PIN)
8
VCC
R1
64.9k
1
C3
0.1µF
Q1
IRF530
R2
8.06k
7
SENSE
GATE
UV
VOUT
D1
CMPZ5241B
11V
6
CL
R6
10Ω
VLOGIC
R10
27k
R7
100Ω
LT4256-1/
LT4256-2
FB
2
C1
10nF
R8
36.5k
PWRGD
R9
4.02k
5
GND
C2
33nF
TIMER
PWRGD
GND
4
R4
27k
3
UV = 36V
PWRGD = 40V
Q2
2N3904
4256 F11
Figure 12. Active Low Enable PWRGD Application
Power Good Detection
The LT4256-1/LT4256-2 includes a comparator for monitoring the output voltage. The output voltage is sensed
through the FB pin via an external resistor string. The
comparator’s output (PWRGD) is an open collector capable of operating from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by transistor Q2 and R10.
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
⎛V
⎞
R8 = ⎜ THPWRGD – 1⎟ • R9, high to low
⎝ 3.99 V
⎠
20kΩ ≤ R8 + R9 ≤ 200kΩ
⎛ R8 ⎞
VTHPWRGD = 4.45V⎜ 1+ ⎟ , low to high
⎝ R9 ⎠
(7)
(8a)
(8b)
425612fa
12
LT4256-1/LT4256-2
U
U
W
U
APPLICATIO S I FOR ATIO
Supply Transient Protection
The LT4256-1/LT4256-2 is 100% tested and guaranteed
to be safe from damage with supply voltages up to 80V.
However, voltage transients above 100V may cause permanent damage. During a short-circuit condition, the
large change in currents flowing through the power supply
traces can cause inductive voltage transients which could
exceed 100V. To minimize the voltage transients, the
power trace parasitic inductance should be minimized by
using wider traces or heavier trace plating and a 0.1µF
bypass capacitor should be placed between VCC and GND.
A surge suppressor, as shown in the application diagrams,
(Transzorb) at the input can also prevent damage from
voltage transients.
GATE Pin
A curve of gate drive vs VCC is shown in Figure 13. GATE
is clamped to a maximum voltage of 12.8V above VCC. This
clamp is designed to sink the internal charge pump current. An external Zener diode must be used as shown in all
applications. At a minimum input supply voltage of 12V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a standard threshold MOSFET can be
used. In applications from 12V to 15V range, a logic level
MOSFET must be used.
In some applications it may be possible for the VOUT pin to
ring below ground (due to the parasitic trace inductance).
12
11
Higher current applications, especially where the output
load is physically far away from the LT4256-1/LT4256-2
will be more susceptible to these transients. This is normal
and the LT4256-1/LT4256-2 have been designed to allow
for some ringing below ground. However, if the application is such that VOUT can ring more than 10V below
ground, damage may occur to the LT4256-1 and an
external diode from ground (anode) to VOUT (cathode)
must be added to the circuit as shown in Figure 14 (it is
critical that the reverse breakdown voltage of the diode be
higher than the highest expected VCC voltage). A capacitor
placed from ground to VOUT directly at the LT4256-1/
LT4256-2 can help reduce the amount of ringing on VOUT
but it may not be enough for some applications.
During a fault condition, the LT4256-1/LT4256-2 pulls
down on GATE with a switch capable of sinking about
60mA. Once GATE drops below the output voltage by a
diode forward voltage, the external Zener will forward bias
and VOUT will also be discharged to GND. In addition to the
GATE capacitance, the output capacitance will be discharged through the LT4256-1/LT4256-2.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
LT4256-1/LT4256-2 becomes active and pulls down on
GATE). This is due to the drain to gate capacitance forcing
current into R7 and C1 when the drain voltage steps up
from ground to VIN with an extremely fast rise time. To
alleviate this situation, a diode, D3, should be put
across R7 with the cathode connected to C1 as shown in
Figure 15.
∆VGATE (V)
10
9
8
7
6
5
10
20
30
40
50
VCC (V)
60
70
80
4256 F13
Figure 13. ∆VGATE vs VCC
425612fa
13
LT4256-1/LT4256-2
U
U
W
U
APPLICATIO S I FOR ATIO
Q1
IRF530
R5
0.033Ω
VIN
D2
SMAT70A
8
1
C3
0.1µF
7
VCC
R1
64.9k
(SHORT PIN)
SENSE
GATE
UV
R6
10Ω
6
R8
36.5k
D3
MRA4003T3
R7
100Ω
LT4256-1/
LT4256-2
R2
8.06k
VOUT
CL
100µF
D1
CMPZ5241B
11V
FB
C1
10nF
2
R9
4.02k
5
C2
33nF
GND
TIMER
PWRGD
GND
4
R4
27k
3
4256 F14
UV = 36V
PWRGD = 40V
Figure 14. Negative Output Voltage Protection Diode Application
Notes on Using the LT4256 in LT1641 Applications
Even though the LT4256 and LT1641 have the same
pinout, several changes were made to improve overall
system accuracy and increase noise immunity. These
changes are spelled out in Table 1 and must be accounted
for if using the LT4256 in an LT1641 application.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. The minimum trace width for
1oz copper foil is 0.02" per amp to make sure the trace
stays at a reasonable temperature. 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/❏. Small resistances can
cause large errors in high current applications. Noise
immunity will be improved significantly by locating resistor dividers close to the pins with short VCC and GND
traces. A 0.1µF decoupling capacitor from UV to GND is
also required.
Table 1. Differences Between LT1641 and LT4256
SPECIFICATION
LT1641
LT4256
COMMENTS
UV Threshold
1.313V
4V
Higher 1% Reference for Better Noise Immunity and System Accuracy
FB Threshold
1.233V
3.99V
Higher 1% Reference for Better Noise Immunity and System Accuracy
TIMER Current
±70%
±40%
More Accurate TIMEOUT
TIMER Shutdown V
1.233V
4.65V
Higher Trip Voltage for Better Noise Immunity
GATE IPU
10µA
30µA
Higher Current to Accommodate Higher Leakage MOSFETs or Parallel Devices
GATE Resistor
1kΩ
100Ω
Different Compensation for Current Limit Loop
Foldback ILIM
12mV
14mV
Slightly Different Current Limit Trip Point
ILIM Threshold
47mV
55mV
Slightly Different Current Limit Trip Point
Fault Latch Reset
Threshold Voltage
1.233V
0.85V
Better Noise Immunity
425612fa
14
LT4256-1/LT4256-2
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
3
4
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.050
(1.270)
BSC
SO8 0303
425612fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT4256-1/LT4256-2
U
U
W
U
APPLICATIO S I FOR ATIO
Q1
IRF530
R5
0.033Ω
VIN
D2
SMAT70A
8
1
C3
0.1µF
7
VCC
R1
64.9k
(SHORT PIN)
SENSE
GATE
UV
6
FB
R6
10Ω
R7
100Ω
LT4256-1/
LT4256-2
R2
8.06k
VOUT
CL
100µF
D1
CMPZ5241B
11V
2
R8
36.5k
D3
1N4148W
C1
10nF
R9
4.02k
5
C2
33nF
GND
TIMER
PWRGD
GND
4
R4
27k
3
4256 TA03
UV = 36V
PWRGD = 40V
Figure 15. High dV/dT MOSFET Turn-On Protection Circuit
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1641-1/LT1641-2
Positive 48V Hot Swap Controller in SO-8
9V to 80V Operation, Active Current Limit, Autoretry/Latchoff
LTC4211
Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker
LTC4251
– 48V Hot Swap Controller in SOT-23
Floating Supply from –15V, Active Current Limiting,
Fast Circuit Breaker
LTC4252-1/LTC4252-2 – 48V Hot Swap Controller in MSOP
Floating Supply from –15V, Active Current Limiting,
Power Good Output
LTC4253
– 48V Hot Swap Controller and Supply Sequencer
Floating Supply from –15V, Active Current Limiting,
Enables Three DC/DC Converters
LT4254
Positive High Voltage Hot Swap Controller
10.8V to 36V, Open-Circuit Detection
425612fa
16
Linear Technology Corporation
LT/LWI/LT 0705 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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