LT6552IS8

LT6552 3.3V Single Supply Video Difference Amplifier U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Differential or Single-Ended Gain Block Wide Supply Range 3V to 12.6V Output Swings Rail-to-Rail Input Common Mode Range Includes Ground 600V/µs Slew Rate –3dB Bandwidth = 75MHz, AV = ±2 CMRR at 10MHz: >60dB Specified on 3.3V, 5V and ±5V Supplies High Output Drive: ±70mA Power Shutdown to 300µA Operating Temperature Range: –40°C to 85°C Available in 8-Lead SO and Tiny 3mm x 3mm x 0.8mm DFN Packages U APPLICATIO S ■ ■ ■ ■ ■ Differential to Single-Ended Conversion Video Line Driver Automotive Displays RGB Amplifiers Coaxial Cable Drivers Low Voltage High Speed Signal Processing On a single 3.3V supply, the input voltage range extends from ground to 1.3V and the output swings from ground to 2.9V while driving a 150Ω load. The LT6552 features 75MHz – 3dB bandwidth, 600V/µs slew rate, and ±70mA output current making it ideal for driving cables directly. The LT6552 maintains its performance for supplies from 3V to 12.6V and is fully specified at 3.3V, 5V and ±5V supplies. The shutdown feature reduces power dissipation to less than 1mW and allows multiple amplifiers to drive the same cable. The LT6552 is available in the 8-lead SO package as well as a tiny, dual fine pitch leadless package (DFN). The device is specified over the commercial and industrial temperature ranges. , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ The LT®6552 is a video difference amplifier optimized for low voltage single supply operation. This versatile amplifier features uncommitted high input impedance (+) and (–) inputs and can be used in differential or single-ended configurations. A second set of inputs gives gain adjustment and DC control to the differential amplifier. TYPICAL APPLICATIO Input Referred CMRR vs Frequency Cable Sense Amplifier for Loop Through Connections with DC Adjust VIN 5V 3 2 CABLE VDC 7 + – LT6552 1 REF 8 FB 6 4 75Ω VOUT 75Ω RF 500Ω RG 500Ω 6552 TA01a CF 8pF COMMON MODE REJECTION RATIO (dB) 100 90 VS = 5V, 0V VCM = 0V DC 80 70 60 50 40 30 20 10 100k 1 10 FREQUENCY (MHz) 100 6552 TA01b 6552f 1 LT6552 U W W W ABSOLUTE AXI U RATI GS (Note 1) Supply Voltage (V + to V –) .................................... 12.6V Input Current (Note 2) ........................................ ±10mA Input Voltage Range ......................................... V – to V + Differential Input Voltage +Input (Pin 3) to –Input (Pin 2) ................................ ±VS Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) ...–40°C to 85°C Specified Temperature Range (Note 5) ....–40°C to 85°C Maximum Junction Temperature .......................... 150°C (DD Package) ................................................... 125°C Storage Temperature Range ..................–65°C to 150°C (DD Package) ....................................–65°C to 125°C Lead Temperature (Soldering, 10 sec) ........................................... 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW REF 1 8 FB –IN 2 7 V+ +IN 3 6 OUT V– 4 5 SHDN DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 160°C/W UNDERSIDE METAL CONNECTED TO V– (PCB CONNECTION OPTIONAL) LT6552CDD LT6552IDD ORDER PART NUMBER TOP VIEW REF 1 8 FB –IN 2 7 V+ +IN 3 6 OUT V– 4 5 SHDN DD PART MARKING* LADR LT6552CS8 LT6552IS8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 100°C/W 6552 6552I *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. 3.3V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3.3V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage Both Inputs (Note 7) MIN TYP MAX 5 20 25 ● UNITS mV mV ∆VOS/∆T Input VOS Drift ● 40 IB Input Bias Current Any Input ● 20 50 µV/°C µA IOS Input Offset Current Either Input Pair ● 1 5 µA 6552f 2 LT6552 3.3V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3.3V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS en Input Noise Voltage Density f = 10kHz in Input Noise Current Density RIN Input Resistance CMRR Common Mode Rejection Ratio VCM = 0V to 1.3V PSRR Power Supply Rejection MIN UNITS nV/√Hz f = 10kHz 0.7 pA/√Hz Common Mode, VCM = 0V to 1.3V 300 kΩ 83 dB VS = 3V to 12V Minimum Supply (Note 8) ● 0 ● 48 ● 3 Gain Error VO = 0.5V to 2V, RL = 1k RL = 150Ω ● ● VOH Swing High (VDIFF = 0.4V), VREF (Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω ● ● (VDIFF = –0.1V), VREF(Pin 1) = 0V, AV = 10 RL = 1k ISINK = 5mA ISINK = 10mA 58 ● GE Swing Low MAX 55 Input Range VOL TYP 1.3 54 V 1 1 3.1 2.5 2 3 3 3.2 2.9 2.5 8 65 40 ● ● ● V dB % % V V V 50 120 200 mV mV mV SR Slew Rate VOUT = 0.5V to 2.5V Measure from 1V to 2V, RL = 150Ω, AV = 2 350 V/µs FPBW Full-Power Bandwidth (Note 9) VO = 2VP-P 55 MHz BW Small-Signal –3dB Bandwidth AV = 2, RL = 150Ω 65 MHz tr, tf Rise Time, Fall Time (Note 10) AV =50, VO = 0.5V to 2.5V, 20% to 80%, RL = 150Ω 125 tS Settling Time to 3% Settling Time to 1% AV = 2, ∆VOUT = 2V, Positive Step RL = 150Ω 20 30 ISC ns ns ns Differential Gain AV = 2, RL = 150Ω, Output Black Level = 0.6V 0.4 % Differential Phase AV = 2, RL = 150Ω, Output Black Level = 0.6V 0.15 Deg Short-Circuit Current VOUT = 0V, VDIFF = 1V 50 mA mA ● IS 175 35 25 Supply Current 12.5 13.5 15 mA mA 300 750 µA 0.5 V ● Supply Current, Shutdown VSHDN = 0.5V ● VL Shutdown Pin Input Low Voltage ● VH Shutdown Pin Input High Voltage ● Shutdown Pin Current VSHDN = 0.5V VSHDN = 3V tON Turn On-Time VSHDN from 0.5V to 3V tOFF Turn Off-Time VSHDN from 3V to 0.5V Shutdown Output Leakage Current VSHDN = 0.5V, 0V ≤ VOUT ≤ V+ ● ● 3 V 40 3 250 ● 150 10 µA µA ns 450 ns 0.25 µA 6552f 3 LT6552 5V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V; Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage Both Inputs (Note 7) MIN TYP MAX 5 20 25 ● UNITS mV mV ∆VOS/∆T Input VOS Drift IB Input Bias Current IOS Input Offset Current en Input Noise Voltage Density f = 10kHz 55 nV/√Hz in Input Noise Current Density f = 10kHz 0.7 pA/√Hz RIN Input Resistance Common Mode, VCM = 0V to 3V 300 kΩ CMRR Common Mode Rejection Ratio VCM = 0V to 3V 40 Any Input ● 20 50 uA Either Input Pair ● 1 5 uA Input Range PSRR Power Supply Rejection VS = 3V to 12V Minimum Supply (Note 8) ● 58 ● 0 ● 48 ● 3 GE Gain Error VO = 0.5V to 3.5V, RL = 1k RL = 150Ω ● ● VOH Swing High (VDIFF = 0.6V), VREF(Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω, 0°C ≤ TA ≤ 70°C (Only) ● ● ● (VDIFF = –0.1V), VREF (Pin 1) = 0V, AV = 10 RL = 1k ISINK = 5mA ISINK = 10mA ● ● ● VOL SR FPBW Swing Low Slew Rate Full-Power Bandwidth (Note 9) µV/°C ● 83 54 V dB V 1 1 4.8 3.6 2.75 dB 3 3 3 4.875 4.3 3.4 8 65 110 % % V V V 50 120 200 mV mV mV VOUT = 0.5V to 3.5V Measure from 1V to 3V, RL = 150Ω, AV = 2 450 V/µs VO = 2VP-P 70 MHz BW Small-Signal –3dB Bandwidth AV = 2, RL = 150Ω 70 tr, tf Rise Time, Fall Time 5V, 0V; AV = 50, VO = 0.5V to 3.5V, 20% to 80%, RL = 1k 125 tS Settling Time to 3% Settling Time to 1% AV = 2, ∆VOUT = 2V, Positive Step RL = 150Ω 20 30 ns ns Differential Gain AV = 2, RL = 150Ω, Output Black Level = 1V 0.25 % Differential Phase AV = 2, RL = 150Ω, Output Black Level = 1V 0.04 Deg Short-Circuit Current VOUT = 0V, VDIFF = 1V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C 70 mA mA mA ISC IS ● ● 50 45 35 Supply Current VSHDN = 0.5V ● VL Shutdown Pin Input Low Voltage ● VH Shutdown Pin Input High Voltage ● Shutdown Pin Current VSHDN = 0.5V VSHDN = 4.7V ● ● ns 13.5 14.5 16 mA mA 400 900 µA ● Supply Current Shutdown MHz 175 0.5 4.7 V V 60 4 200 10 µA µA 6552f 4 LT6552 5V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, 0V. Figure 1 shows the DC test circuit, VREF = VCM = 1V, VDIFF = 0V, VSHDN = V+, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS tON Turn-On Time VSHDN from 0.5V to 4.7V 250 ns tOFF Turn-Off Time VSHDN from 4.7V to 0.5V 450 ns 0.25 µA Shutdown Output Leakage Current VSHDN = 0.5V, 0V ≤ VOUT MIN ≤ V+ ● TYP MAX UNITS ±5V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V. Figure 2 shows the DC test circuit, VREF = VCM = 0V, VDIFF = 0V, VSHDN = V +, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage Both Inputs (Note 7) MIN TYP MAX 10 25 30 ● UNITS mV mV ∆VOS/∆T Input VOS Drift µV/°C IB Input Bias Current IOS Input Offset Current en Input Noise Voltage Density f = 10kHz 55 nV/√Hz in Input Noise Current Density f = 10kHz 0.7 pA/√Hz RIN Input Resistance Common Mode, VCM = –5V to 3V 300 kΩ CMRR Common Mode Rejection Ratio VCM = –5V to 3V 75 dB PSRR Power Supply Rejection VS = ±2V to ±6V, VCM = 0V GE Gain Error VO = –3V to 3V, RL = 1k RL = 150Ω ● ● Output Voltage Swing (VDIFF = ± 0.6V), VREF (Pin 1) = 0V, AV = 10 RL = 1k RL = 150Ω RL = 75Ω, 0°C ≤ TA ≤ 70°C (Only) ● ● ● ● 50 Any Input ● 25 50 µA Either Input Pair ● 1 5 µA Input Range ● 58 ● –5 ● 48 1 1 V dB 3 3 % % ±4.8 ±3.6 ±2.75 ±4.875 ±4.3 ±3.4 400 600 V/µs V V V SR Slew Rate FPBW Full-Power Bandwidth VO = 6VP-P (Note 9) 30 MHz BW Small-Signal –3dB Bandwidth AV = 2, RL = 150Ω 75 MHz tr, tf Rise Time, Fall Time AV = 50, VO = –3V to 3V, 20% to 80% 125 tS Settling Time to 3% Settling Time to 1% AV = 2, ∆VOUT = 6V, Positive Step RL = 150Ω 25 35 ns ns Differential Gain AV = 2, RL = 150Ω, Output Black Level = 0V 0.2 % Differential Phase AV = 2, RL = 150Ω, Output Black Level = 0V 0.15 Deg Short-Circuit Current VOUT = 0V, VDIFF = ±1V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C 70 ● ● mA mA mA VSHDN = –4.5V ● ISC Supply Current Shutdown IS VCM = 0V, VDIFF = –1.5V to +1.5V, VO = –5V to 5V Measure from –2V to 2V, RL = 150Ω 3 54 50 45 35 Supply Current ● VL Shutdown Pin Input Low Voltage ● VH Shutdown Pin Input High Voltage ● 4.7 175 ns 650 1400 µA 14 16.5 18.5 mA mA –4.5 V V 6552f 5 LT6552 ±5V ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V. Figure 2 shows the DC test circuit, VREF = VCM = 0V, VDIFF = 0V, VSHDN = V +, unless otherwise noted. RL = RF + RG = 1k. (Note 6) SYMBOL PARAMETER CONDITIONS Shutdown Pin Current VSHDN = –4.5V VSHDN = 4.7V tON Turn-On Time VSHDN from – 4.5V to 4.7V tOFF Turn-Off Time VSHDN from 4.7V to –4.5V Shutdown Output Leakage Current VSHDN = –4.5V, V – ≤ VOUT ≤ V+ Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected from ESD with diodes to the supplies. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: The LT6552C/LT6552I are guaranteed functional over the temperature range of –40°C to 85°C. Note 5: The LT6552C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified performance from –40°C to 85°C, but is not tested or QA sampled at these temperatures. The LT6552I is guaranteed to meet specified performance from – 40°C to 85°C. MIN –+ FB –IN V+ V– VREF + – + – VCM UNITS 85 3 250 10 µA µA 200 ● ns 400 ns 0.25 µA Note 6: When RL = 1k is specified, the load resistor is RF + RG, but when RL = 150Ω or RL = 75Ω is specified, then an additional resistor of that value is added to the output. Note 7: VOS measured at the output (Pin 6) is the contribution from both input pairs and is input referred. Note 8: Minimum supply is guaranteed by the PSRR test. Note 9: Full power bandwidth is calculated from the slew rate. FPBW = SR/2πVp Note 10: VS = 3.3V, tr and tf limits are guaranteed by correlation to VS = 5V and ±5V tests. RG 100Ω 0.1% REF +IN MAX ● ● RG 100Ω 0.1% VDIFF TYP 1µF OUT RF 900Ω 0.1% – + SHDN VSHDN + – + – V+ RL + – VDIFF VCM – + REF FB –IN V+ +IN V– V– 1µF 1µF OUT SHDN VSHDN + – + – 6552 F01 Figure 1. 3.3V, 5V DC Test Circuit RF 900Ω 0.1% V+ RL 6552 F02 Figure 2. ±5V DC Test Circuit 6552f 6 LT6552 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage –10 18 14 INPUT BIAS CURRENT (µA) SUPPLY CURRENT (mA) –12 TA = 125°C TA = –55°C 12 TA = 25°C 10 8 6 4 –4 VS = 5V, 0V VCM = 1V –14 –16 –18 –20 –22 2 2 0 6 8 10 4 TOTAL SUPPLY VOLTAGE (V) 12 50 25 75 0 TEMPERATURE (°C) 100 TA = 125°C –12 TA = 25°C –14 –16 TA = –55°C –18 –20 Output Saturation Voltage vs Load Current (Output High) Output Saturation Voltage vs Load Current (Output Low) 1 OUTPUT LOW SATURATION VOLTAGE (V) VS = 5V, 0V TA = 125°C 100m TA = 25°C TA = –55°C 10m 0.01 0.1 1 10 SOURCING LOAD CURRENT (mA) 100m TA = 125°C TA = –55°C TA = 25°C 0.1 1 10 SINKING LOAD CURRENT (mA) TA = 25°C –40 TA = –55°C –50 –60 0 1 2 3 4 SHUTDOWN PIN VOLTAGE (V) 8 6 4 5 6552 G07 3.0 3.5 4.5 4.0 SHUTDOWN PIN VOLTAGE (V) 70 Output Short-Circuit Current vs Temperature 80 VS = 5V, 0V 65 60 55 VS = 3.3V, 0V 50 45 40 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 5.0 6552 G06 OUTPUT SHORT-CIRCUIIT CURRENT (mA) OUTPUT SHORT-CIRCUIIT CURRENT (mA) –30 TA = –55°C 10 0 2.5 100 75 TA = 125°C –20 TA = 25°C 12 Output Short-Circuit Current vs Temperature –10 TA = 125°C 6552 G05 Shutdown Pin Current vs Shutdown Pin Voltage VS = 5V, 0V VCM = 1V VS = 5V, 0V VCM = 1V 2 1m 0.01 100 16 VS = 5V, 0V 14 10m 5 Supply Current vs Shutdown Pin Voltage 6552 G04 0 1 3 4 2 COMMON MODE VOLTAGE (V) 0 6552 G03 SUPPLY CURRENT (mA) 1 –24 125 6552 G02 6552 G01 OUTPUT HIGH SATURATION VOLTAGE (V) –8 –10 –22 –24 –50 –25 0 SHUTDOWN PIN CURRENT (µA) VS = 5V, 0V –6 INPUT BIAS CURRENT (µA) 20 16 Input Bias Current vs Common Mode Voltage Input Bias Current vs Temperature 125 6552 G08 VS = ±5V SOURCING CURRENT 75 SINKING CURRENT 70 65 60 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 6552 G09 6552f 7 LT6552 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Noise Voltage Density vs Frequency Open-Loop Gain 225 400 300 200 100 RL = 1k RL = 150Ω –200 –300 –400 150 125 100 75 50 25 100 –500 –5 –4 –3 –2 –1 0 1 2 3 OUTPUT VOLTAGE (V) 4 5 1k 10k FREQUENCY (Hz) Closed-Loop Voltage Gain vs Frequency 6.2 CLOSED-LOOP VOLTAGE GAIN (dB) 7 6 3.3V 5 VIN 4 VDC 3 2 3 2 7 + – LT6552 1 REF 8 FB 4 6 RF 500Ω VOUT RL 150Ω RG 500Ω 1 0 100k 1M 10M FREQUENCY (Hz) 6.1 6.0 5.9 5.8 VDC 3 2 70 60 50 7 + – LT6552 1 REF 8 FB 4 6 RF 500Ω VOUT RL 150Ω RG 500Ω 5.7 10k 100M 100 VS = 3.3V, OV VCM = 1V 100k CL = 5pF RL = 1k VS = ±5V 30 40 10 –10 VS = ±5V 100M 30 100 20 0 –20 GAIN –20 1M 10M FREQUENCY (Hz) VS = 3.3V, OV 80 VCM = 1V 60 20 0 –30 100k 1M 10M FREQUENCY (Hz) 130 100M 20 125 6552 G16 40 PHASE MARGIN 0 2 AV = 2 RL = 150Ω 80 GAIN BANDWIDTH PRODUCT 110 –60 500M –3dB Bandwidth vs Temperature 85 CL = 5pF RL = 1k TA = 25°C VCM =1V 120 –40 6552 G15 30 8 6 4 10 12 TOTAL SUPPLY VOLTAGE (V) 20 14 6552 G17 PHASE MARGIN (DEG) VS = ±5V PHASE MARGIN (DEG) 40 PHASE MARGIN 50 25 75 0 TEMPERATURE (°C) VS = ±5V VS = 3.3V, OV VCM = 1V 80 –50 –25 PHASE 40 Gain Bandwidth Product and Phase Margin vs Supply Voltage VS = 3.3V, OV VCM = 1V 100k 140 CL = 5pF 120 RL = 1k TA = 25°C 100 6552 G14 GAIN BANDWIDTH PRODUCT (MHz) GAIN BANDWIDTH PRODUCT (MHz) 120 1k 10k FREQUENCY (Hz) Open-Loop Gain and Phase vs Frequency 3.3V VIN Gain Bandwidth Product and Phase Margin vs Temperature GAIN BANDWIDTH PRODUCT 0 100 AV = 2 VOUT = 1.5V DC VS = 3.3V, 0V 6552 G13 140 1 6552 G12 CF 8pF CF 8pF 0.1M 2 PHASE (DEG) CLOSED-LOOP VOLTAGE GAIN (dB) 8 3 100k Gain Flatness vs Frequency AV = 2 VOUT = 1.5V DC VS = 3.3V, 0V 9 4 6552 G11 6552 G10 10 VS = 5V, 0V VCM = 1V –3dB BANDWIDTH (MHz) –100 175 OPEN-LOOP GAIN 0 5 VS = 5V, 0V 200 VCM = 1V INPUT NOISE CURRENT DENSITY (pA/√Hz) VS = ±5V INPUT NOISE VOLTAGE DENSITY (nV/√Hz) CHANGE IN INPUT OFFSET VOLTAGE (µV) 500 Input Noise Current Density vs Frequency VS = ±5V 75 70 65 60 55 –50 –25 VS = 3.3V, OV VOUT = 1.5V 50 25 75 0 TEMPERATURE (°C) 100 125 6552 G18 6552f 8 LT6552 U W TYPICAL PERFOR A CE CHARACTERISTICS RL = 150Ω TA = 25°C VOUT = –3V TO 3V VS = ±5V Output Impedance vs Frequency Slew Rate vs Temperature 550 VS = ±5V AV = 2 RL = 150Ω AV = 2 1 0.1 VS = 5V, 0V VOUT = 0.5V T0 3.5V 400 10M 1M FALLING 300 VS = 3.3V, 0V VOUT = 0.5V T0 2.5V RISING 100 VS = 3.3V, 0V 50 40 30 20 1M 10M FREQUENCY (Hz) 60 NEGATIVE SUPPLY 40 30 POSITIVE SUPPLY 20 30 25 RS = 20Ω, RL = ∞ 20 RS = RL = 50Ω 1M 10M FREQUENCY (Hz) 100M 100 CAPACITIVE LOAD (pF) 10 6552 G23 –30 –40 RL = 150Ω, 2ND 6552 G24 VS = ±5V AV = 2 VO = 2VP-P –50 –60 –70 –80 RL = 1k, 2ND RL = 150Ω, 2ND RL = 150Ω, 3RD RL = 1k, 2ND –90 RL = 1k, 3RD 100k 1M FREQUENCY (Hz) 1000 2nd and 3rd Harmonic Distortion vs Frequency –50 –80 10k RS = 10Ω, RL = ∞ 35 0 100k RL = 150Ω, 3RD –70 VS = 5V, 0V 50 A = 2 V 45 RF = RG = 500Ω CFB = 8pF 40 5 0 10k 100M 10 55 10 VS = 3.3V, 0V AV = 2 VO = 0.5V TO 2.5V –60 8 15 10 2nd and 3rd Harmonic Distortion vs Frequency –40 6 GAIN (AV) Series Output Resistor vs Capacitive Load 50 6552 G22 –30 4 6552 G21 VS = ±5V TA = 25°C DISTORTION (dB) 10 100k 2 125 Power Supply Rejection Ratio vs Frequency POWER SUPPLY REJECTION RATIO (dB) VS = ±5V 60 DISTORTION (dB) COMMON MODE REJECTION RATIO (dB) 70 300 6552 G20 Common Mode Rejection Ratio vs Frequency 80 RISING 400 200 6552 G19 VCM = 0V DC 500 0 50 25 75 0 TEMPERATURE (°C) FREQUENCY (Hz) 90 FALLING 600 100 200 –50 –25 100M RISING 350 250 0.01 100k 700 450 SLEW RATE (V/µs) AV = 10 RL = 150Ω TA = 25°C VOUT = –3V TO 3V VS = ±5V 800 FALLING 10 SLEW RATE (V/µs) OUTPUT IMPEDANCE (Ω) 500 Slew Rate vs Closed-Loop Gain 900 OVERSHOOT (%) 100 RL = 1k, 3RD 10M 6552 G25 –100 10k 100k 1M FREQUENCY (Hz) 10M 6552 G26 6552f 9 LT6552 U W TYPICAL PERFOR A CE CHARACTERISTICS Large Signal Response, VS = 5V, 0V 0V AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω 50ns/DIV Small Signal Response, VS = 5V, 0V 50mV/DIV 1V/DIV 500mV/DIV Large Signal Response, VS = ±5V 0V 6552 G27 AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω Small Signal Response, VS = 5V, 0V 50ns/DIV 6552 G28 AV = 1 CL = 10pF RL = 150Ω Shutdown Response 50ns/DIV 6552 G29 Output Overdrive Recovery VSHDN 2V/DIV 50mV/DIV 2.5V VIN 1V/DIV 0V 0V 2.5V AV = 2 CF = 5pF CL = 10pF RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 G30 VOUT 1V/DIV VOUT 2V/DIV 0V 0V AV = 2 RL = 150Ω VIN = 1.25V VS = 5V, 0V 200ns/DIV 6552 G31 AV = 2 VS = 5V, 0V 100ns/DIV 6552 G32 6552f 10 LT6552 U U W U APPLICATIO S I FOR ATIO The LT6552 is a video difference amplifier with two pairs of high impedance inputs. The primary purpose of the LT6552 is to convert high frequency differential signals into a single-ended output, while rejecting any common mode noise. In the simplest configuration, one pair of inputs is connected to the incoming differential signal, while the other pair of inputs is used to set amplifier gain and DC level. The device will operate on either single or dual supplies and has an input common mode range which includes the negative supply. The common mode rejection ratio is greater than 60dB at 10MHz. Feedback is applied to Pin 8 and the LT6552’s transient response is optimized for gains of 2 or greater. Figure 3 shows the single supply connection. The amplifier gain is set by a feedback network from the output to Pin 8 (FB). A DC signal applied to Pin 1 (REF) establishes the output quiescent voltage and the differential signal is applied to Pins 2 and 3. Figure 4 shows several other connections using dual supplies. In each case, the amplifier gain is set by a feedback network from the output to Pin 8 (FB). SHDN VINDIFF VDC 5 3 2 V+ 7 + – LT6552 1 REF 8 FB 6 VO 4 RF R + RG VO = (VINDIFF + VDC) F RG RG 6552 F01 Figure 3 SHDN VIN 3 2 5 SHDN V+ + – LT6552 7 1 REF 8 FB RG 6 VO 4 VIN 3 2 5 SHDN V+ + – LT6552 7 1 REF 8 FB VINDIFF 6 VO VIN 4 RG 3 2 5 V+ 7 + – LT6552 1 REF 8 FB V– V– RF RF RF ( R R+ R ( V F G G IN RG VO = – ( R R+ R ( V F G G IN VO = ( R R+ R ( V F G G VO 4 V– VO = + 6 INDIFF – ( RR ( V F G IN 6552 F01 Figure 4 6552f 11 LT6552 U W U U APPLICATIO S I FOR ATIO Amplifier Characteristics The current generated through R1 or R2, divided by the capacitor CM, determines the slew rate. Note that this current, and hence the slew rate, are proportional to the magnitude of the input step. The input step equals the output step divided by the closed-loop gain. The highest slew rates are therefore obtained in the lowest gain configurations. The Typical Performance Characteristic Curve of Slew Rate vs Closed-Loop Gain shows the details. Figure 5 shows a simplified schematic of the LT6552. There are two input stages; the first one consists of transistors Q1 to Q8 for the (+) and (–) inputs while the second input stage consists of transistors Q9 to Q16 for the reference and feedback inputs. This topology provides high slew rates at low supply voltages. The input common mode range extends from ground to typically 1.75V from VCC, and is limited by 2VBE’s plus a saturation voltage of current sources I1-I4. Each input stage drives the degeneration resistors of PNP and NPN current mirrors, Q17 to Q20, that convert the differential signals into a singleended output. The complementary drive generator supplies current to the output transistors that swing from railto-rail. ESD The LT6552 has reverse-biased ESD protection diodes on all inputs and outputs, as shown in Figure 5. If these pins are forced beyond either supply, unlimited current will flow through these diodes. If the current is transient in nature and limited to 100mA or less, no damage to the device will occur. 7 V+ I1 I2 I3 I5 I4 R3 R4 Q21 Q17 Q2 Q3 Q5 R1 Q4 Q6 Q7 Q10 Q11 Q13 R2 Q18 Q15 CM V+ DESD9 Q1 Q8 Q9 Q12 Q14 Q16 COMPLEMENTARY DRIVE GENERATOR 6 OUT DESD10 Q19 Q20 V– Q22 I6 V+ RIN1 V+ DESD1 DESD2 3 +IN V– V+ RIN2 DESD3 RIN3 DESD6 V– 2 –IN 1 REF V– R6 4 V– V+ V+ DESD5 DESD4 R5 V+ RIN4 DESD7 DESD11 5 SHDN BIAS DESD8 V– 8 FB DESD12 V– 6552 FO5 Figure 5. Simplified Schematic 6552f 12 LT6552 U W U U APPLICATIO S I FOR ATIO Layout and Passive Components Operating with Low Closed-Loop Gains With a bandwidth of 75MHz and a slew rate of 600V/µs, the LT6552 requires special attention to board layout and supply bypassing. Use a ground plane, short lead lengths and RF quality low ESR supply bypass capacitors. The positive supply pin should be bypassed with a small capacitor (typically 0.1µF) within 1 inch of the pin. When driving loads greater than 10mA, an additional 4.7µF electrolytic capacitor should be used. When using split supplies, the same is true for the negative supply pin. The parallel combination of the feedback resistor and gain setting resistor on Pin 8 (FB) can combine with the input capacitance to form a pole which can degrade stability. In general, use feedback resistors of 1k or less. The LT6552 has been optimized for closed-loop gains of 2 or greater. For a closed-loop gain of 2 the response peaks about 3dB. Peaking can be reduced by using low value feedback resistors, and can be eliminated by placing a capacitor across the feedback resistor (feedback zero). Figure 6 shows the closed-loop gain of 2 frequency response with various values of the feedback capacitor. This peaking shows up as a time domain overshoot of 40%; with an 8pF feedback capacitor the overshoot is eliminated. Figures 7A and 7B show the Small Signal Response of the LT6552 with and without an 8pF feedback capacitor. 10 CLOSED-LOOP VOLTAGE GAIN (dB) AV = 2 9 RF = RG = 500Ω RL = 150Ω 8 T = 25°C A 7 VOUT = 1.5V DC VS = 3.3V, 0V 6 CF = 0pF CF = 3pF CF = 5pF 5 CF = 8pF 4 CF = 10pF 3 2 1 0 0.1 1 10 FREQUENCY (MHz) 100 6552 F06 50mV/DIV 50mV/DIV Figure 6. Closed-Loop Gain vs Frequency 1.5V AV = 2 RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 F07a Figure 7A. Small Signal Transient Response, VS = 3.3V, 0V 1.5V AV = 2 CF = 8pF RF = RG = 500Ω RL = 150Ω 50ns/DIV 6552 F07b Figure 7B. Small Signal Transient Response, VS = 3.3V, 0V with 8pF Feedback Capacitor 6552f 13 LT6552 U W U U APPLICATIO S I FOR ATIO SHDN Pin The LT6552 includes a shutdown feature that disables the part, reducing quiescent current and making the output high impedance. The part can be shutdown by bringing the SHDN pin within 0.5V of V–. When shutdown the supply current is typically 400µA and the output leakage current is 0.25µA (V– ≤ VOUT ≤ V+). In normal operation the SHDN can be tied to V+ or left floating; if the pin is left unconnected, an internal FET pull-up will keep the LT6552 fully operational. U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 3.00 ±0.10 (4 SIDES) 0.38 ± 0.10 8 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.200 REF 0.75 ±0.05 0.00 – 0.05 4 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 6552f 14 LT6552 U PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN 7 6 5 .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 2 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC SO8 0303 6552f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6552 U TYPICAL APPLICATIO YPBPR to RGB Video Converter +3V +3V 499Ω 499Ω 499Ω 499Ω 5.6pF 8.2pF 8 8 1 2 3 FB 7 REF – + 1 LT6552 6 2 3 5 4 FB 7 REF – + LT6552 6 75Ω G 5 4 75Ω SD SD –3V –3V +3V 499Ω 909Ω Y 2.2pF 8 1 PR 21.5Ω 53.6Ω 2 21.5Ω 3 FB 7 REF – + 11.3Ω LT6552 6 75Ω R 5 4 75Ω SD –3V +3V 42.2Ω 499Ω 1.3k 1pF 8 1 PB 2 49.9Ω 25.5Ω 3 FB 7 REF – + LT6552 6 75Ω B 5 4 75Ω SD –3V R = Y + 1.4 • PR G = Y – 0.34 • PB – 0.71 • PR B = Y + 1.8 • PB BW (± 0.5dB) > 25MHz BW (–3dB) > 36MHz IS ≈ 70mA 6552 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1193 AV = 2 Video Difference Amp 80MHz BW, 500V/µs Slew Rate, Shutdown LT1675 RGB Multiplexer with Current Feedback Amplifiers –3dB Bandwidth = 250MHz, 100MHz Pixel Switching LT6205/LT6206/LT6207 Single/Dual/Quad Single Supply 3V, 100MHz Video Op Amps 450V/µs Slew Rate, Rail-to-Rail Output, Input Common Modes to Ground LT6550/LT6551 3.3V Triple and Quad Video Amplifiers Internal Gain of 2, 110MHz –3dB Bandwidth, Input Common Modes to Ground 6552f 16 Linear Technology Corporation LT/TP 0304 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2003