LT6556
750MHz Gain of 1 Triple
2:1Video Multiplexer
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DESCRIPTIO
FEATURES
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750MHz –3dB Small Signal Bandwidth
450MHz –3dB 2VP-P Large-Signal Bandwidth
120MHz ±0.1dB Bandwidth
High Slew Rate: 2100V/µs
Fixed Gain of 1; No External Resistors Required
72dB Channel Separation at 10MHz
52dB Channel Separation at 100MHz
–84dBc 2nd Harmonic Distortion at 10MHz, 2VP-P
–87dBc 3rd Harmonic Distortion at 10MHz, 2VP-P
Low Supply Current: 9.5mA per Amplifier
6.5ns 0.1% Settling Time for 2V Step
ISS ≤ 330µA per Amplifier When Disabled
Differential Gain of 0.033%, Differential Phase of 0.022°
Wide Supply Range: ±2.25V (4.5V) to ±6V (12V)
Available in 24-Lead SSOP and 24-Lead QFN Packages
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APPLICATIO S
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While the performance of the LT6556 is optimized for dual
supply operation, it can also be operated with a single supply as low as 4.5V. Using dual 5V supplies, each amplifier
draws only 9.5mA. When disabled, the amplifiers draw
less than 330µA and the outputs become high impedance.
For applications requiring a fixed gain of 2, refer to the
LT6555 datasheet.
The LT6556 is available in 24-lead SSOP and ultra-compact
24-lead QFN packages.
RGB Buffers
UXGA Video Multiplexing
LCD Projectors
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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The LT®6556 is a high speed triple 2:1 video multiplexer
with an internally fixed gain of 1. The individual buffers
are optimized for performance with a 1k load and feature a
2VP-P –3dB bandwidth of 450MHz, making them ideal for
driving very high resolution video signals. Separate power
supply pins for each amplifier boost channel separation
to 72dB, allowing the LT6556 to excel in many high speed
applications.
TYPICAL APPLICATIO
RGB Multiplexer and Line Driver
Large-Signal Transient Response
V+
RINA
GINA
BINA
LT6556
1.5
75Ω
×1
ROUT
VIN = 2VP-P
VS = ±5V
RL = 1k
TA = 25°C
1.0
1k
75Ω
75Ω AGND
GOUT
×1
1k
RINB
GINB
BINB
OUTPUT (V)
0.5
0
–0.5
–1.0
75Ω
–1.5
×1
75Ω
BOUT
SELECT A/B
1k
0
2
4
6
8 10 12 14 16 18 20
TIME (ns)
6556 TA02
VREF
75Ω
ENABLE
DGND
–
V
6556 TA01
6556f
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LT6556
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ABSOLUTE
AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–)
.............................12.6V
Input Current (Note 2) .........................................±10mA
Output Current (Continuous) ..............................±70mA
⎯E⎯N to DGND Voltage (Note 2) ..................................5.5V
SEL to DGND Voltage (Note 2) ....................................8V
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4) ... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Junction Temperature
SSOP ................................................................ 150°C
QFN................................................................... 125°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
QFN.................................................... –65°C to 125°C
Soldering Temperature (10 sec) ............................ 300°C
21 V+
IN3A
5
AGND1
6
IN1B
8
IN2B
9
IN3A 2
17 OUT1
16 V–
15 V–
IN3B 11
14 V+
13 V+
12
15 OUT2
14 V+
AGND2 6
16 OUT3
G = +1
25
IN1B 5
V+
AGND3 10
V–
18 V+
V– 4
18 OUT2
17
VREF 1
AGND1 3
19 V–
7
AGND2
20 OUT1
G = +1
EN
4
24 23 22 21 20 19
13 OUT3
7
8
9 10 11 12
V–
VREF
V+
22 SEL A/B
V+
3
V+
IN2A
DGND
23 EN
IN3B
24
2
IN2B
1
AGND3
IN1A
DGND
G = +1
IN2A
V+
IN1A
TOP VIEW
TOP VIEW
SEL A/B
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PACKAGE/ORDER I FOR ATIO
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 25) IS V –
MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 90°C/W
ORDER PART NUMBER
GN PART MARKING
ORDER PART NUMBER
UF PART MARKING*
LT6556CGN
LT6556IGN
LT6556CGN
LT6556IGN
LT6556CUF
LT6556IUF
6556
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, V⎯E⎯N = 0.4V, VAGND, VDGND, VVREF = 0V.
SYMBOL
PARAMETER
VOS
Offset Voltage
IIN
Input Current
RIN
Input Resistance
CIN
PSRR
Input Capacitance
Power Supply Rejection Ratio
CONDITIONS
VIN = 0V, VOS = VOUT
MIN
TYP
MAX
UNITS
18
±67
±75
mV
mV
–12
±45
µA
●
●
VIN = ±1V
●
f = 100kHz
●
VS = ±2.25V to ±6V (Note 6)
●
100
500
1
pF
51
62
dB
kΩ
6556f
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LT6556
ELECTRICAL CHARACTERISTICS
The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 1k, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
IPSRR
Input Current Power Supply Rejection
VS = ±2.25V to ±6V (Note 6)
●
●
AV ERR
Gain Error
VOUT = VREF = ±2V, Nominal Gain 1V/V
AV MATCH
Gain Matching
Any One Channel to Another
VOUT
Output Voltage Swing
(Note 7)
IS
Supply Current, Per Amplifier
RL = ∞
Supply Current, Disabled, Per Amplifier
●
1
±3
µA/V
–1.15
0
%
UNITS
±0.05
%
±3.85
V
9.5
–200
–75
–50
–50
±50
–95
–21
–5
–1
±105
mA
mA
µA
µA
µA
µA
µA
µA
mA
1200
2100
V/µs
VOUT = 200mVP-P
750
MHz
120
MHz
335
175
MHz
MHz
dB
dB
dB
dB
I⎯E⎯N
Enable Pin Current
ISEL
Select Pin Current
ISC
Output Short-Circuit Current
SR
Slew Rate
±1V on ±2.2V Output Step (Note 8)
–3dB BW
Small-Signal –3dB Bandwidth
0.1dB BW
Gain Flatness ±0.1dB Bandwidth
VOUT = 200mVP-P
FPBW
Full Power Bandwidth 2V
Full Power Bandwidth 4V
All-Hostile Crosstalk
VOUT = 2VP-P (Note 9)
VOUT = 4VP-P (Note 9)
f = 10MHz, VIN = 2VP-P
f = 100MHz, VIN = 2VP-P
f = 10MHz, VIN = 2VP-P
f = 100MHz, VIN = 2VP-P
INA = INB = 0V
Channel-to-Channel Select Time
±3.65
MAX
●
V⎯E⎯N = 4V, RL = ∞
V⎯E⎯N = Open, RL = ∞
V⎯E⎯N = 0.4V
V⎯E⎯N = 4V
VSEL = 0.4V
VSEL = 4V
RL = 0Ω, VIN = ±2V, VREF = ±1V
Selected Channel to Unselected
Channel Crosstalk
Channel Select Output Transient
–2.8
TYP
●
●
●
●
●
●
●
47
42
190
–72
–52
–85
–64
200
13
14.5
330
330
mVP-P
8
ns
6.5
ns
500
ps
tS
Settling Time
INA = –1V, INB = 1V
from 50% SEL to VOUT = 0V
0.1% of VFINAL, VSTEP = 2V
tR, tF
Small-Signal Rise and Fall Time
10% to 90%, VOUT = 200mVP-P
dG
Differential Gain
(Note 10)
0.056
%
0.028
Deg
dP
Differential Phase
(Note 10)
HD2
2nd Harmonic Distortion
f = 10MHz, VOUT = 2VP-P
–84
dBc
HD3
3rd Harmonic Distortion
f = 10MHz, VOUT = 2VP-P
–87
dBc
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This parameter is guaranteed to meet specified performance
through design and characterization. It is not production tested.
Note 3: As long as output current and junction temperature are kept
below the Absolute Maximum Ratings, no damage to the part will occur.
Depending on the supply voltage, a heat sink may be required.
Note 4: The LT6556C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: The LT6556C is guaranteed to meet specified performance from
0°C to 70°C. The LT6556C is designed, characterized and expected to
meet specified performance from –40°C and 85°C but is not tested or
QA sampled at these temperatures. The LT6556I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: In order to follow the constraints for 4.5V operation for PSRR
and IPSRR testing at ± 2.25V, the DGND pin is set to V–, the ⎯E⎯N pin is set
to V– + 0.4V, and the SEL pin is set to either V– + 0.4V or V– + 4V. At ±6V
and all other cases, DGND is set to ground and the ⎯E⎯N and SEL pins are
referenced from it.
Note 7: The VREF pin is set to 3V when testing positive swing and –3V
when testing negative swing to ensure that the internal input clamps do
not limit the output swing.
Note 8: Slew rate is 100% production tested using both inputs of
channel 2. Slew rates of channels 1 and 3 are guaranteed through
design and characterization.
Note 9: Full power bandwidth is calculated from the slew rate:
FPBW = SR/(π • VP-P)
Note 10: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set. The resolution of this equipment is better than 0.05%
and 0.05°. Nine identical amplifier stages were cascaded giving an
effective resolution of better than 0.0056% and 0.0056°.
6556f
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LT6556
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current per Amplifier
vs Temperature
12
VS = ±5V
VEN, VIN, VDGND, VSEL = 0V
10 TA = 25°C
VEN = 0.4V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
12
VS = ±5V
RL = ∞
VIN = 0V
VEN = 0V
10
Supply Current per Amplifier
vs ⎯E⎯N Pin Voltage
8
6
4
8
6
4
2
2
VS = ±5V
RL = ∞
VIN = 0V
10
SUPPLY CURRENT (mA)
12
Supply Current per Amplifier
vs Supply Voltage
TA = –55°C
8
TA = 25°C
6
TA = 125°C
4
2
VEN = 4V
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0
1
2
0
VS = ±5V
VIN = 0V
VS = ±5V
5
VIN = 1.5V
–10
–15
VIN = 0V
–20
VIN = –1.5V
–25
–30
–40
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
Maximum Output Voltage Swing
vs VREF Pin Voltage
OUTPUT VOLTAGE (V)
3
VS = ±5V
RL = 1k
4
–1
TA = 25°C
TA = 125°C
TA = 125°C
TA = 25°C
–2
–3
–4
–5
–140
0
TA = –55°C
3
TA = 125°C
2
TA = 25°C
1
TA = –55°C
1
3
2
EN PIN VOLTAGE (V)
5
4
6556 G06
0
VS = ±5V
VIN = 4V
VVREF = 3V
TA = –55°C
2
0
TA = 25°C
–100
Output Voltage Swing
vs ILOAD (Output Low)
5
HIGH SWING
1
TA = –55°C
–80
Output Voltage Swing
vs ILOAD (Output High)
OUTPUT VOLTAGE (V)
4
TA = 125°C
–60
6556 G05
6556 G04
5
–40
–120
–35
0
–55 –35 –15
VS = ±5V
VDGND = 0V
–20
EN PIN CURRENT (μA)
INPUT BIAS CURRENT ( A)
OFFSET VOLTAGE (mV)
10
4.0
⎯E⎯N Pin Current vs ⎯E⎯N Pin Voltage
0
–5
15
3.5
1.0 1.5 2.0 2.5 3.0
EN PIN VOLTAGE (V)
0.5
6556 G03
Input Bias Current
vs Temperature
Offset Voltage vs Temperature
20
0
6556 G02
6556 G01
25
0
3 4 5 6 7 8 9 10 11 12
TOTAL SUPPLY VOLTAGE (V)
VS = ±5V
VIN = –4V
VVREF = –3V
–1
OUTPUT VOLTAGE (V)
0
–55 –35 –15
TA = 125°C
TA = –55°C
–2
TA = 25°C
–3
–4
LOW SWING
–2 –1.5 –1 –0.5 0 0.5 1
VREF PIN VOLTAGE (V)
1.5
2
6556 G07
0
0
10 20 30 40 50 60 70 80 90 100
SOURCE CURRENT (mA)
6556 G08
–5
0
10 20 30 40 50 60 70 80 90 100
SINK CURRENT (mA)
6556 G09
6556f
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LT6556
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise Spectral Density
1000
in
10
100
10
1
VS = ±5V
TA = 25°C
±PSRR
60
REJECTION RATIO (dB)
en
100
PSRR vs Frequency
70
VS = ±5V
VIN = 0V
TA = 25°C
VS = ±5V
TA = 25°C
INPUT IMPEDANCE (kΩ)
INPUT NOISE (nV/√Hz OR pA/√Hz)
Input Impedance vs Frequency
1000
–PSRR
50
+PSRR
40
30
20
10
0.1
0.01
1
0.001
0.01
0.1
1
FREQUENCY (kHz)
10
100
0.1
1
10
FREQUENCY (MHz)
100
0
0.001
1000
0.01
0.1
1
FREQUENCY (MHz)
10
100
6556 G12
6556 G11
6556 G10
Frequency Response
vs Output Amplitude
1
0.10
GAIN (dB)
–1
VOUT = 200mVP-P
–2
VOUT = 2VP-P
–3
IN3B
IN1A
0
–0.05
VOUT = 4VP-P
–4
–0.10
IN1B
–5
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
3
CL = 10pF
CL = 15pF
CL = 6.8pF
0
CL = 3.3pF
–3
IN3A
IN2A
CL = 0pF
–6
0.1
1
10
100
FREQUENCY (MHz)
1000
–0.15
0.1
1
10
100
FREQUENCY (MHz)
Crosstalk vs Frequency
–40
AMPLITUDE (dB)
–40
DRIVE IN A;
SELECT IN B
10
100
FREQUENCY (MHz)
–60
WORST
ADJACENT
–80
–10
–20
–30
ALL CHANNELS
DRIVEN
VS = ±5V
VOUT = 2VP-P
RL = 1k
TA = 25°C
–40
–50
–60
–70
–80
HD2
HD3
–90
DRIVE IN B;
SELECT IN A
1000
Harmonic Distortion vs Frequency
0
VS = ±5V
VOUT = 2VP-P
–20 RL = 1k
TA = 25°C
–60
1
6555 G15
0
VS = ±5V
VOUT = 2VP-P
–20 RL = 1k
TA = 25°C
–100
1000
Crosstalk vs Frequency
0
–80
–6
0.1
6556 G14
6556 G13
AMPLITUDE (dB)
6
IN2B
0.05
0
GAIN (dB)
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
AMPLITUDE (dB)
2
9
0.15
VS = ±5V
RL = 1k
TA = 25°C
DISTORTION (dBc)
3
Frequency Response with
Capacitive Loads
Gain Flatness vs Frequency
–100
–100
–110
–120
0.1
1
10
100
FREQUENCY (MHz)
1000
6556 G16
–120
0.1
1
10
100
FREQUENCY (MHz)
1000
6556 G17
–120
0.01
0.1
1
10
FREQUENCY (MHz)
100
6556 G18
6556f
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LT6556
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Capacitive Load vs
Output Series Resistor
Output Impedance vs Frequency
100000
30
1000
100
10
ENABLED
VEN = O.4V
1
VS = ±5V
TA = 25°C
VOUT = 2VP–P
VS = ±5V
RL = 1k
TA = 25°C
20
15
AC PEAKING
>3dB
10
0.1
1
10
FREQUENCY (MHz)
100
–0.20
10
100
CAPACITIVE LOAD (pF)
0.7
0.6
0.2
1.5
0.5
0
–0.5
0
–1.5
–0.1
–2.0
4
6
8 10 12 14 16 18 20
TIME (ns)
20
15
10
5
0
8 10 12 14 16 18 20
TIME (ns)
2
4
6
0
–1.3 –1.25 –1.2 –1.15 –1.1 –1.05 –1.0 –.95 –.90
GAIN ERROR—INDIVIDUAL CHANNEL (%)
8 10 12 14 16 18 20
TIME (ns)
6556 G24
6556 G23
6556 G22
Gain Error Matching Distribution
Channel Switching Transient
Channel Switching Transient
40
0.15
0.10
0.05
0
1.5
1.0
0.5
0
–0.05
25
VS = ±5V
RL = 1k
20
10
5
0
–0.1 –0.075 –0.05 –0.025 0 0.025 0.05 0.075 0.1
GAIN ERROR—BETWEEN CHANNELS (%)
6556 G25
–1.0
5
5
4
4
SEL A/B (V)
SEL A/B (V)
15
–0.5
–0.10
INA = INB = 0V
TA = 25°C
3
2
1
0
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
6556 G26
OUTPUT (V)
VS = ±5V
VOUT = ±2V
RL = 1k
TA = 25°C
OUTPUT (V)
PERCENT OF UNITS (%)
25
–2.5
–0.2
2
6
VS = ±5V
VOUT = ±2V
RL = 1k
TA = 25°C
30
–1.0
0.1
0
4
Gain Error Distribution
VIN = 4VP-P
VS = ±5V
RL = 1k
TA = 25°C
2.0
OUTPUT (V)
0.3
2
35
2.5
1.0
0.4
0
6556 G21
Large-Signal Transient Response
0.5
OUTPUT (V)
1000
6556 G20
VIN = 700mVP-P
VS = ±5V
RL = 1k
TA = 25°C
0.8
VIN = 200mVP-P
VS = ±5V
RL = 1k
TA = 25°C
–0.15
1
Video Amplitude Transient
Response
0.9
0
–0.10
5
1000
0.05
–0.05
6556 G19
30
0.10
25
0
0.1
0.01
35
0.15
PERCENT OF UNITS (%)
10000
Small-Signal Transient Response
0.20
OUTPUT (V)
DISABLED
VEN = 4V
OUTPUT SERIES RESISTANCE ( )
35
OUTPUT IMPEDANCE (Ω)
1000000
VS = ±5V
RL = 1k
INB = 300MHz, 2VP-P SINE
TA = 25°C INA = 0V
–1.5
3
2
1
0
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
6556 G27
6556f
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LT6556
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PI FU CTIO S
(GN24 Package)
IN1A (Pin 1): Channel 1 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
be connected externally. Proper supply bypassing is
necessary for best performance. See the Applications
Information section.
DGND (Pin 2): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
V– (Pin 15): Negative Supply Voltage for Channel 3 Output
Stage. V– pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
IN2A (Pin 3): Channel 2 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
VREF (Pin 4): Voltage Reference for Input Clamping. This
is the tap to an internal voltage divider that defines midsupply. It is normally connected to ground in dual supply,
DC coupled applications.
IN3A (Pin 5): Channel 3 Input A. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 6): Analog Ground for Isolation between IN3A
and IN1B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN1B (Pin 7): Channel 1 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 8): Analog Ground for Isolation between IN1B
and IN2B. AGND pins have ESD protection and should not be
connected to potentials outside the power supply range.
IN2B (Pin 9): Channel 2 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
AGND (Pin 10): Analog Ground for Isolation between
IN2B and IN3B. AGND pins have ESD protection and
should not be connected to potentials outside the power
supply range.
IN3B (Pin 11): Channel 3 Input B. This pin has a nominal
impedance of 500kΩ and does not have any internal
termination resistor.
V– (Pin 12): Negative Supply Voltage. V– pins are not internally connected to each other and must all be connected
externally. Proper supply bypassing is necessary for best
performance. See the Applications Information section.
V+ (Pins 13, 14, 24): Positive Supply Voltage. V+ pins
are not internally connected to each other and must all
OUT3 (Pin 16): Channel 3 Output. It is the buffered output
of the selected Channel 3 input.
V+ (Pin 17): Positive Supply Voltage for Channels 2 and
3 Output Stages. V+ pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT2 (Pin 18): Channel 2 Output. It is the buffered output
of the selected Channel 2 input.
V– (Pin 19): Negative Supply Voltage for Channels 1 and
2 Output Stages. V– pins are not internally connected to
each other and must all be connected externally. Proper
supply bypassing is necessary for best performance. See
the Applications Information section.
OUT1 (Pin 20): Channel 1 Output. It is the buffered output
of the selected Channel 1 input.
V+ (Pin 21): Positive Supply Voltage for Channel 1 Output
Stage. V+ pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
SEL ⎯A/B (Pin 22): Select Pin. This high impedance pin
selects which set of inputs are sent to the output pins.
When the pin is pulled low, the A inputs are selected. When
the pin is pulled high, the B inputs are selected.
⎯ (Pin 23): Enable Control Pin. An internal pull-up resistor
E⎯ N
of 46k defines the pin’s impedance and will turn the part
off if the pin is unconnected. When the pin is pulled low,
the amplifiers are enabled.
Exposed Pad (Pin 25, QFN Only): The Exposed Pad is
V– and must be soldered to the PCB. It is internally connected to the QFN Pin 4, V–.
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Power Supplies
The LT6556 is optimized for ±5V supplies but can be operated on as little as ±2.25V or a single 4.5V supply and
as much as ±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected or the part may
not function correctly!
Enable/Shutdown
The LT6556 has a shutdown mode controlled by the ⎯E⎯N
pin and referenced to the DGND pin. If the amplifier will be
enabled at all times, the ⎯E⎯N pin can be connected directly
to DGND. If the enable function is desired, either driving
the pin above 2V or allowing the internal 46k pull-up
resistor to pull the ⎯E⎯N pin to the top rail will disable the
amplifier. When disabled, the output will become very
high impedance. Supply current into the amplifier in the
disabled state will be:
IS =
V + – VEN V + – V –
+
46k
80k
It is important that the following constraints on the DGND,
⎯E⎯N and SEL pins are always followed:
V+ – VDGND ≥ 4.5V
-0.5V ≤ V⎯E⎯N – VDGND ≤ 5.5V
VSEL – VDGND ≤ 8V
In dual supply cases where V+ is less than 4.5V, DGND
should be connected to a potential below ground, such as
V–. Since the ⎯E⎯N and SEL pins are referenced to DGND, they
may need to be pulled below ground in those cases. However,
in order to protect the internal enable circuitry, the ⎯E⎯N pin
should not be forced more than 0.5V below DGND.
In single supply applications above 5.5V, an additional
resistor may be needed from the ⎯E⎯N pin to DGND if the
pin is ever allowed to float. For example, on a 12V single
supply, a 33k resistor would protect the pin from floating
too high while still allowing the internal pull-up resistor
to disable the part.
On dual ±2.25V supplies, connecting the DGND pin to V– is
the only way of ensuring that V+ – VDGND ≥ 4.5V.
The enable/disable times of the LT6556 are fast when
driven with a logic input. Turn on (from 50% ⎯E⎯N input to
50% output) typically occurs in less than 50ns. Turn off
is slower, but is typically below 500ns.
Channel Select
The SEL pin uses the same internal threshold as the ⎯E⎯N
pin and is also referenced to DGND. When the pin is logic
low, the channel A inputs are passed to the output. When
the pin is logic high, the channel B inputs are passed to
the output. The pin should not be floated but can be tied
to DGND to force the outputs to always be channel A or
to V+ (when less than 8V) to force the outputs to always
be channel B.
Truth Table
SEL ⎯A/B
⎯E⎯N
OUT
0
0
IN A
1
0
IN B
X
1
OFF
Input Considerations
The LT6556 uses input clamps referenced to the VREF pin
to prevent damage to the input stage on the unselected
channel. Three transistors in series limit the input voltage to
within three diode drops (±) from VREF . VREF is nominally
set to half of the sum of the supplies by the 40k resistors.
A simplified schematic is shown in Figure 1.
V+
40k
IN
VREF
40k
V–
6556 F01
Figure 1. Simplified Schematic of VREF Pin and Input Clamping
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To improve clamping, the pin’s DC impedance should be
minimized by connecting the VREF pin directly to ground
in the symmetric dual supply case with a common mode
voltage of 0V. If the common mode voltage is not centered
at ground or the input voltage exceeds plus or minus three
diodes from ground, an external resistor to either supply
can be added to shift the VREF voltage to the desired level.
The only way to cover the full input voltage range of V– +
1V to V+ – 1V is to shift VREF up or down.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
benefit from the very high speed and very low crosstalk of
the LT6556. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input traces must be run over a distance of
several centimeters, they should use a controlled impedance with either series or shunt terminations (nominally
50Ω or 75Ω) to maintain signal fidelity.
The VREF pin can also be directly driven with a DC source.
Figure 2 shows the effect of the clamp on input current
when sweeping input voltage with various VREF pin voltages. Bypassing the VREF pin is not necessary.
Care should be taken to minimize capacitance on the
LT6556’s output traces by increasing spacing between
traces and adjacent metal and by eliminating metal planes
in underlying layers. To drive cable or traces longer than
several centimeters, using the LT6555 with its fixed gain
of+2 in conjunction with series and load termination resistors may provide better results.
250
VREF = –2V
VREF = –1V
VREF = 0V
VREF = 1V
VREF = 2V
200
INPUT CURRENT (μA)
150
100
50
0
–50
–100
–150
TA = 25°C
VS = ±5V
–200
–250
–4
–3
–2
0
1
–1
2
INPUT VOLTAGE (V)
3
4
6556 F02
A plot of AC performance driving a 1k load with various
trace lengths is shown in Figure 3. All data is from a 4-layer
board with 2oz copper, 18mil of board layer thickness to
the ground plane, a trace width of 12mils and spacing to
adjacent metal of 18mils. The 0.2cm output trace places
the 1k resistor as close to the part as possible, while the
other curves show the load resistor consecutively further
away. The worst case, 4cm, trace has almost 10pF of
parasitic capacitance.
Figure 2. Input Current vs Input Voltage
at Different VREF Voltages
6
AMPLITUDE (dB)
4
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to less
than ±10mA. Continuing to drive the input beyond the
output limit can result in increased current drive and
slightly increased swing, but will also increase supply
current and may result in delays in transient response
at larger levels of overdrive.
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
4cm TRACE
2
2cm TRACE
0
0.2cm TRACE
–2
–4
–6
0.1
1
10
100
FREQUENCY (MHz)
1000
6556 F03
Figure 3. Response vs Output Trace Length
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In order to counteract any peaking in the frequency response from driving a capacitive load, a series resistance
can be inserted in the line at the output of the part to flatten the response. Figure 4 shows the frequency response
with the same 4cm trace from Figure 3, now with a 10Ω
series resistor inserted near the output pin of the amplifier. Note that using a 10Ω series resistor with a 1k load
only decreases the output amplitude by 0.1dB or 1% and
has a minimal effect on the bandwidth of the system. See
the graph labeled “Maximum Capacitive Load vs Output
Series Resistor” in the Typical Performance Characteristics
section for more information.
6
AMPLITUDE (dB)
4
VS = ±5V
VOUT = 200mVP-P
RL = 1k
TA = 25°C
4cm TRACE
0
4cm TRACE
RS, OUT = 10Ω
–4
–6
0.1
1
10
100
FREQUENCY (MHz)
Single Supply Operation
Figure 5 illustrates how to use the LT6556 with a single
supply ranging from 4.5V to 12V. Since the output range is
comparable to the input range, the DC bias point at the input
can be set anywhere between the supplies that will prevent
the AC-coupled signal from running into the output range
limits. As shown, the DC input level is mid-supply.
The only additional power dissipation in the single supply
configuration is through the resistor bias string at the input
and through any load resistance at the output. In many
cases, the output can be used to directly drive other single
supply devices without additional coupling and without
any resistive load.
2
–2
To maintain the LT6556’s channel isolation, it is beneficial
to shield parallel input and parallel output traces using a
ground plane or power supply traces. Vias between topside and backside metal may be required to maintain a
low inductance ground near the part where numerous
traces converge. See Figures 7 and 8 for photos of an
optimized layout.
4.5V TO 12V
1000
6556 F04
Figure 4. Response vs Series Output Resistance
5k
22μF
IN
VIN
While the AGND pins on the LT6556 are not connected to
the amplifier circuitry, tying them to ground or another
“quiet” node significantly increases channel isolation
and is always recommended. The AGND pins do have
ESD protection and therefore should not be connected to
potentials outside the power supply range.
Low ESL/ESR bypass capacitors should be placed as close
to the positive and negative supply pins as possible. One
4700pF ceramic capacitor is recommended for both V+
and V– supply busses. Additional 470pF ceramic capacitors
with minimal trace length on each supply pin will further
improve AC and transient response as well as channel
isolation. For high current drive and large-signal transient
applications, additional 1µF to 10µF tantalums should
be added on each supply. The smallest value capacitors
should be placed closest to the package.
5k
AGND
V+
1/3
LT6556
OUT
V–
6556 F05
Figure 5. Single Supply Configuration, One Channel Shown
Input Expansion
In applications with more than two inputs per channel,
multiple LT6556s can be connected directly together at the
outputs. Logic circuitry can be used to drive the ⎯E⎯N pins
of each LT6556 to ensure that only one set of channels is
buffered at a time. See Figure 9 for a schematic.
Since the output impedance of a disabled LT6556 is high,
adding additional channels will not resistively load an
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LT6556
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enabled output. However, since the disabled LT6556 and its
traces have around 6pF of capacitance, it may be desirable
to resistively isolate the outputs of each channel to maintain
flat frequency response as shown in the graph labeled
“Maximum Capacitive Load vs Output Series Resistor” in
the Typical Performance Characteristics section.
ESD Protection
The LT6556 has reverse-biased ESD protection diodes on all
pins. If any pins are forced a diode drop above the positive
supply or a diode drop below the negative supply, large
currents may flow through these diodes. If the current is
kept below 10mA, no damage to the devices will occur.
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TYPICAL APPLICATIO
RGB Multiplexer Demo Board
traces and isolate the part from any capacitive loading in
those traces, they also contribute to gain error if the output is not terminated with high impedance. For example,
if the output is terminated with a 1k load, the 75Ω back
termination will cause a 7% gain error. Decreasing the
value of the back termination resistors will decrease the
signal attenuation but may compromise the AC response.
However, connecting the LT6556 output pins to the output
traces on the DC892A board without some series resistance
is not recommended; 10Ω to 20Ω is generally sufficient.
Figures 7 and 8 show the top and bottom side board layout
and placement.
The DC892A Demo Board illustrates optimal routing,
bypassing and termination using the LT6556 as an
RGB video multiplexer. The schematic is shown in Figure 6.
All inputs and outputs are routed to have a characteristic
impedance of 75Ω and 75Ω input shunt and output series
terminations are connected as close to the part as possible. The board is fabricated with four layers with internal
ground and power planes.
While the 75Ω back termination resistors at the outputs
of the LT6556 minimize signal reflections in the output
E1
EN
J1
50Ω BNC
1
EN
5 4 3 2 DGND
E4
SEL A/B
Z = 50
JP1
3 CONTROL 1
E2
DGND
2
R9
50Ω
OPT
R8
50Ω
OPT
2
EXT ENABLE
J8
50Ω BNC
1
SEL A/B
Z = 50
3 A
R7
B 1 20k
VCC
JP4
SEL
DGND
5 4 3 2
JP2
3 DGND 1
2
FLOAT AGND
3
IN1A
IN2A
IN3A
IN1B
IN2B
IN3B
BNC × 6
5 JP12
1 L1 Z = 75
4
3
2
5 JP13
1 L1 Z = 75
4
3
2
5 JP14
1 L1 Z = 75
4
3
2
5 JP5
1 L1 Z = 75
4
3
2
5 JP6
1 L1 Z = 75
4
3
2
5 JP7
1 L1 Z = 75
4
3
2
JP5
VREF
2
EXT
E5
VREF
C1
4700pF
GND
C2
470pF
C3
470pF
C10
4700pF
U1 LT6556CUF
22
21
V+
IN1A
DGND 23
24
VREF
1
2
3
5
6
7
8
9
R10
75Ω
J2
BANANA JACK
VCC
3.3V TO 5V
1
R11
75Ω
R12
75Ω
R4
75Ω
R5
75Ω
R6
75Ω
4
DGND
EN
SEL A/B
IN2A
IN3A
OUT1
V–
AGND1
IN1B
OUT2
V+
AGND2
OUT3
IN2B
AGND3
IN3B
V–
–
V
19
E3
AGND
17
16
15
14
13
V–
12
V+
11
V+
10
C5
4700pF
1 JP3 3
SUPPLY
R1
75Ω
Z = 75
L2
R2
75Ω
Z = 75
L2
R3
75Ω
SINGLE DUAL
2
AGND
CC
SEL
25
J3
BANANA JACK
C7
0.33μF
10V V
20 EN
18
V+
VREF
C4
10μF
16V
1206
C6
470pF
C9
10μF
16V
1206
C8
0.33μF
10V
Z = 75
L2
BNC × 3
5
J9
4
3
2
J10 5
1
4
3
2
J11 5
1
4
3
2
1
OUT1
OUT2
OUT3
J4
BANANA JACK
VEE
–3.3V TO –5V
VEE
6556 F06
NOTE:
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
Figure 6. Demo Board Schematic
6556f
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LT6556
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TYPICAL APPLICATIO
Figure 7. Demo Board Topside
(IC Removed for Clarity)
Figure 8. Demo Board Bottom Side
6556f
12
V–
DGND
1k
46k
BIAS
V+
SELECT
TO OTHER
OUTPUT
STAGES
770Ω
SEL
TO OTHER
INPUT STAGES
INA 100Ω
V–
V+
VREF
V–
40k
40k V
REF
INB 100Ω
V–
V+
VREF
VREF
360Ω
6556 SS
360Ω
V–
OUT
V+
W
W
SI PLIFIED SCHE ATIC
EN
V+
LT6556
(One channel shown)
6556f
13
LT6556
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PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 1413
.033
(0.838)
REF
.045 ±.005
.229 – .244
(5.817 – 6.198)
.254 MIN
.150 – .157**
(3.810 – 3.988)
.150 – .165
1
.0165 ± .0015
2 3
4
5 6
7
8
9 10 11 12
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN24 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
6556f
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LT6556
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UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6556f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6556
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TYPICAL APPLICATIO
RED 1
GREEN 1
BLUE 1
V+
LT6556 #1
75Ω
IN1A
IN1B
5V
OUT1
×1
75Ω
75Ω
RED 2
GREEN 2
BLUE 2
IN2A
OUT2
×1
IN2B
75Ω
75Ω
IN3A
75Ω
OUT3
×1
IN3B
AGND
DGND
SEL
VREF
EN
V
ROUT
–
–2V
5V
RED 3
GREEN 3
BLUE 3
LT6556 #2
75Ω
GOUT
V+
IN1A
IN1B
OUT1
×1
BOUT
75Ω
75Ω
RED 4
GREEN 4
BLUE 4
IN2A
IN2B
OUT2
×1
75Ω
75Ω
IN3A
IN3B
75Ω
OUT3
×1
AGND
DGND
SEL
VREF
EN
SEL0
V–
NC7SZ14
SEL1 SEL0 OUTPUT
0
0
1
0
1
2
1
0
3
1
1
4
SEL1
6556 F09
–2V
Figure 9. 4:1 RGB Multiplexer
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1203
150MHz Single 2:1 Multiplexer
Single SPDT Video Switch
LT1399
300MHz Triple Current Feedback Amplifier
0.1dB Gain Flatness to 150MHz, Shutdown
LT1675
250MHz Triple RGB Multiplexer
100MHz Pixel Switching, 1100V/µs Slew Rate, 16-Lead SSOP
LT6550/LT6551
3.3V Triple and Quad Video Buffers
110MHz Gain of 2 Buffers in MS Package
LT6553
650MHz Gain of 2 Triple Video Amplifier
Same Pinout as the LT6554 but Optimized for Driving 75Ω Cables
LT6554
650MHz Gain of 1 Triple Video Amplifier
Performance Similar to the LT6556 with One Set of Inputs, 16-Lead SSOP
LT6555
650MHz Gain of 2 Triple Video Multiplexer
Same Pinout as the LT6556 but Optimized for Driving 75Ω Cables
6556f
16 Linear Technology Corporation
LT/TP 0805 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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