100VIN
LT8310
Forward Converter
Controller
Features
Description
Input Voltage Range: 6V to 100V
n Duty Mode Control Regulates an Isolated Output
without an Opto
n High Efficiency Synchronous Control
n Short-Circuit (Hiccup Mode) Overcurrent Protection
n Programmable OVLO and UVLO with Hysteresis
n Programmable Frequency (100kHz to 500kHz)
n Synchronizable to an External Clock
n Positive or Negative Polarity Output Voltage Feedback
with a Single FBX Pin
n Programmable Soft-Start
n Low Shutdown Current < 1µA
n Available in FE20 TSSOP with HV Pin Spacing
The LT®8310 is a simple-to-use resonant reset forward
converter controller that drives the gate of a low side
N-channel MOSFET from an internally regulated 10V supply. The LT8310 features duty mode control that generates
a stable, regulated, isolated output using a single power
transformer. With the addition of output voltage feedback,
via opto-coupler (isolated) or directly wired (nonisolated),
current mode regulation is activated, improving output
accuracy and load response. The flexibility to choose
transformer turns ratio makes high step-down or step-up
ratios possible without operating at duty cycle extremes.
n
Applications
Industrial, Automotive and Military Systems
48V Telecommunication Isolated Power Supplies
n Isolated and Nonisolated DC/DC Converters
n
n
The user can program the switching frequency from 100kHz
to 500kHz to optimize efficiency, performance or external
component size. A synchronous output is available for
controlling secondary side synchronous rectification to
improve efficiency. User programmable protection features
include monitors on input voltage (UVLO and OVLO) and
switch current (overcurrent limit). The LT8310 soft-start
feature helps protect the transformer from flux saturation.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
78 Watt Isolated Forward Converter, ±8% VOUT
47µH
2.2µF
100V
×4
2:1
1µF
100V
86.6k
•
•
UVLO VIN
1.74k
LT8310
1.43k
4.7µF
10nF
–VIN
49.9k
200kHz
100µF
13.5
GATE
INTVCC
SENSE
0.025Ω
1%
102k
NC
+
RDVIN
DFILT
SYNC
RT SS
0.47µF
GND
SOUT
VC FBX
Output Voltage Load Regulation
14.0
13.0
–VOUT
150pF
NPO
OVLO
22µF
×8
VOUT
12V
0.6A TO 6.5A
VOUT (V)
VIN
36V TO 72V
12.5
12.0
11.5
11.0
NC
8310 TA01a
10.0
NC
VIN = 72V
VIN = 48V
VIN = 36V
10.5
0
1
2
4
3
IOUT (A)
5
6
7
8310 TA01b
8310f
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1
LT8310
Absolute Maximum Ratings
(Notes 1, 2)
VIN, UVLO................................................................100V
INTVCC, RDVIN, SYNC...............................................20V
DFILT...........................................................................8V
VC, OVLO, SS, RT.........................................................3V
FBX.................................................................. –3V to 3V
SENSE........................................................ –0.3V to 0.3V
GATE, SOUT...........................................................Note 3
Operating Junction Temperature Range (Notes 4, 5)
LT8310E.............................................. –40°C to 125°C
LT8310I............................................... –40°C to 125°C
LT8310H............................................. –40°C to 150°C
LT8310MP.......................................... –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature Range (Soldering, 10 sec)......... 300°C
Pin Configuration
TOP VIEW
UVLO
1
20 NC
OVLO
3
18 VIN
DFILT
5
RT
6
SYNC
7
14 GATE
SS
8
13 SENSE
VC
9
12 NC
FBX 10
21
GND
16 RDVIN
15 INTVCC
11 SOUT
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C (E-, I-GRADES), TJMAX = 150°C (H-GRADE),
θJC = 10°C/W, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO THE GROUND PLANE
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8310EFE#PBF
LT8310EFE#TRPBF
LT8310FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8310IFE#PBF
LT8310IFE#TRPBF
LT8310FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8310HFE#PBF
LT8310HFE#TRPBF
LT8310FE
20-Lead Plastic TSSOP
–40°C to 150°C
LT8310MPFE#PBF
LT8310MPFE#TRPBF
LT8310FE
20-Lead Plastic TSSOP
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
8310f
For more information www.linear.com/LT8310
LT8310
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply
100
V
VIN Supply Current in Shutdown
UVLO = 0V
UVLO = 1.15V
0.3
5
1
7
µA
µA
VIN Operating Current
Not Switching
3.8
4.6
mA
1.220
1.250
Operating Input Voltage
l
6
UVLO
UVLO Threshold Voltage
UVLO Falling
UVLO Threshold Hysteresis
UVLO Rising
UVLO Low Quiescent Current Threshold
IVIN < 1µA
UVLO Pin Input Current
UVLO = 1.15V
UVLO = 1.30V
l
1.196
40
l
V
mV
0.36
0.62
0.85
V
4.5
5.7
20
6.8
150
µA
nA
1.225
1.250
1.275
V
OVLO
OVLO Threshold Voltage
OVLO Rising
OVLO Threshold Hysteresis
OVLO Falling
–33
OVLO Pin Input Current
OVLO = 1.17V
OVLO = 1.32V
10
120
150
400
nA
nA
10.0
10.3
V
l
mV
Linear Regulator
INTVCC Regulation Voltage
IINTVCC = 0mA to 20mA
Regulator Dropout Voltage (VIN – INTVCC)
VIN = 9V, IINTVCC = 20mA
INTVCC Undervoltage Lockout Threshold
INTVCC Falling
l
9.6
600
4.60
INTVCC Undervoltage Hysteresis
INTVCC Overvoltage Lockout Threshold
4.75
mV
4.90
0.45
INTVCC Rising
17.0
INTVCC Overvoltage Hysteresis
17.4
17.8
–0.65
INTVCC Current Limit
VIN = 12V
INTVCC Current in Shutdown
UVLO = 0V, INTVCC = 10V
INTVCC Line Regulation
10.8V ≤ VIN ≤ 100V
INTVCC Load Regulation
0mA ≤ IINTVCC ≤ 20mA
l
25
33
–3.0
V
V
39
mA
0.01
%/V
125
0.001
V
V
µA
–0.4
%
190
ns
Duty Cycle Control
Minimum GATE On-Time
Maximum Duty Cycle
VIN = 12V
RDVIN Pin Input Current
Duty Control Transconductance (Note 6)
(ΔIDFILT / ΔVSET)
VSET = 1V
Duty Mode Control Gain (Notes 6, 7),
Gain = VIN /VSET at IDFILT = 0µA
VSET = 0.5V to 6V
Duty Cycle Foldback,
Foldback = Duty at VSS = 1.15V/Duty (Nom)
SS = 1.15V
l
75
78
82
%
l
19.7
20.0
20.3
µA
22.5
25.0
27.5
µA/V
11.76
12.00
12.24
V/V
l
0.14
%/%
Error Amplifier
FBX Error Amp Reference Voltage
FBX > 0V
FBX < 0V
FBX Overvoltage Threshold
FBX > 0V
FBX < 0V
l
l
1.568
–0.820
1.600
–0.800
1.632
–0.780
V
V
6
5.5
7.5
7.5
9
10
%
%
8310f
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3
LT8310
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Feedback Mode Threshold Voltage
(Below = Duty Mode/Above = Current Mode)
FBX > 0V
FBX < 0V
0.2
–0.3
0.3
–0.2
0.4
–0.13
V
V
Feedback Mode Threshold Hysteresis
FBX > 0V
FBX < 0V
FBX Pin Input Current
FBX = 1.6V
FBX = –0.8V
20
20
–100
Transconductance (ΔIVC /ΔVFBX)
70
0
mV
mV
100
100
nA
nA
250
µA/V
VC Source Current
VFBX = 0V, VVC = 1.3V
–14
µA
VC Sink Current
VFBX = 1.7V, VVC = 1.3V
VFBX = –0.85V, VVC = 1.3V
13
11
µA
µA
VC Pin Output Impedance
3.3
MΩ
VC Pin Current Mode Gain
5
V/V
Gate Driver
GATE Rise Time
CGATE = 3.3nF
30
ns
GATE Fall Time
CGATE = 3.3nF
27
ns
GATE Low Voltage
0.05
GATE High Voltage
V
V
INTVCC
– 0.05
Current Sense
SENSE Pin Maximum Current Threshold
l
115
SENSE Pin Input Current
125
135
–200
mV
µA
Oscillator
Switching Frequency
RT = 100k to GND, VSS ≥ 2.9V
RT = 33.2k to GND, VSS ≥ 2.9V
RT = 20k to GND, VSS ≥ 2.9V
l
l
l
95
285
475
100
300
500
105
315
525
kHz
kHz
kHz
Switching Frequency Line Regulation
VIN = 6V to 100V
RT Pin Voltage
VSS = 3V
0.8
1.0
1.3
V
Frequency Foldback
Foldback = (fOSC at VSS = 1.15V)/fOSC(NOM)
VSS = 1.15V
0.15
0.20
0.25
Hz/Hz
2.00
V
SYNC Pin Input High Threshold Voltage
0.01
l
SYNC Pin Input Low Threshold Voltage
l
%
1.00
V
SYNC Pin Input Resistance
SYNC = 2V
200
SYNC Frequency Operating Range
RT = 33.2k
l
400
kHz
Minimum SYNC High Setup Time
fSW = 400kHz
l
250
ns
Minimum SYNC Low Hold Time
fSW = 400kHz
l
250
ns
260
kΩ
SOUT Driver
SOUT Rise Time
CSOUT = 1nF
20
ns
SOUT Fall Time
CSOUT = 1nF
25
ns
SOUT Low Voltage
0.05
SOUT High Voltage
4
INTVCC
– 0.05
V
V
8310f
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LT8310
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOUT-to-GATE Delay (tPRE)
SOUT Falling to GATE Rising (Note 8)
l
190
240
300
ns
GATE-to-SOUT Delay (tPOST)
GATE Falling to SOUT Rising (Note 8)
l
0
12
25
ns
0.95
1.00
1.05
V
2.5
V
–60
–6
–50
–5
6
–40
–4
µA
µA
mA
Soft-Start
SS Active Switching Level (GATE Switches)
SS Frequency Foldback Complete
fOSC within Specified Limits
l
SS Pin Current (Note 8)
Soft-Up
Slow Wake
Hard-Down, VSS = 0.4V
l
l
SS Reset Threshold Voltage
0.27
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are relative to GND unless otherwise noted. All pin
currents are defined positive into the pin unless otherwise noted.
Note 3: Do not apply a positive or negative voltage or current source to the
GATE or SOUT pins, otherwise permanent damage may occur.
Note 4: The LT8310E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8310I is guaranteed over the full −40°C to 125°C operating junction
temperature range. The LT8310H is guaranteed over the full –40°C to
150°C operating junction temperature range. The LT8310MP is guaranteed
over the full –55°C to 150°C operating junction temperature range.
Operating lifetime is derated at junction temperatures greater than 125°C.
V
Note 5: The LT8310 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum junction temperature may impair device reliability.
Note 6: VSET = VINTVCC – VRDVIN.
Note 7: Line regulation in duty mode control applications is constrained
by the accuracy of the RDVIN pin input current, the duty mode control
gain, and the external set resistor, RSET. RSET should be specifiied to 1%
or better.
Note 8: See the Timing Diagrams section.
8310f
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5
LT8310
Typical Performance Characteristics
1.01
12.12
VSET = 1V
VSET = 2V
VSET = 1V
VSET = 0.5V
40
60
VIN (V)
80
20.0
0
19.9
–0.5
1.0
VSET = 1V
19.8
–1.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
8310 G02
8310 G03
Switching Frequency
vs Temperature
Switching Frequency and (Period)
vs Programming Resistance
12
500
10
8
300
6
200
4
UVLO Threshold vs Temperature
RT = 33.2k
100
2
0
0
120
1.29
303
1
300
0
297
1.30
2
1.28
1.27
ERROR (%)
400
306
fSW (kHz)
600
tSW (µs)
fSW (kHz)
0.5
11.76
–2
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
100
tSW
20.1
–1
VIN = 96V
VIN = 48V
VIN = 24V
8310 G01
fSW
1
VUVLO (V)
20
0
20.2
0
11.88
0.99
Duty Set Current vs Temperature
2
ERROR (%)
12.00
1.00
0.98
Duty • VIN Temperature Regulation
IRDVIN (µA)
12.24
DUTY • VIN (V)
1.02
ERROR (%)
DUTY • VIN/(12 • VSET) (V/V)
DUTY • VIN Line Regulation
(Normalized)
TA = 25°C, unless otherwise noted.
1.26
1.25
1.24
1.23
–1
RISING
1.22
FALLING
1.21
40
20
60
RT (kΩ)
80
100
8310 G04
7.0
UVLO FALLING
IUVLO (µA)
IUVLO (µA)
4
3
2
1
0
0
0.2
0.4
0.6 0.8 1.0
VUVLO (V)
1.2
1.4
1.6
8310 G07
6
OVLO Threshold Voltage
vs Temperature
UVLO Hysteresis Current
vs Temperature
5
–1
8310 G06
8310 G05
UVLO Hysteresis Current
vs UVLO Voltage
6
1.20
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.26
VUVLO = 1.15V
6.5
1.25
6.0
1.24
VOVLO (V)
0
294
–2
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
5.5
RISING
1.23
FALLING
5.0
1.22
4.5
1.21
4.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.20
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
8310 G08
8310 G09
8310f
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LT8310
Typical Performance Characteristics
INTVCC Voltage vs Temperature
and Load Current
127.5
2
125.0
0
122.5
10.4
2.4
SHUTDOWN
AT TJ ≈ 165°C
2.0
10.2
–2
10.0
9.8
9.6
LOAD = 1mA
LOAD = 10mA
LOAD = 20mA
INTVCC Current Limit
vs Temperature
INTVCC Current Limit
vs Input Voltage
36
50
20
40
60
VIN (V)
80
30
100
26
–75 –50 –25 0 25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (°C)
100
GATE, SOUT PINS
NOT SWITCHING
–0.816
1.616
–0.808
POSITIVE
1.600
–0.792
1.568
–0.784
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
8310 G15
SOUT Driver Transition Time
vs Capacitance
100
TIME (ns)
4.3
4.2
4.1
4.0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
tRISE
60
70
tFALL
50
40
50
30
20
10
10
5
15
10
CGATE (nF)
20
25
8310 G17
tRISE
40
20
0
tFALL
60
30
0
VIN = 48V
fSW = 100kHz
90
80
70
4.4
–0.800
NEGATIVE
80
4.5
24
1.632
VIN = 48V
fSW = 100kHz
90
4.6
IVIN (mA)
20
8310 G12
GATE Driver Transition Time
vs Capacitance
8310 G16
8
12
16
INTVCC LOAD (mA)
4
8310 G14
VIN Quiescent Current
vs Temperature
4.7
0
1.584
8310 G13
4.8
TA = –65°C
0
TIME (ns)
0
32
28
25
20
VIN = 12V
TJ ≈ TA + 15°C
POSITIVE VFBX (V)
–IINTVCC (mA)
–IINTVCC (mA)
30
TA = 25°C
0.8
FBX Regulation Voltage
vs Temperature
34
THERMALLY
SETTLED,
TA = 25°C
1.2
NEGATIVE VFBX (V)
INSTANTANEOUS
FROM OFF,
TA = TC = 25°C
35
TA = 125°C
8310 G11
8310 G10
40
1.6
0.4
9.4
–75 –50 –25 0 25 50 75 100 125 150 175
TA, AMBIENT TEMPERATURE (°C)
120.0
–4
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
45
INTVCC Dropout Voltage
vs Load Current, Temperature
DROPOUT VOLTAGE (V)
4
VINTVCC (V)
130.0
ERROR (%)
VSENSE (V)
SENSE Overcurrent Threshold
Voltage vs Temperature
TA = 25°C, unless otherwise noted.
0
0
1.5
4.5
3.0
CSOUT (nF)
6.0
7.5
8310 G18
8310f
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7
LT8310
Typical Performance Characteristics
Driver Nonoverlap Delays
vs Temperature
25
1.2
SOUT FALL TO GATE RISE
1.0
20
225
fSW/fSW(NOM) (kHz/kHz)
250
Switching Frequency (Normalized)
vs Soft-Start Voltage
Set Current vs Soft-Start Voltage
300
275
TA = 25°C, unless otherwise noted.
15
IRDVIN (µA)
tDLY (ns)
200
175
150
125
10
100
75
5
50
25
0
0
0.5
1.0
1.5
VSS (V)
2.0
2.5
0.2
3.0
–0.2
0
0.5
1.0
1.5
VSS (V)
2.0
2.5
3.0
8310 G21
Output Voltage Transient
Response (Typical Applications,
Pages 1 and 31)
GATE Duty Cycle (Normalized)
vs Soft-Start Voltage
100kHz
300kHz
500kHz
1.0
DUTY/DUTY (NORM) (%/%)
0.4
8310 G20
8310 G19
1.2
0.6
0
GATE FALL TO SOUT RISE
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0.8
0.8
VOUT
1V/DIV
0.6
0.4
1ms/DIV
VIN = 48V
IOUT = 4.5A TO 6.5A TO 4.5A
0.2
8310 G23
0
–0.2
0
0.5
1.0
1.5
VSS (V)
2.0
2.5
3.0
8310 G22
8
8310f
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LT8310
Pin Functions
UVLO (Pin 1): System Undervoltage Lockout Input.
Program the system falling UVLO threshold (minimum
VIN voltage) with a resistive voltage divider from VIN to
this pin. The pin voltage is compared internally to an accurate 1.22V threshold. Program the system rising UVLO
hysteresis via this pin’s 5.7µA hysteretic current and the
values of the external resistors. The device is shut down
below the UVLO threshold and draws 1µA or less from VIN
when VUVLO ≤ 0.36V (min). The UVLO pin can withstand
100V maximum.
OVLO (Pin 3): System Overvoltage Lockout Input. Program
the system rising OVLO threshold (maximum VIN voltage)
with a resistive voltage divider from VIN to this pin. The
pin voltage is compared internally to an accurate 1.25V
threshold. Exceeding the OVLO threshold sets the fault
latch and forces a system shutdown.
DFILT (Pin 5): Duty Cycle Loop Filter Pin. Set the duty
cycle loop filter pole by connecting a capacitor to GND
from this pin in both duty mode and current mode applications. Consult the Applications Information section
to choose the capacitor value to reduce load step ringing
in duty mode control applications. Do not float this pin, a
capacitor is required.
RT (Pin 6): Switching Period Set Input. Set the oscillator
switching period (frequency) via a resistor to GND from
this pin, typically 20k to 100k for 2µs to 10µs (500kHz to
100kHz). In applications where an external clock drives the
SYNC pin, program the switching period to the expected
SYNC frequency value. Place the resistor close to the pin
and minimize stray capacitance. Do not leave the RT pin
open.
SYNC (Pin 7): External Clock Input. Drive this pin with
an external fixed-frequency clock signal to synchronize
switching to it. The SYNC falling edge is automatically
detected and converted to a pulse that starts the minimum
off-time of the duty cycle. The SYNC pulse low and highs
times must both be ≥250ns. Select an RT resistor that
programs the internal switch frequency to the external
SYNC frequency to keep the maximum duty cycle limit
accurate. When VSS < 1V, the SYNC pin is ignored.
SS (Pin 8): Soft-Start Input. Program start and hiccup
timing by tying an external capacitor between SS and GND.
During normal soft-start this pin sources 50µA. During
faults and initial start, a 6mA (typ) current sink discharges
this pin to 0.27V (typ). The GATE pin is shut off until VSS
≥ 1V. After an overcurrent shutdown, the pin sources only
5µA until VSS ≥ 1V, which provides an extended wake-up
period that reduces power dissipation during repeated
start-up retries (hiccup mode). Switching frequency and
duty cycle are folded back until SS > 2.5V. Above 1V, the
pin sources 50µA until charged to an internal 3V clamp.
VC (Pin 9): Transconductance Error Amp Output. Compensate the converter loop at this pin with an external series
resistor and capacitor to GND in feedback applications.
In opto-isolated feedback applications, compensation is
generally done on the secondary side (see the Applications Information section). In duty mode control applications that have no output voltage feedback, leave this pin
unconnected.
FBX (Pin 10): Feedback Input and Mode Control. Standard
input for nonisolated applications that require voltage
feedback. Program output voltage with a resistive voltage
divider to compare to the internal 1.6V reference for positive
output applications, or to the –0.8V reference for negative
output applications. When –0.2V < VFBX < 0.3V, duty mode
controls the GATE pin, otherwise FBX is assumed to be
in control. FBX exceeding its reference by 7.5% ends the
switching cycle in progress without triggering a system
reset. Tie FBX to GND if duty mode only is desired.
SOUT (Pin 11): Synchronization Output. Pulse transformer
driver for applications with synchronous secondary-side
control, complementary to GATE. The SOUT falling edge
leads GATE turn-on by 240ns (typ), and the rising edge
trails GATE turn off by 12ns (typ). Actively pulled to INTVCC
during shutdown.
NC (Pin 12): No Internal Connection. Connect to GND.
8310f
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9
LT8310
Pin Functions
SENSE (Pin 13): Switch Current Sense Input. Positive
input of the low side current sense to the control loops
and the overcurrent comparator. Kelvin-connect this pin to
the sense resistor at the source of the N-channel MOSFET
switch. Exceeding 125mV at this pin triggers an overcurrent fault, and sends the system into fast shutdown, slow
wake-up, and soft-start.
GATE (Pin 14): Switch Control Output. Low side switch
drive (GND to INTVCC) for external N-channel MOSFET. The
maximum duty cycle is limited to 78% (typ) because resonant reset forward converters require time for transformer
flux to reset. Actively pulled to GND during shutdown.
INTVCC (Pin 15): Regulated Supply Output. A 10V LDO
supply generated from VIN and capable of supplying the
GATE pin. Must be bypassed with a 4.7µF capacitor or
higher. The regulator voltage can be externally driven up
to 17V, as long as VIN ≥ VINTVCC, to reduce internal power
dissipation from VIN or to accommodate more than 10V
gate drive for high voltage N-channel MOSFETs.
Resistor value accuracy contributes directly to the output
voltage accuracy, choose appropriate tolerance. In current
mode applications, feedback sets VOUT, therefore program
RSET to set a maximum duty cycle guardrail that constrains
the volt-seconds of flux in the transformer during transients.
This pin must be connected to INTVCC by a resistor.
VIN (Pin 18): Supply Input and System Input Voltage
Sense. Input supply for the part; operational from 6V to
100V. Accurate duty cycle requires accurate sensing of
the VIN voltage, so keep the connection to the transformer
primary short to minimize resistive voltage drops. Bypass
to GND with 1µF.
NC (Pin 20): No Internal Connection. Connect to VIN.
GND (Exposed Pad Pin 21): Ground. This pin also senses
the negative terminal of the current sense resistor. Solder
the exposed pad directly to the ground plane.
RDVIN (Pin 16): Duty Cycle Control Input. This pin sinks
a precise 20µA in normal operation, but less during softstart, when the duty cycle is folded back. Connect a resistor
RSET between the INTVCC and RDVIN pins to program the
desired (no opto) application output voltage:
RSET
10
⎛ VOUT ⎞
⎛ N ⎞ ⎜⎝ 12 ⎟⎠
=⎜ P ⎟•
⎝ NS ⎠ 20µA
8310f
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NC
CSS
RT
CDFILT
R1
R2
10
9
8
7
6
5
3
1
50µA
FBX
VC
SS
–
200k
3V
HICCUP
LOGIC
SYNC
RT
DFILT
OVLO
UVLO
–0.8V
FBX
1.6V
FAULT
5µA
3V
+
–
+
–
1V
IREF
FBX
15µA
INTVCC
SS
CLAMPS
VC
SS LOW
+
+
CLK
+
0.3V
+
+
SYS UV
SYS OV
SYS OT
REG UV
REG OV
ISW MAX
FBX OV
RST PCM
RST DUTY
R
PCM LATCH
S Q
S
DUTY LATCH
R Q
FB MODE
SS LOW
17.4V
FALLING HYST
–0.65V
+
–0.2V
REG OV
INTVCC
REG UV
RISING HYST
0.45V
+ 4.75V
DUTY
1
FB MODE
SS LOW
FB MODE
PCM
0
1.72V
+
+
ISW MAX
PWM
CONTROL
LOGIC
gm = 25µA/V
+
–
+
–
gm = 25µA/V
–0.86V
SNS
ISUP
IREF
VIN
+
A=5
125mV
SOUT DRIVER
GATE DRIVER
÷ 12
DUTY CYCLE
FOLDBACK
20µA NOM.
SS
13
11
14
16
FBX OV
8310 F01
RSET
15
18
GND
EXPOSED 21
PAD
SENSE
SOUT
GATE
0µA
TO 20µA
RDVIN
INTVCC
10V
VIN
Figure 1. LT8310 Block Diagram Configured as a Nonsynchronous Duty Mode Converter
gm = 250µA/V
S
FAULT LATCH
Q R
+
+
SLOPE COMP
RAMP GENERATOR
SLOPE
COMP
100kHz TO 500kHz
CLOCK PULSE
OSCILLATOR
DUTY RAMP
DUTY LOOP
RAMP GENERATOR
SYS OT
SYS OV
SYS UV
0.27V
0.25V TO 1V
SS
HICCUP
+
–
TIM
165°C
1
1
1V NOM.
FREQUENCY
FOLDBACK
+
1.25V
5.7µA
1.22V
+
R3
VIN
+
–
VIN
CIN
NC
M1
+
VSET
–
CREG
C2
•
RSENSE
•
T1
NP:NS
CRST
D1
D2
L1
CL
VOUT
LT8310
Block Diagram
8310f
11
LT8310
Timing Diagrams
Start-Up/ Soft-Start / Fault / Shutdown / Restart
VIN
START UP
VUVLO
RISING ~ 1.26V
VINTVCC
FALLING 1.22V
SHUT DOWN
REGULATOR CAPACITOR
DISSIPATING
5.2V
FAST DOWN
SOFT-START
VSS
1V
1V
0.27V
VGATE
SLOW WAKE
•••
OVERCURRENT
VSENSE
•••
125mV
125mV
•••
tSS
•••
NOT TO SCALE
tHICCUP
8310 TD01
Nonoverlapping GATE/SOUT
tPOST
VSOUT
VGATE
8310 TD02
tPRE
D • tSW
(1 – D) • tSW
tSW
12
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LT8310
Operation
Introduction
The LT8310 is a constant-frequency forward converter
controller with a low side N-channel MOSFET gate driver
and low side switch current sensing that offers two operating modes: duty mode control and peak current mode
control. Duty mode control that requires no output voltage
feedback is targeted for (but not limited to) isolated duty
mode control applications, to which it brings a simple
schematic, low parts count, and only one isolation element,
a transformer. In current mode control applications, feedback determines the output voltage, but the duty control
loop enforces a programmable relative maximum duty
cycle that clamps the volt-seconds of core flux to avoid
transformer saturation during transients. At all times the
LT8310 also enforces an absolute maximum duty cycle
that provides time to reset the core each switching period.
With a patent pending architecture, the LT8310’s duty
control loop imposes volt-second accuracy over the span
of input voltage that translates into both accurate output
voltage without feedback and protection from transformer
saturation.
Duty Mode Control
The duty mode control loop compels a PWM duty cycle
that is inversely proportional to the system input voltage,
D(VIN) ∝ 1/VIN, which is the correct function for a buck
(or buck derived) converter to generate a constant output
regardless of the line input. For a given scaling constant KD,
D(VIN ) =
KD [ V ]
VIN
[1]
In a forward converter with transformer turns ration NP/NS,
VOUT =
D(VIN ) • VIN
KD
=
NP / NS
NP / NS
[2]
In the discussion that follows it will be helpful to refer to
the Block Diagram in Figure 1. Duty mode control governs
operation when the feedback pin (FBX) is tied to GND. It
serves as an accurate volt-second clamp when current
mode control governs operation because feedback is
present. The system clock starts the PWM duty cycle by
driving the GATE pin high to close the external MOSFET
switch and initiating a timing ramp in the duty loop ramp
generator. While GATE is high, current proportional to VIN
discharges a capacitor (CDFILT) between the DFILT pin and
GND; when GATE is pulled low, a fixed current charges
it. The duty cycle ends when the ramp voltage plus some
switch current feedback exceeds the DFILT voltage, at
which point GATE falls and shuts off the primary-side
switch until the start of the next period.
The condition of the main switch (on or off, as indicated
by GATE pin voltage) controls the sourcing and sinking
of current at the DFILT pin. The voltage imposed between
the INTVCC and RDVIN pins, VSET, establishes an internal reference current (IREF). During the switch on-time,
D • tSW, a current proportional to the system input voltage
VIN (which is sensed at the VIN supply pin) is subtracted
from the reference current and driven at DFILT. During the
switch off-time, (1-D) • tSW, only the reference current is
driven. The external capacitor to GND at DFILT (CDFILT)
integrates the current. In steady-state operation with sufficient load, the feedback loop forces the net cycle current
to zero, which produces a duty cycle inversely proportional
to VIN (Equation 3), and ultimately a constant output voltage
(Equation 4). An external resistor (RSET) between INTVCC
and RDVIN and a precise 20µA sink at RDVIN program
VSET and thus, VOUT.
D=
12 • VSET
VIN
VOUT =
12 • VSET
NP / NS
[3]
[4]
8310f
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13
LT8310
Operation
With no output voltage feedback, the secondary-side LC
filter might freely ring (depending on load resistance and
parasitics) in response to load current steps; the primaryside switch current that feeds into the duty mode control
loop limits the ringing. During the switch on-time, inductor current translates to switch current that is scaled and
added to the timing ramp. Constant current is absorbed
into the DC level of the DFILT voltage, which does not affect duty cycle, but changing current dynamically adjusts
the duty cycle to dampen the ringing. The DFILT capacitor
is chosen with respect to the output LC time constant
(√L1•CL) to track out the oscillation. The selection of this
capacitor is discussed in the section, Compensating the
Duty Mode Control Loop.
Several system operation and protection features are exclusive to current mode control. When the load is light, automatic pulse skipping allows the effective switching period
to extend, which lowers the duty cycle without necessitating
impractically narrow GATE pulses. If FBX pin overvoltage
is detected during a cycle, the duty cycle ends, GATE falls,
and the switch turns off, which allows the output voltage
to coast down. When current mode control governs operation, the duty loop circuitry acts as a relative maximum duty
cycle clamp that protects the transformer from developing
excessive volt-seconds of flux during transients and it limits
the output voltage. This feature also allows the system to
revert to duty mode control if FBX is grounded. The duty
cycle clamp margin is user-programmable.
Duty mode control operation requires a minimum load in
steady-state to balance the sum of the transformer magnetization current and output inductor ripple current, see
the section, Minimum Load Requirements.
Common Operation and Protection Features
Current Mode Control
To serve applications that require tighter output voltage
regulation and faster load response, the LT8310 offers
standard constant-frequency peak current mode control
when output voltage feedback (opto-isolated or nonisolated) is connected. The system clock starts the PWM duty
cycle by driving the GATE pin high to close the external
MOSFET switch. The switch current flows through the
external current sensing resistor RSENSE and generates
a voltage proportional to the switch current. The current
sense voltage is amplified and added to a stabilizing slope
compensation ramp. When the resulting sum exceeds the
control pin (VC) voltage, the duty cycle ends, and the main
switch is opened. The VC pin level is set by the error amplifier, which amplifies the difference between the reference
voltage (1.6V or –0.8V, depending on the configuration)
and the feedback pin (FBX) voltage. In this manner, the
error amplifier sets the correct peak switch current level
to keep the output in regulation.
14
A programmable soft-start pin (SS) controls the power-up
time and folds back the switching frequency and the duty
cycle during start-up to protect the transformer and to
limit inrush current. A minimum on-time of 190ns (typ)
ensures that the MOSFET switch has enough time to turn
on reliably, and a maximum duty cycle of 78% guarantees
time for core reset each cycle. The SYNC pin allows an
external pulse signal to override the LT8310’s oscillator
and set the switching period. The SOUT pin supplies a
non-overlapping signal complementary to the GATE that
may be used for synchronous converter applications. The
SOUT pin driver has about 40% of the GATE pin’s drive
strength, and may be used to drive a pulse transformer
(isolated) for forced continuous mode (FCM) operation.
Other protection mechanisms end the normal switching
cycle or force system shutdown to protect the application circuit. The minimum and maximum VIN operating
thresholds are programmed at the UVLO and OVLO pins,
respectively. Input voltages outside of the set limits shut
down the system. Shutdown also occurs when the INTVCC
regulator voltage goes above or below its operating range,
and when the die temperature exceeds 165°C. The switch
8310f
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LT8310
Operation
overcurrent limit threshold is programmed at the SENSE
pin. If the maximum current limit is reached, a fault latch
is set and the system shuts down. Upon restart the system
will operate in hiccup mode, which extends the soft-start
time and thus reduces average power dissipated in the
MOSFET during repeated retries.
NP:NS
VIN
T1
•
CAT
L1
•
FWD
D1
CL
D2
SW
M1
GATE
Forward Converter Basics
A forward converter is a buck-derived topology that
comprises a transformer, a primary-side PWM-controlled
switch, secondary-side switches, an inductor, and a capacitor, as shown in Figure 3. The secondary-side switches may
be nonsynchronous (diodes), synchronous (MOSFETs), or
a combination thereof. The transformer provides galvanic
isolation for isolated applications.
VOUT
IL1
IOUT
LOAD
8310 F02
CRST
Figure 3. Forward Converter Architecture (Nonsynchronous)
Refer to Figure 2 in the following discussion of signals
in a forward converter. When the GATE signal goes high,
the primary winding sees the full input voltage, and the
secondary winding voltage has a value scaled by the turns
ratio, VIN /(NP/NS). During this period the forward diode
VGATE
VSW(PK)
VSW(MAX)
VIN
VSW
VSW(PK)
NP /NS
VFWD
tRST
VIN
NP /NS
VCAT
IL1
IOUT
0A
CORE FLUX
TIME
(1 – D) • tSW
D • tSW
8310 F03
tSW
Figure 2. Typical Signals in a Forward Converter
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15
LT8310
Operation
D1 conducts, which imposes VIN /(NP/NS) – VOUT across
inductor L1 (ignoring voltage drop across the diode), for
the switch on-time, D • tSW. When the GATE signal goes
low, the switch turns off, and the primary winding voltage collapses as the primary current charges the reset
resistor CRST. The switch node voltage (VSW) resonates
past VIN, which takes the primary winding voltage negative. The secondary winding voltage also goes negative,
forward diode D1 turns off, and the inductor current
flows through the catch diode, D2, which imposes –VOUT
(again ignoring diode drop) across inductor L1 for the
switch off-time, (1 – D) • tSW. The output voltage may
be calculated by considering the volt-second balance in
the inductor under steady-state conditions (Equation 5),
and then solving for VOUT. Equation 6 makes it clear that
forcing the duty cycle to be inversely proportional to the
input voltage would create a constant output voltage as
desired.
⎛ V
⎞
⎜ IN − VOUT ⎟ • D • TSW +(−VOUT ) • (1−D) • TSW = 0
⎝ NP / NS
⎠
VOUT =
16
D • VIN
NP / NS
To keep the transformer from saturating, its core flux must
be reset periodically. The LT8310 relies on resonant reset
each cycle uses a capacitor between the switch node,
SW, and ground (see Figure 2). When the main switch
turns off at the end of the duty cycle, VSW ramps up to
and beyond VIN, which cuts off secondary-side current
and forces primary-side current to charge the switching
node. Node SW resonates for half a sine wave until the
transformer voltage and current are both zero, which
leaves VSW = VIN until the next switch activation. Note that
(1) the maximum voltage on the primary switch exceeds
the input voltage, and may be well above it, and (2) ideally,
the flux reset completes within the switch off-time before
the next cycle begins. The LT8310 controller imposes an
absolute maximum duty cycle that provides a predictable
minimum off-time (at a given switching frequency) in
which to reset the core.
[5]
[6]
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LT8310
Applications Information
INTVCC Regulator Bypassing and Operation
The GATE and SOUT pin drivers and other chip loads
are powered from the INTVCC pin, which is an internally
regulated supply. The internal low dropout regulator requires a capacitor from the INTVCC pin to GND for stable
operation and to store the charge for the large GATE and
SOUT switching currents; a 4.7μF capacitor is adequate
for most applications. Choose a 16V rated low ESR, X7R
ceramic capacitor for best performance. Place the capacitor close to the LT8310 to minimize the trace length both
to the INTVCC pin and to the chip ground. In shutdown,
the INTVCC pin sinks 125μA (typical) until the pin voltage
falls below 4.75V.
An internal current limit on the INTVCC output protects
the LT8310 from excessive on-chip power dissipation.
The minimum specified current limit should be considered when choosing the switching N-channel MOSFET
and the operating frequency. Careful selection of a lower
QG MOSFET allows higher GATE switching frequencies,
which leads to smaller magnetics. SOUT switching current
must be accounted for when that pin drives a MOSFET
gate, but in typical applications where SOUT is unused or
drives an AC-coupled pulse transformer, GATE switching
dominates the steady-state regulator load and the SOUT
current may be ignored. The MOSFET gate drive switching
current required may be calculated using Equation 7, see
the Thermal Considerations section for further information.
IDRIVE = QG • fSW [7]
The INTVCC voltage tracks a few hundred millivolts below
the supply voltage until the regulation loop closes when
VIN exceeds about 10.5V. The INTVCC pin has its own
undervoltage disable set to 4.75V (typical) that protects
the external MOSFET from excessive power dissipation
caused by not being fully enhanced. If the INTVCC pin
drops below its undervoltage threshold, the GATE pin will
be forced to GND, the SOUT pin will follow the INTVCC
voltage, and the soft-start pin will be reset.
The regulator may be overdriven from external circuitry to
reduce switching power dissipation in the LT8310 package,
or to drive a MOSFET switch with a high threshold. The
overdriven INTVCC pin voltage must be less than the IC
supply to avoid back-driving the VIN pin. The INTVCC pin
has its own overvoltage threshold set to 17.4V (typical) that
disables the system to protect MOSFETs rated for VGS(MAX)
= 20V, a common specification. As with undervoltage
shutdown, the GATE pin will be forced to GND, the SOUT
pin will follow the INTVCC voltage, and the soft-start pin
will be reset. A 4.7μF 25V rated low ESR, X7R capacitor
is recommended when INTVCC is overdriven.
Programming the System Turn-On and Turn-Off
Thresholds
The system undervoltage and overvoltage thresholds are
programmed by a resistive voltage divider from VIN to
UVLO and OVLO, respectively (Figure 4). The falling UVLO
threshold,1.22V (nom), accurately sets the minimum operating VIN (Equation 8), below which the system goes into
low power mode. A 5.7μA (typical) pull-down current that
is active when the UVLO pin is below its falling threshold
provides rising hysteresis that sets the minimum startup VIN (Equation 9). The built-in comparator hysteresis
contributes a small amount to the rising threshold as well.
⎛ R3+R2+R1⎞
VIN(UVLO FALLING) = 1.22V • ⎜
⎟
⎝ R2+R1 ⎠
[8]
VIN(UVLO RISING) = VIN(UVLO FALLING) + 5.7µA • R3
⎛ R3 + R2 + R1⎞
+ 40mV • ⎜
⎝ R2 + R1 ⎟⎠
[9]
The rising OVLO threshold, 1.25V (nom), accurately sets
the maximum operating VIN (Equation 10), above which
the system stops switching and awaits soft-start. The
built-in comparator hysteresis provides falling hysteresis
that sets the maximum restart VIN (Equation 11).
VIN
VIN
R3
LT8310
UVLO
R2
OVLO
R1
GND
8310 F04
Figure 4. Resistor Connections for System UVLO
and OVLO Threshold Programming
8310f
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17
LT8310
Applications Information
⎛ R3+R2+R1⎞
V IN(OVLO RISING) = 1.25V • ⎜
⎟
⎝
⎠
R1
[10]
[11]
Selecting the resistor values best proceeds as follows:
1. Choose VIN(UVLO FALLING) and VIN(OVLO RISING) for the
system
2. Choose a rising hysteresis voltage, VHYST(UVLO RISING),
and calculate R3 = VHYST(UVLO RISING) /5.7µA
4. Calculate R1 from Equation 10, which then determines
R2, and
5. Recheck the thresholds using actual resistor values.
NP 0.75 • V IN(MIN)
<
NS
VOUT(TARG)
Programming the Duty Cycle Loop Output Voltage Target
In all applications, the LT8310 duty mode control loop
must have a programmed output voltage target,
VOUT(TARG), that is the value the converter would produce,
without output voltage feedback, using ideal components.
For the forward converter, this is characterized by Equation
6 (here recast with the target output).
T1
NP:NS
•
+VOUT
•
D2
GATE
RDVIN
SENSE
CL
–VOUT
CRST
INTVCC
L1
D1
CREG
[13]
After fixing the turns ratio, consider the duty cycle. In general, the highest operating duty cycle should be maximized
to best utilize the MOSFET each switching period, and to
reduce the effect of switching losses each in cycle. The
+VIN
LT8310
[12]
First consider the transformer turns ratio in the core
schematic in Figure 5. Since duty mode control forces the
duty cycle to be inversely proportional the input voltage,
the largest duty cycle occurs at the lowest operating input
voltage. For a given target output voltage and minimum
input voltage, the LT8310’s maximum duty cycle limit,
75% (min), constrains the turns ratio per Equation 13.
3. Calculate the sum of R2 + R1 from Equation 8
VIN
D • V IN
NP / NS
This is accomplished by setting the scaling factor (KD)
of the duty cycle versus VIN function and choosing the
transformer turns ratio (NP/NS). In applications without
output voltage feedback, the target voltage minus any
voltage drops (e.g., diode thresholds, ohmic losses) yields
the nominal output voltage, VOUT. In applications using
an opto-coupler, the target is used as an upper guard rail
level to the nominal output voltage that is set by feedback,
and it is a measure of the relative duty cycle clamp margin.
VIN(OVLO FALLING) = V IN(OVLO RISING)
⎛ R3 + R2 + R1⎞
− 33mV • ⎜
⎟⎠
⎝
R1
VOUT(TARG) =
M1
RSET
RSENSE
DFILT
CFLT
–VIN
GND
VC
FBX
NC
8310 F05
Figure 5. Forward Nonsynchronous Converter Core Schematic
18
8310f
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LT8310
Applications Information
duty cycle should be checked for feasibility and margin
over the full VIN operating range. The minimum input voltage produces the maximum duty cycle, which must not
exceed the LT8310’s minimum-specified maximum duty
cycle limit (75%). The maximum input voltage produces
the minimum duty cycle, which must be greater than duty
cycle of the minimum GATE pulse width, fSW • tON(MIN),
as in Equation 14.
fSW • tON(MIN) <
VOUT(TARG) NP
•
< 0.75
VIN
NS
[14]
Finally, the duty cycle scaling must be programmed. As
discussed in the latter part of the section, Duty Mode
Control, the voltage difference between the INTVCC and
RDVIN pins, VSET, and an accurate internal gain of 12V/V
sets the duty mode loop scaling constant, KD. The RDVIN
pin sinks a precise 20µA that permits a single resistor,
RSET, to program the voltage difference.
12V
12V
KD =
• VSET =
• (20µA • RSET )
V
V
Programming the Switching Frequency
The RT frequency adjust pin allows the user to program the
switching frequency from 100kHz to 500kHz to optimize
efficiency and performance or external component size.
Higher frequency operation yields smaller component
size, but increases switching losses and gate driving
current, and may not allow sufficiently high or low duty
cycle operation. It also decreases magnetization current,
which reduces the minimum load requirement under duty
cycle mode control. Lower frequency operation gives better performance at the cost of larger external component
size. Table 1 shows the RT values for several frequencies
that match the design equation, Equation 17.
Table 1. Resistor Selection Guidance for Some Common
Switching Frequencies
FREQUENCY (fSW)
(kHz)
PERIOD (tSW)
(µs)
CLOSEST 1% RESISTOR (RT)
(kΩ)
100
10.0
100
150
6.67
66.5
200
5.00
49.9
250
4.00
40.2
300
3.33
33.2
350
2.86
28.7
400
2.50
24.9
450
2.22
22.1
500
2.00
20.0
[15]
Resistor RSET may be chosen to achieve the desired
VOUT(TARG) based on Equation 16.
RSET
VOUT(TARG) NP
•
12V / V NS
=
20µA
[16]
The tolerance of the set resistor contributes directly to the
accuracy of the target output voltage, which is especially
important to the accuracy of converters operating without
output voltage feedback, so always use a 1% or better
resistor. Keep RSET close to the RDVIN and INTVCC pins of
the chip to minimize trace length and avoid cross-coupling
with other signals.
During soft-start, the RDVIN sinking current is reduced
to fold back the duty cycle while the clock frequency is
also reduced. This protects the transformer by limiting
the volt-seconds of flux generated when the clock period
is made longer. Take care to consider the flux conditions
during soft-start if external currents are employed for
trimming or margining.
RT =
t
1000kHz
• 10k = SW • 10k
fSW
1µs
[17]
Minimize stray-coupling to the adjacent DFILT and SYNC
pins by keeping the traces short. An external resistor from
the RT pin to GND is required—do not leave this pin open.
Programming the Current Sense
The LT8310 features primary-side switch current sensing
that protects the system from excessive load current, damps
output ringing when duty mode control dominates, and
sets the duty cycle when current mode control dominates.
When VSENSE exceeds 125mV (nom), the maximum switch
current threshold, the system shuts down and attempts
a restart after a slow wake-up period (see Programming
the Soft-Start Interval and Hiccup Period). In converter
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LT8310
Applications Information
applications operating without output voltage feedback,
current sense information is fed back to the duty cycle loop
to reduce output voltage ringing due to load current steps
that excite the output LC tank. In supply applications, each
cycle ends when the amplified SENSE voltage exceeds the
VC pin control level. In all cases, during the cycle on-time,
the switch sees the rippling inductor current (IL1), scaled
by the transformer turns ratio (Equation 18) plus the
transformer’s primary magnetizing current, Iµ,p. Applying
VIN across the magnetizing inductance generates a peak
magnetizing current of approximately 12 • VSET • tSW/Lµ,p.
ISWITCH =
IL1
+ Iµ,p
NP / NS
[18]
Resistor RSENSE connected between the SENSE and GND
pins converts the switch current to a voltage. It should be
selected to provide the maximum switch current required
by the application, including inductor ripple current, without
exceeding the SENSE pin’s overcurrent threshold. A good
rule of thumb is to allow 10% margin on the minimum
overcurrent threshold of 115mV.
During steady-state operation, the average inductor current
equals the load current. In applications under duty mode
control, which require a minimum load, less inductor ripple
means a lower minimum load current, so peak inductor
current might be 10% or less above the maximum load
current. Output voltage ring damping operates best with a
strong average current signal, so RSENSE should be chosen
as large as allowed by the SENSE pin threshold. Equation
19 provides a good value for RSENSE that accounts for the
minimum SENSE threshold:
RSENSE ≤
115mV
1.1• ISWITCH(MAX)
[19]
In applications with output voltage feedback, current mode
control is most agile with a steep slope to the ripple, so
peak inductor current might be 20% or more above the
average load current. Equation 20 provides a good value for
RSENSE that accounts for the minimum SENSE threshold:
RSENSE ≤
20
115mV
1.4 • ISWITCH(MAX)
[20]
It is always prudent to verify the peak inductor current
in the application to ensure the sense resistor selection
provides margin to the SENSE overcurrent limit threshold.
The placement of RSENSE should be close to the source
of the N-channel MOSFET and GND of the LT8310. The
SENSE input to LT8310 should be a Kelvin connection to
the positive terminal of RSENSE. Verify the power in the
resistor to ensure that it does not exceed its rated maximum.
Programming the Soft-Start Interval and Hiccup
Period
The built-in soft-start circuit significantly reduces the inrush
current spike and output voltage overshoot at start-up.
Please refer to Figure 6 and the Timing Diagrams section
for the following discussion of soft-start behavior. The
soft-start interval is programmed by a capacitor connected
from the SS pin to GND. In a normal start-up, after the
INTVCC voltage exceeds its rising threshold of about
5.2V, the SS pin sources 50µA (typical), which ramps the
capacitor voltage. Switching commences when the 1.00V
switching threshold is exceeded (EN_GATE high).
Assuming the SS pin starts fully discharged, the soft-start
time, tSS, may be programmed by choosing CSS using
Equation 21. A 100nF soft-start capacitor produces about
2ms of delay, which suits many applications.
CSS = 50nF •
tSS [ms]
1ms
[21]
The SS pin voltage is discharged when the fault latch is
set under any of the following conditions: the UVLO pin
voltage falls below its threshold (SYS_UV high), the OVLO
pin voltage exceeds its threshold (SYS_OV high), the die
temperature exceeds 165°C (SYS_OT high), the INTVCC
voltage falls below or rises above its operating range
(REG_UV or REG_OV high), or the SENSE pin voltage
exceeds its maximum threshold because the switch current
is too large (ISW_MAX high). When the fault condition
ceases and VSS < 0.27V, the fault latch clears, which brings
about restart as SS rises through the 1V threshold.
Exceeding maximum switch current sets the hiccup latch,
which extends the soft-start time by reducing the pull-up
current to 5µA (typical). After the fault latch is reset, the
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HICCUP
3V
50µA
8
HICCUP
LATCH
ISW_MAX
3V
S Q
R
5µA
SS
SYS_UV
FAULT
LATCH
SYS UV
SYS OV
SYS OT
REG UV
REG OV
ISW MAX
CSS
0.25V
+
S Q
R
FAULT_RST
FAULT
1V
+
SS_LOW
EN_GATE
8310 F06
Figure 6. Soft-Start Control Logic
slow wake-up time keeps the retry rate low during overcurrent conditions to reduce power dissipation. Hiccup
mode ends and the hiccup latch clears when VSS exceeds
1.00V, after which the pull-up current reverts to 50µA. For
practical purposes, the hiccup interval is approximately 8
times the soft-start time (Equation 22).
while the output inductance and capacitance, L1 and CL,
define the output resonance time constant.
tHICCUP ≈ 8 • tSS
Compensating the Duty Mode Control Loop
In applications without output voltage feedback, little to
no output voltage ringing is the desired response; in current mode applications that have output voltage feedback
(isolated or not), this programming ensures controlled
operation if the output feedback fails.
For best results, the duty mode control loop compensation
should be programmed in relation to the LC tank resonance
of the output filter to best attenuate output voltage ringing
due to load current steps in duty mode control applications,
and to best provide the volt-second guardrail in supply
converters. The duty control transconductance, nominally
gm(DFILT) = 25µA/V, and the external compensation capacitance, CDFILT, define the duty control loop time constant,
τDFILT =
CDFILT
g m(DFILT)
τLC = L1•CL
[23]
[24]
The output ringing is decently damped when the loop time
constant is approximately twice the transformer ratio times
the LC resonance, as in Equation 25. For more damping
and a slower response, increase CDFILT, for less damping
and a faster response, decrease CDFILT.
NP
µA
• 25 • L1•CL
[25]
N
V
S
In rare applications where a very fast duty loop response
is more advantageous than output voltage ring reduction
(e.g., sharp input voltage steps occur more regularly than
sharp load current steps), the compensation capacitor may
be chosen small for faster loop speed, independent of the
LC tank’s natural period.
CDFILT = 2 •
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LT8310
Applications Information
A practical approach to design the compensation network
is to start with the typical CC = 4.7nF and RZ = 20k, calculate an new RZ when all the component values in Equation
26 are available, then tune the compensation network to
optimize the performance. Stability should be checked
across all operating conditions, including load current,
input voltage and temperature.
Compensating the Direct-Wired Current Mode
Control Loop
When output voltage feedback is directly wired to the FBX
pin, the LT8310 uses current mode control to regulate the
output. To compensate the current mode feedback loop of
the LT8310, a series resistor-capacitor network is usually
connected from the VC pin to GND (Figure 7).
Minimum Load Requirements
For most applications, a capacitor (CC) in the range of 1nF
to 22nF is suitable, with 4.7nF being typical. The resistor
(RZ) should fall in the range of 10k to 50k, with 20k being
typical. An estimate for RZ based on the output voltage,
the output capacitance (CL), the compensation capacitance
(CC), the sense resistor (RSENSE), the turns ratio (NP/NS),
and the absolute value of the feedback reference (|VREF |
= 1.6V or 0.8V) is:
RZ = RSENSE • 100k •
In standard current mode converters, the controller senses
rising output voltage and activates pulse-skipping mode
that reduces the power delivered to the load as the output
current demand decreases, until there is no load and the
main switch is turned off. With no output voltage sensing
to command pulse skipping and a VIN-based control loop
that operates continuously, LT8310 nonsynchronous duty
mode control applications require a minimum load in steady
state operation to dissipate transformer magnetization and
inductor ripple currents. Failure to provide the minimum
load current results in an increased steady-state output
voltage, which peaks at VIN /(NP/NS) when IOUT = 0A.
CL (NP / NS ) • VOUT
•
[26]
CC
VREF
A small capacitor is sometimes connected in parallel with
the RC compensation network to attenuate the VC voltage
ripple induced from the output voltage ripple through
the internal error amplifier. The parallel capacitor usually
ranges in value from 10pF to 100pF.
In Equation 27, given an output voltage (VOUT), the minimum load current is expressed as a function of (1) the
T1
NP:NS
+VIN
•
VIN
L1
+VOUT
•
R6
D1
LT8310
CREG
D2
–VOUT
CRST
INTVCC
GATE
RDVIN
SENSE
CL
R5
M1
RSET
RSENSE
DFILT
CFLT
GND
FBX
VC
RZ
–VIN
8310 F07
CC
Figure 7. Forward Nonsynchronous Direct-Wired Nonisolated Basic Schematic
22
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switching frequency (fSW), (2) the transformer’s primary
magnetizing inductance (Lµ) as seen on the secondaryside through the turns ratio (NP/NS), and (3) the ripple
current in the inductor (L1) during the off-time portion of
the duty cycle (1 – DMIN).
V
IOUT(MIN)= OUT
2 • fSW
⎛ (N / N )2 (1− D ) ⎞
MIN
•⎜ P S +
⎟
⎜⎝
Lµ
L1 ⎟⎠ [27]
The minimum load current may be reduced in three ways,
given a fixed output voltage. First, the switching frequency,
fSW, may be increased while keeping the same transformer
and output inductor. Operating at higher frequency tends
to decrease efficiency as switching transients account for
a higher percentage of the period. Some power transfer
lost to lower efficiency generally outweighs power spent
on burning dummy load current if the natural load is too
light. Second, the transformer magnetizing inductance may
be increased by using more turns to reduce the magnetizing current. Within the same family of transformers, an
8:4 transformer will have more magnetizing inductance
than a 2:1 transformer, but more turns also means more
winding resistance losses. Third, the output inductor may
be increased, which directly reduces the output ripple
current, and thus the minimum load.
If an application’s natural load is not sufficient, a dedicated
load resistor that guarantees the minimum current for a
given output voltage may be selected using Equation 28.
Consider the power dissipation when choosing the rating
and type of resistor ROUT.
⎛
Lµ
L1 ⎞
•⎜
⎟
⎜⎝ (N / N )2 (1− DMIN ) ⎟⎠
P
S
switches, the current sense resistor, and the DCR’s of the
transformer and inductor. Take care to select components
for their low ohmic losses to control both the absolute
accuracy of the output voltage and the load regulation
effect. Once ohmic losses are estimated or measured
for a given application, the output voltage target may be
adjusted upward, and a new value of set resistor chosen
to compensate, see Programming the Duty Cycle Loop
Output Voltage Target.
Transformer Selection
Important parameters that guide the choice of transformer
include the primary-to-secondary turns ratio, the presence
or absence of auxiliary windings and their turns ratios,
the power rating, the operating frequency, the magnetizing inductance, the leakage inductance, the DC winding
resistances of the primary and secondary and the isolation
voltage rating.
An application’s input voltage range and output voltage
target drive the choice of turns ratio between the primary
and secondary windings (see Equation 12). DC/DC power
transformer winding ratios should be specified to ±1%, a
variation that directly affects the accuracy of converters
without output voltage feedback, but that only influences the
duty cycle range in circuits with output voltage feedback.
Some application circuits require auxiliary primary- or
secondary-side rails to accommodate the supply limits of
other external devices. Switching power dissipation in the
LT8310 may be reduced by driving the INTVCC regulator
externally from a third winding.
[28]
Rather than stipulate a maximum current and core flux
limit for DC/DC converter transformers, most vendors
specify a power rating, an operating frequency range and
a minimum magnetizing inductance.
Before a more specific discussion of component selection,
a general note about DC resistance in the power path is
warranted. For duty mode control applications, no voltage feedback exists to compensate for voltage drops in
the system. Contributors include the on-resistance of all
While flux capability (saturation) is important, most
manufacturers specify a power rating.
ROUT < 2 • fSW
Ohmic Loss Matters
For a lower minimum load current, choose less magnetizing current/more magnetizing inductance.
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LT8310
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Table 2 provides some recommended transformer vendors.
Table 2.Recommended Transformer Manufacturers
MANUFACTURER
Champs Technologies
WEB ADDRESS
www.champs-tech.com
Coilcraft
www.coilcraft.com
Cooper-Coiltronics
Pulse Electronics
An initial design value for the resonant reset capacitor
requires estimates of the transformer’s magnetizing inductance (Lµ) and MOSFET output capacitance (COSS), in
addition to the reset time target (Equation 31).
www.cooperet.com
www.pulseelectronics.com
Würth-Midcom
www.we-online.com
Resonant Reset Capacitor Selection
The reset capacitor value must be sized to allow a half period
of a sine wave to complete during the shortest off-time the
switch normally experiences, namely when VIN is lowest
and the duty cycle is greatest. The LT8310’s maximum
duty cycle clamp of 78% typical/82% maximum (see the
Electrical Characteristics section) sets a lower bound on
the off-time of 18% of the period. Minimum input voltage,
turns ratio, and output voltage target determine the largest
duty cycle in steady state operation, DMAX. The resonant
reset time, tRST, must fall between the two:
⎛t
⎞2 1
CRST = ⎜ RST ⎟ •
− COSS
⎝ π ⎠ Lµ
[31]
Board layout, transformer windings, and the forward diodes
also contribute to the total switch node capacitances, and
may be subtracted from the resonant capacitor value as
required. Keep the resonant reset capacitor close to the
MOSFET’s drain at one terminal and well grounded with a
short trace at the other terminal. Prototyping to characterize
the actual reset behavior is highly recommended.
In step-up applications (where NP/NS < 1), splitting the
capacitance between the primary-side switch node and
the secondary-side forward node may help reduce switch
node ringing. The secondary-side capacitor value reflects
to the primary-side by a factor of (NS/NP)2.
0.18 • tSW < tRST < (1 - DMAX) • tSW [29]
Primary Switch MOSFET Selection
The maximum switch node voltage, VSW(MAX), occurs at the
peak of the resonance when the input voltage is greatest. In
practical circuits, the switch node might slew beyond VIN
before resonating, it might initially spike, and then have a
high frequency ripple, or it might not complete resonance
if the available reset time is too short—all of which change
the peak voltage. Estimate the maximum switch voltage
with Equation 30, and increase it by at least 20% when
choosing the voltage rating of the reset capacitor.
Important parameters for the primary N-channel MOSFET
switch include the maximum drain-source voltage rating
(VDS), the gate-source threshold voltage (VGS), the onresistance (RDS(ON)), the gate charge (QG), the maximum
drain current (ID), and the thermal resistances (θJC and θJA).
VSW(MAX) = VIN(MAX)
⎛N ⎞ π t
+VOUT(TARG) • ⎜ P ⎟ • • SW
⎝ NS ⎠ 2 tRST
[30]
A COG/NPO type capacitor is the best choice for the resonant reset capacitor—first, for its negligible microphonic
action that would otherwise cause electronic or audio
interference, and second, for its excellent voltage linearity
and flatness over temperature, which makes for consistent
timing across operating conditions and less margining of
other components and specifications.
24
The drain-source breakdown voltage (BVDSS or VDS(MAX))
is the key to MOSFET selection because the primary switch
experiences a maximum voltage significantly above the
input (see Figure 3), which was estimated in Equation 30.
Many available power MOSFETs are avalanche-rated, and
will easily withstand occasional overvoltage, but regular
avalanching is inefficient, and can be destructive depending on energy, frequency, and temperature. Derating the
result of Equation 30 by at least 20% and prototyping the
circuit are recommended design procedures.
An internal current limit on the INTVCC output protects the
LT8310 from excessive on-chip power dissipation. The
minimum value of this current should be considered when
choosing the main N-channel MOSFET and the operating
frequency. Selection of a lower QG MOSFET allows higher
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switching frequencies, which leads to smaller magnetics.
The required switching current, IGATE, can be calculated
using Equation 32, see the Thermal Considerations section
for further details.
IGATE = QG • fSW [32]
The power dissipated in the primary MOSFET in a forward
converter is described by Equation 33. The first term
represents the conduction loss in the device, and the
second term represents the switching loss. CRSS is the
reverse-transfer capacitance, which is usually specified
in the MOSFET characteristics. For maximum efficiency,
RDS(ON) and CRSS should be minimized.
PSW = I2L(MAX) • RDS(ON) • DMAX
2
+2 • VIN
• CRSS • fSW •
IL(MAX)
1A
[33]
From the known power dissipated in the main MOSFET,
its junction temperature can be obtained using Equation
34. TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
TJ = TA + PSW • θJA = TA + PSW • (θJC + θCA) [34]
Input Capacitor Selection
The input capacitor supplies the transient input current
through to the transformer and main switch, so it must be
sized according to transient current requirements. Forward
converters experience discontinuous input currents on par
with the load current divided by the transformer turns ratio.
The switching frequency, output current, and tolerable input
voltage ripple are key inputs to estimating the capacitor
value required to limit input voltage ripple to a specified
level. An X7R type ceramic capacitor is usually the best
choice since it has the least variation with temperature and
DC bias. Low ESR and ESL at the switching frequency are
necessary to avoid excess spiking of the input voltage.
To achieve RMS input ripple of VIN(RIPPLE), the input
capacitor for a forward converter can be estimated using
Equation 35. For example, 15µF is an appropriate selection for 100mV RMS ripple on a 350kHz converter with
2A maximum load current and a transformer turns ratio
of NP/NS = 2.
CIN =
0.5 • IL(MAX)
fSW • VIN(RIPPLE) • (NP / NS )
[35]
Table 3 provides some recommended ceramic capacitor
vendors.
Table 3.Recommended Ceramic Capacitor Manufacturers
MANUFACTURER
WEB ADDRESS
Kemet
www.kemet.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
TDK
www.tdk.com
Inductor Selection
The inductor used with the LT8310 should have a saturation
current rating appropriate to the maximum load current, and
thus appropriate to the switch current rating and RSENSE
resistor. For applications with no output voltage feedback,
choose an inductor value that keeps ripple current low in
support of the minimum load current target, IL(MIN). If
the contribution of the output inductor equals that of the
reflected transformer magnetizing inductance (Lµ), a first
cut for the inductor value based on operating frequency,
output voltage, and minimum duty cycle is:
L1=
VOUT • (1−DMIN )
f SW • IL(MIN)
[36]
Once both the transformer and inductor are chosen, the
minimum load current estimate in Equation 27 should be
re-evaluated, and the component selections modified if
necessary.
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LT8310
Applications Information
For applications where current mode control dominates,
choose an inductor value that provides a current mode
ramp on SENSE during the switch on-time of approximately
20mV magnitude based on operating frequency, output
voltage, minimum duty cycle and transformer turns ratio.
The following equation is useful to estimate the inductor
value for continuous conduction mode operation:
L1=
VOUT • (1−DMIN )
RSENSE
•
fSW
(NP / NS ) • 20mV
[37]
Table 4 provides some recommended inductor vendors.
Table 4. Recommended Inductor Manufacturers
MANUFACTURER
Champs Technologies
WEB ADDRESS
www.champs-tech.com
Coilcraft
www.coilcraft.com
Cooper-Coiltronics
www.cooperet.com
Vishay
Würth-Midcom
www.vishay.com
www.we-online.com
Secondary-Side Switch Selection
A nonsynchronous application, with or without output
voltage feedback, requires only Schottky diode switches
in the secondary. The forward diode conducts the full
(increasing) inductor current when the primary switch
is closed, and the reflected magnetization current (much
smaller) after resonant reset completes. The catch diode
conducts the full (decreasing) inductor current when the
main switch turns off, which is reduced by the magnetization current after resonant reset completes (see Figure 3).
Three-pin dual-packaged diodes may be used to save board
space because the diodes share a node, but the switches
see different reverse voltages, which may favor different
parts in higher current applications. The forward diode
must withstand in reverse the full primary switch node
resonance voltage divided by the primary-to-secondary
turns ratio (NP/NS); see Equation 30 for an estimate of
the resonant maximum. The catch diode must withstand
the maximum input voltage divided by the turns ratio
in reverse. However in step-up applications, the catch
node may ring, which would require a higher rating for
26
the switch, or a snubber to limit the peak voltage. When
choosing diode breakdown ratings consider the likelihood
of abnormal operating conditions. For example: incomplete
resonant reset increasing the switch node voltage and
reverse stress on the forward diode, or sub minimum load
current resulting in increased output voltage and reverse
stress on the catch diode.
As in any converter, the voltage drop across the switches
reduces efficiency, which is reason enough to use low
threshold Schottky diodes with low series resistance.
In duty mode control dominated applications, the actual
output voltage is reduced from the target voltage by the
diode drop. The nominal forward voltage drop at a fixed
load can be planned into the target voltage if desired (see
the section, Programming the Duty Loop Output Voltage
Target. Both the forward and catch diodes must be rated
for the maximum inductor current, have suitable power
dissipation ratings, and be fast enough relative to the
switching frequency to achieve crisp turn-on and turnoff edges.
Table 5 provides some recommended diode vendors.
Table 5. Recommended Diode Manufacturers.
MANUFACTURER
Central Semiconductor
WEB ADDRESS
www.centralsemi.com
Diodes, Inc.
www.diodes.com
ON Semiconductor
www.onsemi.com
Vishay
www.vishay.com
Synchronous applications with MOSFET switches in the
secondary have the same stresses and requirements as
diodes, but the advantage of smaller forward voltage drops.
The LT8310 provides the non-overlapping SOUT signal
that is the inverse of the GATE drive for synchronizing
switch drivers such as the LT8311 or LTC3900 to avoid
cross-conduction, see their data sheets for details.
Synchronous switches will experience body diode conduction at start-up, shutdown, and during small delays
each switching period. Consider body diode current and
reverse recovery time when selecting MOSFET switches.
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Output Capacitor Selection
The inductor in the output stage of a forward converter
ensures continuous load current, hence for constant or
slowly varying loads, the output capacitance has a relatively
easy task of filtering inductor ripple current. Fast load
steps withdraw or deposit capacitor charge that changes
the output voltage until inductor current reacts to restore
it and meet the new load demand.
In current mode control applications, tight coupling
between the voltage and current feedback loops and the
compensation zero at the VC pin make for excellent load
regulation. The recommended output capacitors for these
circuits are a 220µF electrolytic in parallel with a small
X7R type ceramic capacitor with low equivalent series
resistance (ESR).
In duty mode control applications, no load voltage feedback is present, so the peak transient output excursion
(ΔVOUT(PK)) goes as the product of the L-C filter output
impedance (√L1/CL), and the magnitude of the load current step (ΔIL(MAX)). Assuming L1 is fixed by other considerations, maximize the load capacitance to minimize
the transient peak, as shown in Equation 38. The ESR
specification of the capacitor should be chosen to satisfy
Equation 39, to minimize its effect.
Arrange multiple X7R type ceramic capacitors in parallel to achieve very low ESR and the desired amount of
capacitance with good temperature and bias stability.
Substituting a high valued electrolytic with high ESR in
parallel with a small X7R capacitor does not provide the
same performance, and should be avoided.
⎛ ΔI
⎞2
L(MAX)
⎟ • L1
CL ≥ ⎜⎜
⎟
ΔV
OUT(PK)
⎝
⎠
L1
ESR2
CL
In steady-state, output voltage ripple arises from inductor ripple current that charges and discharges the output
capacitor, and from the voltage drop across its ESR.
Equation 40 provides an estimate of the output ripple in
relation to the nominal output voltage.
VOUT(RIPPLE) ≈
⎛
1
ESR ⎞⎟
⎜
+
⎜ L1• C • f2
⎟ • VOUT(NOM)
L1•
f
SW
⎝
⎠
L SW
Programming the Output Voltage in Direct-Wired
Feedback Applications
For nonisolated applications, direct-wired feedback from
the load to the FBX pin configures the LT8310 as a traditional peak current mode controlled forward converter.
The FBX pin features dual references (1.6V and –0.8V)
that support DC/DC conversion or DC/DC inversion automatically. Proper selection of the transformer turns ratio
also makes large conversion/inversion ratios (step-down
or step-up) possible without relying on extremely low or
high duty cycles, which improves efficiency. In wired applications, the output voltage (VOUT) is set by a resistor
divider, as shown in Figure 8.
VINTVCC
RSET
R6
LT8310
RDVIN
FBX
R5
DFILT
CDFILT
GND
VC
RZ
CC
VOUT
INTVCC
[38]
[39]
[40]
C0
OPT.
8310 F08
Figure 8. Wired Feedback for Nonisolated
Supply Applications
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LT8310
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Equations 41 and 42 provide suitable resistor ratios for
positive and negative output converters:
Programming the Output Voltage in Opto-Isolated
Feedback Applications
R6 VOUT(POS)
=
−1
1.6V
R5
Application circuits requiring both isolation and excellent
line regulation can use the LT8310 with opto-isolated
feedback. The opto-coupler must be paired with an optocoupler driver device, e.g., the LT8311 or the LT4430,
which usually governs the output voltage programming.
In Figure 9, a resistive voltage divider, R5 and R6, feeds
the FB pin of the LT8311. In general, the output voltage
programming in terms of the resistor ratio and opto driver
reference level, VREF(OPTO), is then:
[41]
R6 VOUT(NEG)
=
−1
−0.8V
R5
[42]
In this configuration, compensate the LT8310 directly at
the VC pin using the guidelines in the Compensating the
Direct-Wired Current Mode Control Loop section. Also, the
duty loop must still be programmed and compensated so
the volt-second clamp can protect the transformer. Select
the RSET resistor to program a target VOUT greater than
the feedback resistors do to give the volt-second clamp
operating headroom; see the Programming the Duty Cycle
Loop Output Voltage Target section. Select the DFILT pin
capacitor as described in the Compensating the Duty Mode
Control Loop section.
⎛ R6 ⎞
VOUT
−1
⎜ ⎟=
⎝ R5 ⎠ VREF(OPTO)
L1
VIN
VOUT
VIN
T1
NP:NS
CREG
•
•
D1
D2
CL
–VOUT
LT8310
VINTVCC
[43]
CRST
INTVCC
GATE
RDVIN
SENSE
M1
RSET
RSENSE
DFILT
CFLT
VC
GND
FBX
VINTVCC
R13
VINTVCC
R11
C8
VIN
R8
R12
R10
R6
LT8311
OPTO FB
R7
COMP
8310 F07
GND
C7
R9
R5
8310 F09
–VIN
Figure 9. Key Components of an Isolated Nonsynchronous Supply
28
8310f
For more information www.linear.com/LT8310
LT8310
Applications Information
Thermal Considerations
The LT8310 is rated to a maximum input voltage of 100V.
Careful attention must be paid to the internal power dissipation of the IC at higher input voltages to ensure that
a junction temperature of 125°C (150°C for H-grade) is
not exceeded. This junction limit is especially important
when operating at high ambient temperatures. At a junction
temperature of 165°C, the thermal limiter shuts down the
system, which pulls the GATE pin to GND, pulls the SOUT
pin to INTVCC, and discharges the soft-start (SS) pin to
GND. Switching can resume after the device temperature
falls by 10°C. This function is intended to protect the device
during momentary thermal overload.
In many applications, the majority of the power dissipation
in the IC comes from the supply current needed to drive
the gate capacitance of the external power MOSFET(s).
For the main switch driven by the GATE pin, and a switch
(if present) on the SOUT pin, the gate-drive current can
be calculated for each as in Equation 7.
A low QG power MOSFET should always be used when operating at high input voltages and the switching frequency
should also be chosen carefully to ensure that the IC does
not exceed a safe junction temperature. The internal junction temperature of the IC can be estimated by:
TJ = TA + VIN • (IQ + IDRIVE (TOT)) • θJA [44]
where TA is the ambient temperature, IQ is the quiescent
current of the part (maximum 4mA), and θJA is the package’s junction-to-ambient thermal impedance (38°C/W).
For example, an application having TA(MAX) = 85°C,
VIN(MAX) = 80V, fSW = 200kHz, and having a MOSFET with
QG = 30nC, the maximum IC junction temperature will be
approximately:
TJ = 85°C + 80V • (4mA + 30nC • 200kHz)
• 38°C/W ≈ 115°C [45]
The exposed pad on the bottom of the package must be
soldered to a ground plane. This ground should then be
connected to an internal copper ground plane with thermal
vias placed directly under the package to spread out the
heat dissipated by the IC.
The LT8310’s internal power dissipation can be reduced
by supplying the GATE and SOUT pins (and some internal
circuits) from an external source, such as a regulated
auxiliary transformer winding. The INTVCC pin may be
overdriven as long as 10.5V < VINTVCC(MAX) < VIN(MIN),
which avoids back-driving the VIN pin. The practical upper limit of INTVCC overdrive is 17.4V (typ) where the
regulator’s overvoltage threshold shuts down switching.
PCB Layout / Thermal Guidelines
For proper operation, PCB layout must be given special
attention. Critical programming signals must be able to
coexist with high dv/dt signals. Compact layout can be
achieved but not at the cost of poor thermal management.
The following guidelines should be followed to approach
optimal performance.
1. Ensure that a local bypass capacitor is used (and placed
as close as possible) between VIN and GND for the
controller IC(s).
2. The critical programming resistor for timing, RT, must
use short traces to both the RT pin and the GND pin
(exposed pad). Keep traces to the RT pin and the DFILT
pin separated.
3. The critical programming resistor for duty cycle, RSET,
must use short traces to both the RDVIN pin and the
INTVCC pin.
4. The current sense resistor for the forward converter
must use short Kelvin connections to the SENSE pin
and GND pin (exposed pad).
8310f
For more information www.linear.com/LT8310
29
LT8310
Applications Information
5. High dv/dt lines should be kept away from both critical
programming resistors (RT, RSET), the current sense
inputs, the VC pin, the UVLO and OVLO pins, and the
FBX feedback traces.
8. Keep high switching current paths away from signal
grounding. Also minimize trace lengths for those
high current switching paths to minimize parasitic
inductance.
6. Gate driver (GATE) and synchronization (SOUT) traces
should be kept as short as possible.
9. For synchronous applications, ensure that the pulse
transformer (from LT8310’s SOUT pin to the SYNC pin
of the secondary-side controller) is properly damped
and not effected by high dv/dt traces. This will prevent
false triggering of the synchronous FETs, avoiding
cross-conduction and repeated soft-start retry (hiccup
mode) behavior.
7. When working with high power components, multiple
parallel components are the best method for spreading out power dissipation and minimizing temperature
rise. In particular, multiple copper layers connected by
vias should be used to sink heat away from each power
MOSFET and power diode.
30
8310f
For more information www.linear.com/LT8310
LT8310
Typical Applications
78 Watt Isolated Nonsynchronous Forward Converter
VIN
36V TO 72V
C1
2.2µF
100V
×4
86.6k
UVLO VIN
LT8310
1.43k
INTVCC
SENSE
RDVIN
GND
C4
22µF
35V
×8
D2
+
VOUT
12V
C5 0.6A TO 6.5A
33µF
35V
TANT
×3
D1
–VOUT
M1
GATE
RSENSE
0.025Ω
102k
DFILT
NC
SYNC
RT
SS
49.9k
200kHz
0.47µF
–VIN
•
C3
150pF
250V
NPO
OVLO
10nF
•
1µF
100V
1.74k
4.7µF
L1
47µH
T1
2:1
SOUT
NC
VC FBX
NC
D1:
D2:
L1:
M1:
T1:
VISHAY VB30120S
VISHAY VBT3080S
WÜRTH WE74435584700
INFINEON IPD600N25N3
WÜRTH WE750313917
8310 TA02a
Output Voltage Line Regulation
Efficiency vs Load Current
14.0
96
13.5
94
13.0
EFFICIENCY (%)
92
VOUT (V)
12.5
12.0
11.5
11.0
10.0
30
40
50
60
VIN (V)
70
88
86
IOUT = 0.6A
IOUT = 1.5A
IOUT = 3.5A
IOUT = 6.5A
10.5
90
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 72V
84
80
82
0
8310 TA02b
1
2
4
3
IOUT (A)
5
6
7
8310 TA02c
8310f
For more information www.linear.com/LT8310
31
LT8310
Typical Applications
78 Watt Isolated Synchronous Forward Converter
VIN
36V TO 72V
C1
2.2µF
100V
×4
T1
2:1
1µF
100V
86.6k
•
•
0.1µF
50V
OVLO
1.43k
5.6k
LT8310
GATE
INTVCC
M3
M1
SENSE
GND
DFILT
10nF
NC
SYNC
0.47µF
VC
FBX
VCC
•
100pF
FG
GND
NC
8310 TA03a
–VOUT
Efficiency vs Load Current
14.0
96
13.5
94
92
EFFICIENCY (%)
VOUT (V)
L1: WÜRTH WE74435572200
M1: INFINEON IPD600N25N3
M2: INFINEON BSC077N12NS3
M3: INFINEON BSC076N06NS3
Q1: CENTRAL SEMI MMBT5551
T1: WÜRTH WE750313917
T2: PULSE PE-68386NL
330Ω
13.0
12.5
12.0
11.5
90
88
86
11.0
VIN = 36V
VIN = 48V
VIN = 72V
10.5
0
1
2
4
3
IOUT (A)
5
6
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 72V
84
7
82
0
8310 TA03b
32
C6
47µF
25V
TANT
×3
TIMER
SYNC
•
+
270k
LTC3900
CS–
Output Voltage Line Regulation
10.0
4.7µF
T2
1:1
SOUT
SS
49.9k
200kHz
M2
220pF
RT
–VIN
RSENSE
0.025Ω
CS+
C5
22µF
25V
×4
CG
5.6k
102k
RDVIN
Q1
10V
C3
150pF
250V
NPO
1.74k
VOUT
12V
0A TO 6.5A
10k
10Ω
VIN
UVLO
4.7µF
16V
L1
22µH
1
2
4
3
IOUT (A)
5
6
7
8310 TA03c
8310f
For more information www.linear.com/LT8310
LT8310
Typical Applications
78 Watt Isolated Nonsynchronous Forward Converter with Opto Feedback
VIN
36V TO 72V
C1
2.2µF
100V
×4
86.6k
2.2nF
LT8310
INTVCC
SENSE
RDVIN
GND
NC
D4
L2
3300µH
0.1µF
50V
VINTVCC
330Ω
10Ω
100k
SYNC
FBX
RT
SS SOUT VC
D3
RSENSE
0.025Ω
DFILT
49.9k
200kHz
–VOUT
M1
GATE
130k
NC
D2
0.01µF
VOUT
12V
0A TO 6.5A
C5
33µF
25V
TANT
×3
+
C4
22µF
25V
×4
D1
OVLO
1.43k
•
C3
150pF
250V
NPO
1.74k
4.7µF
16V
•
1µF
100V
UVLO VIN
VINTVCC
L1
22µH
T1
2:1
10k
Q1
10V
2k
330Ω
4.7µF
16V
D5
OPTO
20.0k
0.47µF
OC
6.8nF
COMP
6.34k
GND
220pF
11.3k
909k
–VIN
8310 TA04a
D1: VISHAY VB30120S
D2: VISHAY VBT3080S
D3, D4: BAV3004
D5: BAS516
Output Voltage Line Regulation
14.0
96
VIN = 36V TO 72V
94
13.0
EFFICIENCY (%)
92
12.5
VOUT (V)
L1: WÜRTH WE744355722
L2: COILCRAFT LPS5030-335MRB
M1: INFINEON IPD600N25N3
Q1: CENTRAL SEMI MMBT5551
T1: WÜRTH WE750313917
Efficiency vs Load Current
13.5
12.0
11.5
90
88
86
11.0
VIN = 36V
VIN = 48V
VIN = 60V
VIN = 72V
84
10.5
10.0
215k
FB
LT4430
MOC 207
6.65k
VIN
0
1
2
4
3
IOUT (A)
5
6
7
82
0
8310 TA04b
1
2
4
3
IOUT (A)
5
6
7
8310 TA03c
8310f
For more information www.linear.com/LT8310
33
LT8310
Typical Applications
Wide VIN, 60 Watt Isolated 8V Rail for Low Voltage Regulators
VIN
9V TO 42V
C1
2.2µF
100V
×4
T1
3:4
1µF
100V
39.2k
•
0.1µF
50V
NOTE 1
C3
2200pF
100V
NPO
×2
5.62k
OVLO
4.7µF
16V
LT8310
GATE
INTVCC
10nF
GND
DFILT
NC
SYNC
VC
M3
FBX
10Ω
3.3k 3W
NOTE 2
D2
33nF
100V
Q1
CS+
VCC
4.7µF
16V
CG
30.1k
M2
+
270k
LTC3900
CS–
TIMER
220pF
FG
C6
22µF
25V
TANT
×5
C5
22µF
25V
×4
GND
SYNC
T2
1:1
SOUT
SS
•
•
330Ω
NC
0.47µF
–VIN
RSENSE
0.008Ω
220pF
RT
49.9k
200kHz
30.1k
10Ω
SENSE
RDVIN
470Ω
D1
VOUT
8V
0A TO 7.5A
5.6V 5.6V
M1
25.5k
2.2nF
L2
3300µH
•
VIN
UVLO
1.24k
L1
33µH
8310 TA05a
D1, D2: BAV3004
D3: CENTRAL SEMI CMMR1U-02
L1: WÜRTH WE74435583300
L2: COILCRAFT LPS5030-335MRB
M1: INFINEON BSC057N08S3-GL
–VOUT
M2: INFINEON BSC067N06LS3-G
M3: INFINEON BSC060N10S3-G
Q1: CENTRAL SEMI MMBT5551
T1: WÜRTH WE750341138
T2: PULSE PE-68386NL
NOTE 1: IN GENERAL, TWO STACKED 5V TO 6V ZENERS WILL HAVE LESS
THERMAL VARIATION THAN A SINGLE 10V TO 12V ZENER
NOTE 2: FOR EXAMPLE, USE THREE (3) PARALLELED 10k, 1W RESISTORS
Output Voltage Line Regulation
Efficiency vs Load Current
10.0
96
9.5
92
EFFICIENCY (%)
VOUT (V)
9.0
8.5
8.0
7.5
VIN = 9V
VIN = 18V
VIN = 30V
VIN = 42V
7.0
6.5
6.0
0
1
2
3
4
5
6
7
88
84
80
VIN = 9V
VIN = 18V
VIN = 30V
VIN = 42V
76
8
72
0
IOUT (V)
8310 TA05b
34
1
2
3
5
4
IOUT (A)
6
7
8
8310 TA05c
8310f
For more information www.linear.com/LT8310
LT8310
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1924 Rev Ø)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20
6.60 ±0.10
18
16 15 14 13 12 11
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
3
5 6 7 8 9 10
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20(16) (CB) TSSOP REV 0 0512
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
8310f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8310
35
LT8310
Typical Application
94% Efficient, 150W Isolated Synchronous Forward Converter
VIN
36V TO 72V
C1
4.7µF
100V
×4
•
LT8310
1.43k
4.7µF
16V
3.9nF
SENSE
RDVIN
GND
NC
VC
20k
FBX
FB
CSP
FSW
CG
CSW
CSN
LT8311
11.3k
–VOUT
VOUT
VIN
100k
SYNC
PGOOD
COMP
INTVCC
OPTO
PMODE
SS
TIMER GND
RSENSE
0.012Ω
22nF
SOUT
40.2k
249kHz
0.47µF
178Ω
220pF
SYNC
RT
SS
178Ω
M1
121k
DFILT
FG
M3
GATE
INTVCC
470µF
VOUT
12V
0A TO 12.5A
100k
390pF
250V
OVLO
+
68pF
3.9nF
M2
1.74k
47µF
×2
20k
D1
•
1µF
100V
86.6k
UVLO VIN
VINTVCC
L1
8µH
T1
8:4
T2
1.25:1
VINTVCC
90.9k
•
4k
3.3k
8310 TA06a
560Ω
–VIN
1µF
4.7µF
22nF
•
100pF 499Ω
10k
62k
499k
2.2µF
4k
PS2801-1
D1: CENTRAL SEMI CMMR1U-02
L1: CHAMPS HRPQI2050-08
M1: INFINEON BSC320N20NS3G
M2: INFINEON BSC042NE7NS3
M3: FAIRCHILD SEMI FDMS86101DC
T1: PULSE PA0423
T2: PULSE PA3493NL
Related Parts
PART NUMBER
LT3752/LT3752-1
LT3753
LT8311
DESCRIPTION
Active Clamp Synchronous Forward Controllers with Internal
Housekeeping Controller
Active Clamp Synchronous Synchronous Forward Controller
Preactive Secondary-Side Synchronous Forward Controller
LTC®3765/LTC3766
Synchronous No-Opto Forward Controller Chip Set with
Active Clamp Reset
LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers
LTC3721-1/LTC3721-2 Nonsynchronous Push-Pull and Full-Bridge Controllers
LTC3722/LTC2722-2
Synchronous Full-Bridge Controllers
LT3748
100V Isolated Flyback Controller
LT3798
LTC3900
Off-Line Isolated No-Opto Flyback Controller with Active PFC
Synchronous Rectifier N-Channel MOSFET Driver for
Forward Converters
Secondary-Side Optocoupler Driver with Reference Voltage
LT4430
36 Linear Technology Corporation
COMMENTS
Input Voltage Range: LT3752: 6.5V to 100V, LT3752-1: Limited
Only by External Components
Input Voltage Range: 8.5V to 100V
Optimized for Use with Primary-Side LT3752/-1, LT3753 and
LT8310 Controllers
Direct Flux Limit™, Supports Self-Starting Secondary Forward
Control
High Efficiency with On-Chip MOSFET Drivers, Adjustable
Synchronous Rectification Timing
Minimizes External Components, On-Chip MOSFET Drivers
Adaptive or Manual Delay Control for Zero Voltage Switching,
Adjustable Synchronous Rectification Timing
5V ≤ VIN ≤ 100V, No-Opto Flyback , MSOP-16 with High Voltage
Spacing
VIN and VOUT Limited Only by External Components
Programmable Timeout and Reverse-Inductor Protection,
Transformer Synchronization, SSOP-16
Overshoot Control Prevents Output Overshoot During Start-up
and Short-Circuit Recovery
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LT8310
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT8310
8310f
LT 0814 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014
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