LT8315
560VIN Micropower No-Opto
Isolated Flyback Converter
with 630V/300mA Switch
DESCRIPTION
FEATURES
Wide Input Voltage Range: 18V to 560V
nn 630V/300mA Integrated Power Switch
nn No Opto-Isolator Required for Regulation
nn Quasi-Resonant Boundary Mode Operation
nn Constant-Current and Constant-Voltage Regulation
nn Low Ripple Light Load Burst Mode® Operation
nn Low Quiescent Current: 70μA
nn Programmable Current Limit and Soft-Start
nn TSSOP Package with High Voltage Spacing
The LT®8315 is a high voltage flyback converter with integrated 630V/300mA switch. No opto-isolator is needed for
regulation. The device samples the output voltage from the
isolated flyback waveform appearing across a third winding on the transformer. Quasi-resonant boundary mode
operation improves load regulation, reduces transformer
size and maintains high efficiency.
nn
APPLICATIONS
At start-up, the LT8315 charges its INTVCC capacitor via a
current source attached to the DRAIN pin. During normal
operation, the current source turns off and the device
draws its power from a third winding on the transformer.
Isolated Telecom, Automotive, Industrial, Medical
Power Supplies
nn Isolated Off Line Housekeeping Power Supplies
nn Electric Vehicles and Battery Stacks
The LT8315 operates from a wide range of input supply
voltages and can deliver up to 15W of power. It is available
in a thermally enhanced 20-pin TSSOP package with four
pins removed for high voltage spacing.
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
20VIN to 450VIN Isolated 12VOUT Supply
Efficiency
VIN
20V TO 450V
90
80
5:1:2
600Ω
20k
93.1k
47pF
10µF
BIAS
FB
61.9k
INTVCC
SMODE
DRAIN
VC
100k
470pF
22nF
5.11k
TC
LT8315
10µF
160µH
DCM
EN/UVLO
VOUT+
12V
640µH
4mH
200µF
VOUT–
5mA to 220mA (VIN = 50V)
5mA to 320mA (VIN = 100V)
5mA to 380mA (VIN = 150V)
5mA to 440mA (VIN > 250V)
SOURCE
IREG/SS
GND
EFFICIENCY (%)
0.44µF
70
60
VIN = 50V
VIN = 100V
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 450V
50
40
30
0
100
200
300
400
LOAD CURRENT (mA)
500
8315 TA01b
330mΩ
121k
8315 TA01a
8315fa
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1
LT8315
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
DRAIN......................................................................630V
BIAS, EN/UVLO..........................................................40V
INTVCC.......................................................................15V
SMODE................................................................ INTVCC
SOURCE, TC, FB, VC, IREG/SS.....................................4V
DCM.................................................................... ±100mA
Operating Junction Temperature (Note 2)
LT8315E, LT8315I............................... −40°C to 125°C
LT8315H............................................. −40°C to 150°C
Storage Temperature Range................... −65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300 °C
ORDER INFORMATION
TOP VIEW
DRAIN 1
20 GND
DRAIN 2
19 NC
DRAIN 3
18 SOURCE
17 EN/UVLO
21
GND
16 SMODE
15 GND
14 IREG/SS
INTVCC 8
13 VC
BIAS 9
12 FB
DCM 10
11 TC
FE PACKAGE
20(16)-LEAD PLASTIC TSSOP
θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LT8315#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8315EFE#PBF
LT8315EFE#TRPBF
LT8315FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8315IFE#PBF
LT8315IFE#TRPBF
LT8315FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT8315HFE#PBF
LT8315HFE#TRPBF
LT8315FE
20-Lead Plastic TSSOP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
8315fa
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LT8315
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. BIAS = 40V, VEN/UVLO = 40V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
BIAS
Chip Bias Voltage Supply Range
After Startup
IQ
BIAS Quiescent Current
Burst Mode Operation
Active
ISHDN
DRAIN Shutdown Current
VEN/UVLO < 0.3V, BIAS = Floating
l
VDRAIN(MIN)
Minimum Drain Voltage for Startup
BIAS = Floating
l
ISTARTUP
Startup Current through Depletion FET
VDRAIN = 18V, BIAS = Floating
l
VUVLO
EN/UVLO Threshold
EN/UVLO Hysteresis
INTVCC UVLO Rising Threshold
40
V
70
470
150
700
μA
8
15
μA
9.5
UNITS
18
V
300
VEN/UVLO Falling
VEN/UVLO Rising
1.18
30
1.22
65
1.26
120
V
mV
Startup Current through Depletion FET
11.1
12
13.1
V
INTVCC UVLO Falling Threshold
FB Regulation Voltage
GM
Voltage Error Amplifier Transconductance
VFB = 1.22V ± 20mV
VTC
TC Voltage
TC Voltage Temperature Coefficient
TA = 25°C
ITC
TC Sinking/Sourcing Current
IIREG/SS
IREG/SS Current
μA
7.7
8.2
8.7
V
l
1.19
1.22
1.25
V
l
75
100
125
μS
1.16
1.22
+4.1
1.28
V
mV/°C
9.9
9.5
10
10.1
10.5
μA
–140
–65
−170
−85
–200
–105
μA
μA
7
10
500
300
800
±100
Current Out-of-Pin
l
Flyback Collapse Detection Threshold
Resonant Valley Detection Threshold
MAX
130
VREG
IDCM
TYP
IDCM Rising
IDCM Falling
μA
RSW
Power MOSFET Resistance
ISW(MAX)
Maximum Switch Current
VSOURCE(MIN)
Minimum Current Voltage Threshold
15
20
25
mV
VSOURCE(MAX)
Maximum Current Voltage Threshold
90
100
110
mV
VSOURCE(ILIM)
Over-Current Voltage Threshold
250ns Blanking Period; Restarts Chip
110
120
130
mV
FSW(MIN)
Minimum Switching Frequency
Burst Mode
Standby Mode
3
187
3.5
220
4
250
kHz
Hz
FSW(MAX)
Maximum Switching Frequency
138
140
142
kHz
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8315E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design
Ω
mA
mA
characterization and correlation with statistical process controls. The
LT8315I is guaranteed over the full −40°C to 125°C operating junction
temperature range. The LT8315H is guaranteed over the full −40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
8315fa
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LT8315
TYPICAL PERFORMANCE CHARACTERISTICS
FRONT PAGE APPLICATION
12.3
12.3
12.2
12.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage vs Temperature
12.4
12.1
12.0
11.9
VIN = 50V
VIN = 100V
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 450V
11.8
11.7
11.6
0
100
200
300
400
LOAD CURRENT (mA)
12.0
11.9
11.8
11.6
–50 –25
FREQUENCY (kHz)
40
VSOURCE
100mV/DIV
VOUT
AC COUPLED
50mV/DIV
VOUT
AC COUPLED
50mV/DIV
FRONT PAGE APPLICATION
200
300
400
LOAD CURRENT (mA)
0
75
150
225
300
LOAD CURRENT (mA)
500
375
450
Discontinuous Mode Waveforms
VSOURCE
100mV/DIV
10µs/DIV
100
VIN = 100V
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 450V
8315 G03
VDRAIN
200V/DIV
20
0
0
VDRAIN
200V/DIV
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
Boundary Mode Waveforms
VIN = 50V
VIN = 100V
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 450V
80
6
3
IOUT = 100mA
IOUT = 200mA
IOUT = 440mA
0
9
8315 G02
Switching Frequency
100
FRONT PAGE APPLICATION
RIREG/SS = 66.5kΩ
12
12.1
8315 G01
120
FRONT PAGE APPLICATION
VIN = 350V
11.7
500
CV/CC Operation
15
OUTPUT VOLTAGE (V)
Load and Line Regulation
12.4
TA = 25°C, unless otherwise noted.
8315 G05
10µs/DIV
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 440mA
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 50mA
Load Transient Response
Startup Waveforms
8315 G06
8315 G04
Burst Mode Waveforms
VIN
350V/DIV
VOUT
10V/DIV
IOUT
500mA/DIV
VDRAIN
200V/DIV
VSOURCE
100mV/DIV
VINTVCC
10V/DIV
VOUT
AC COUPLED
500mV/DIV
VOUT
AC COUPLED
50mV/DIV
100µs/DIV
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 3mA
8315 G07
VBIAS
10V/DIV
10ms/DIV
8315 G08
FRONT PAGE APPLICATION
VIN = 350V, IOUT = 10mA TO 440mA
50ms/DIV
8315 G09
FRONT PAGE APPLICATION
VIN = 350V, ROUT = 28Ω
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LT8315
TYPICAL PERFORMANCE CHARACTERISTICS
DRAIN Shutdown Current
BIAS Quiescent Current
Depletion Startup Current
160
VDRAIN = 100V
VDRAIN = 630V
1.6
–55°C
25°C
150°C
1.4
45
30
15
120
1.2
IINTVCC (mA)
QUIESCENT CURRENT (μA)
SHUTDOWN CURRENT (μA)
60
TA = 25°C, unless otherwise noted.
80
40
1.0
0.8
0.6
0.4
0.2
0
–50 –25
0
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
8315 G10
FB Regulation Voltage
3
6
9
VINTVCC (V)
EN/UVLO Rising
EN/UVLO Falling
12
15
8315 G12
TC Pin Voltage
1.240
1.80
1.235
1.30
1.25
1.20
1.60
1.230
TC VOLTAGE (V)
FB REGULATION VOLTAGE (V)
ENABLE THRESHOLD (V)
0
8315 G11
EN/UVLO Threshold
1.35
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.225
1.220
1.215
1.210
1.40
1.20
1.00
1.205
1.15
–50 –25
0
1.200
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
IREG/SS Pin Current
Switching Frequency Limit
Switch Current Limit
150
110
10.4
145
105
10.3
135
FREQUENCY (kHz)
10.0
9.9
9.8
130
125
5
4
3
9.7
100
MAXIMUM SWITCHING FREQUENCY
SOURCE VOLTAGE (mV)
140
10.1
MINIMUM SWITCHING FREQUENCY
95
85
25
20
15
2
10
1
5
9.5
–50 –25
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8315 G16
0
25 50 75 100 125 150
TEMPERATURE (°C)
8315 G17
MAXIMUM CURRENT LIMIT
90
9.6
0
25 50 75 100 125 150
TEMPERATURE (°C)
8315 G15
10.5
10.2
0
8315 G14
8315 G13
IREG/SS CURRENT (μA)
0.80
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
–50 –25
MINIMUM CURRENT LIMIT
0
25 50 75 100 125 150
TEMPERATURE (°C)
8315 G18
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LT8315
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Switch-Off Time
400
900
350
850
300
800
250
750
OFF TIME (ns)
ON TIME (ns)
Minimum Switch-On Time
200
150
700
650
100
600
50
550
0
–50 –25
0
TA = 25°C, unless otherwise noted.
500
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
8315 G19
8315 G20
DCM Pin Threshold
16
0
–20
RESISTANCE (Ω)
DCM CURRENT (µA)
12
–60
RESONANT VALLEY DETECT
–100
–120
–140
–160
10
8
6
4
FLYBACK COLLAPSE DETECT
–180
2
–200
–220
–50 –25
Switch RDS(ON)
14
–40
–80
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
–50 –25
8315 G21
0
25 50 75 100 125 150
TEMPERATURE (°C)
8315 G22
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LT8315
PIN FUNCTIONS
DRAIN (Pins 1,2,3): Drain of the 630V Internal Power
Switch and Startup FET. Design a compact layout with the
transformer and input capacitor, and minimize trace area
to reduce EMI and voltage spikes.
INTVCC (Pin 8): Internal Gate Driver Bias Voltage. During
start-up, current from the DRAIN charges this pin to 12V.
During operation, a linear regulator from BIAS maintains
this voltage at 10V. Bypass locally with a ≥2.2μF ceramic
≥15V capacitor.
BIAS (Pin 9): Unregulated Input Voltage for the IC. This pin
derives power from a third winding on the transformer to
provide power to INTVCC. Bypass locally with a capacitor.
DCM (Pin 10): Discontinuous Conduction Mode Detector. This pin detects the dV/dt of the switching waveform,
ensuring accurate output voltage sampling and quasiresonant boundary-mode switching. Connect a capacitor
with series resistance from this pin to the third winding.
TC (Pin 11): Temperature Compensation Pin. This pin
presents a proportional-to-absolute-temperature (PTAT)
voltage, which is equal to the internal 1.22V reference
voltage at 25°C and rises with temperature by 4.1mV/°C,
to compensate for the output rectifier diode. Connect an
appropriate resistor from this pin to FB.
FB (Pin 12): FeedBack Pin. The voltage appearing on this
pin is sampled and regulated to equal the internal 1.22V
reference voltage. Connect this pin to a resistor divider
from the third winding to regulate the output voltage.
IREG/SS (Pin 14): Current Regulation/Soft-Start Pin. A
10μA current flows out of this pin. The resulting voltage
sets the output current regulation point, as determined by
an internal current regulation loop. Program the current
with a resistor to GND, or connect a capacitor to implement soft-start.
SMODE (Pin 16): Standby Mode Pin. Connect this pin to
INTVCC to enable Standby Mode, which reduces the minimum switching frequency to 220Hz for ultralow quiescent
power consumption. Connect to GND to disable.
EN/UVLO (Pin 17): Enable/Undervoltage Lockout Pin. The
chip will operate only if the voltage on this pin is greater
than the internal 1.22V reference voltage. Connect to a
resistor divider as desired, or connect to BIAS or INTVCC
if UVLO functionality is not desired.
SOURCE (Pin 18): Source of 630V Internal Power Switch.
The voltage appearing on this pin is used for peak currentmode control and current limiting. Connect a currentsensing resistor to GND to program the current limit.
Design a compact layout with the transformer and input
capacitor to reduce EMI and voltage spikes.
NC (Pin 19): No-Connect. This pin is electrically disconnected. Leave floating.
GND (Pins 15, 20, 21): Ground. Solder the exposed pad
(Pin 21) to a ground plane for heat sinking.
VC (Pin 13): Loop Compensation Pin. An internal GM
transconductance amplifier feeds this pin with an error
current depending on the sampled FB voltage. The resulting voltage determines the switching frequency and peak
current limit for power delivery. Connect a series R-C
network to stabilize the regulator.
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LT8315
BLOCK DIAGRAM
NPS :1
VIN
CIN
ZSNUB
LPRI
DSNUB
•
•
DOUT
VOUT +
COUT
LSEC
VOUT –
9
BIAS
LDO
CBIAS
–
10V
+
VUVLO
DRAIN
1, 2, 3
630V
DEPLETION
FET
M2
+
DBIAS
8
17
MASTER
LATCH
EN/UVLO
BIAS/REF
CONTROL
TSD
CINTVCC
16
–
INTVCC
SMODE
630V
POWER
FET
S
Q
M1
DRIVER
R
CDCM
:NTS
•
RDCM
10
RFB2
12
LTER
RFB1
DCM
FB
BOUNDARY
DETECT
×1
VOLTAGE
CONTROLLED
OSCILLATOR
SOURCE
CURRENT
COMPARATOR
+
RSNS
×10
GND
15, 20, 21
–
S&H
18
RTC
11
TC
×1
+4.1mV/°C
CURRENT
ERROR AMP
VOLTAGE
ERROR AMP
–
GM
1.22V
1.25×(1–D)
–
+
10µA
+
13
VC
RC
14
IREG/SS
8315 BD
RIREG
CC
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LT8315
OPERATION
The LT8315 is a high-voltage current-mode switching
regulator designed for the isolated flyback topology. The
special problem normally encountered in such circuits is
that information relating to the output voltage on the isolated
secondary side of the transformer must be communicated
to the primary side in order to achieve regulation. This is
often performed by opto-isolator circuits, which waste
output power, require extra components that increase the
cost and physical size of the power supply, and exhibit
trouble due to limited dynamic response, nonlinearity,
unit-to-unit variation, and aging over life.
The LT8315 does not need an opto-isolator because it
derives its information about the isolated output voltage
by examining the flyback pulse waveform appearing on a
tertiary winding on the transformer. The output voltage is
easily programmed with two resistors.
Boundary Mode Operation
Boundary mode is a variable frequency, current-mode
switching scheme. The internal N-channel MOSFET turns
on and the inductor current increases until it reaches the
limit determined by the voltage on the VC pin and the sense
resistor’s value. After the internal MOSFET turns off, the
voltage on the tertiary winding rises to the output voltage
multiplied by the transformer tertiary-to-secondary turns
ratio. After the current through the output diode falls to
zero, the voltage on the tertiary winding falls. A boundary
mode detection comparator on the DCM pin detects the
negative dV/dt associated with the falling voltage and triggers the sample-and-hold circuit to sample the FB voltage.
When the tertiary voltage reaches its minimum and stops
falling, the boundary mode comparator turns the internal
MOSFET back on for minimal switching energy loss.
The LT8315 features a boundary mode control method (also
called critical conduction mode), where the part operates
at the boundary between continuous conduction mode and
discontinuous conduction mode. Due to boundary mode
operation, the output voltage can be determined from the
tertiary winding’s voltage when the secondary current is
almost zero. This method improves load regulation without
extra resistors and capacitors.
Boundary mode operation returns the secondary current
to zero every cycle, so parasitic resistive voltage drops
do not cause load regulation errors. Boundary mode
also allows the use of a smaller transformer compared
to continuous conduction mode and does not exhibit
subharmonic oscillation.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in traditional
switching regulators, including current comparator, internal
reference, LDO, logic, timers, and an N-channel MOSFET.
The novel sections include a special sampling error amplifier, a temperature compensation circuit, an output current
regulator, and a depletion-mode startup FET.
As the load gets lighter, the peak switch current decreases.
Maintaining boundary mode requires the switching frequency to increase. An excessive switching frequency
increases switching and gate charge losses. To limit these
losses, the LT8315 features an internal oscillator which
limits the maximum switching frequency to 140kHz. Once
the switching frequency hits this limit, the part starts to
reduce its switching frequency and operates in discontinuous conduction mode.
Depletion Startup FET
The LT8315 features an internal depletion mode MOSFET.
At startup, this transistor charges the INTVCC capacitor
so that the LT8315 has power to begin switching. This
removes the need for an external bleeder resistor or other
components.
Discontinuous Conduction Mode Operation
Low Ripple Burst Mode Operation
Unlike traditional flyback converters, the internal MOSFET
has to turn on and off to generate a flyback pulse in order
to update the sampled output voltage. The duration of a
well-formed flyback pulse must exceed the minimum-off
time for proper sampling. To this end, a minimum switch
turn-off current is necessary to ensure a flyback pulse of
sufficient duration.
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LT8315
OPERATION
As the load gets very light, the LT8315 reduces switching
frequency while maintaining the minimum current limit in
order to reduce current delivery while still properly sampling the output voltage. Because flyback pulses must be
generated to regulate the output, a minimum switching
frequency of 3.5kHz is enforced. The minimum switching frequency determines how often the output voltage
is sampled and introduces a minimum load requirement.
Tying the SMODE pin to INTVCC enables Standby Mode,
which reduces the minimum switching frequency to 220Hz,
reducing the minimum load requirement at the expense
of a longer period between samples.
CV/CC Regulation
Like a traditional voltage regulator, the LT8315 implements a GM transconductance amplifier that regulates
the output voltage. In addition, the LT8315 includes a
current regulation loop which regulates the estimated
output current to a point set by the voltage on the IREG/
SS pin. Below the current setpoint, the output voltage
is regulated for constant-voltage (CV) regulation. Below
the voltage setpoint, the output current is regulated for
constant-current (CC) regulation.
APPLICATIONS INFORMATION
The LT8315 is designed to be an easy-to-use, yet fullyfeatured flyback regulator. With proper technique, it is
simple to build an efficient and robust power solution.
The depletion FET is current-limited to avoid destructive
power levels. To ensure start-up, do not load INTVCC or
BIAS with excessive current while the chip is starting.
However, don’t let the simplicity beguile you into sloppy
lab practices: the voltage and power levels involved can
be lethal. Milliamperes from a high voltage power supply can cause heart fibrillation and death. Never touch
conductive nodes while the circuit is active, and keep one
hand behind your back while probing. Conduct lab work
in the presence of an assistant, who can perform first aid
in case of emergency.
ENABLE and Undervoltage Lockout (UVLO)
Depletion Startup FET
The LT8315 features an internal depletion-mode FET, which
has a negative threshold voltage and is therefore normally
on. At startup, this FET charges the INTVCC capacitor to
12V so that the LT8315 has power to begin switching.
This removes the need for an external bleeder resistor or
other startup components. Once INTVCC is charged, the
depletion-mode FET turns off.
A resistive divider from VIN to the EN/UVLO pin implements
undervoltage lockout (UVLO). The EN/UVLO pin threshold
is set at 1.22V. Upon startup, the EN/UVLO pin exhibits a
~65mV hysteresis voltage to prevent oscillations.
The EN/UVLO pin can also be driven with logic levels and
set by the output pin of a digital controller. Otherwise,
EN/UVLO can also be tied to BIAS or INTVCC to keep the
chip enabled.
Output Voltage
The output voltage is programmed by the RFB1 and RFB2
resistors depicted in the Block Diagram. The LT8315
operates similarly to traditional current-mode switchers,
except in the use of a unique sample-and-hold error amplifier, which regulates the isolated output voltage from the
sampled flyback pulse.
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LT8315
APPLICATIONS INFORMATION
Operation is as follows: when the power switch M1 turns
off, the voltage across the tertiary winding rises. The
amplitude of the flyback pulse is given as:
With a fixed value for RFB1 (such as 10kΩ) chosen, rearrangement of the expression for VOUT yields the starting
value for RFB2:
VFLBK = (VOUT + VF + ISEC • ESR) • NTS,
+V
⎛V
⎞
RFB2 = RFB1 • ⎜ OUT F • NTS − 1⎟
⎝ 1.22V
⎠
where
VF = Output diode (DOUT) forward-biased voltage
where
ISEC = Transformer secondary current
VOUT = Desired output voltage
ESR = Parasitic resistance of secondary circuit
VF = Output diode (DOUT) forward voltage ≈ 300mV
NTS = Transformer tertiary-to-secondary turns ratio
NTS = Transformer tertiary-to-secondary turns ratio
The voltage divider formed by RFB1 and RFB2 feeds a
scaled version of the flyback pulse to the FB pin, where
it is sampled and fed to the error amplifier. Because the
sample-and-hold circuit samples the voltage when the
secondary current is nearly zero, the (ISEC • ESR) term in
the VFLBK equation can be ignored.
Power up the application with the final power components
installed and the starting RFB2 value, and measure the
regulated output voltage, VOUT(MEAS). The final RFB2 value
can be adjusted to:
The internal 1.22V reference voltage feeds the non-inverting
input of the error amplifier. The high gain of the overall
loop causes the FB voltage to be nearly equal to the reference voltage. The resulting flyback voltage VFLBK can be
expressed as:
⎛ R ⎞
VFLBK = ⎜ 1+ FB2 ⎟ • 1.22V
⎝ RFB1 ⎠
Combining with the previous VFLBK equation and solving
for VOUT yields:
⎛ R ⎞ 1.22V
VOUT = ⎜ 1+ FB2 ⎟ •
− VF
⎝ RFB1 ⎠ NTS
Due to the fast nature of the flyback pulse, it is recommended to keep RFB1 between 1kΩ and 10kΩ in order to
preserve the resistor divider’s dynamic response.
RFB2(FINAL) ≈ (RFB2 + RFB1) •
VOUT
VOUT(MEAS)
− RFB1
Once the final RFB2 value is selected, the regulation accuracy from board to board for a given application will be
very consistent, typically within ±5% when including device
variation of all the components in the system (assuming
resistor tolerances and transformer windings matching
within ±1%). However, if the transformer or the output
diode is changed, or the layout is dramatically altered,
there may be some change in VOUT.
Example: Consider a 12V output supply with an output
diode whose forward voltage at nearly zero current is
300mV at room temperature. If the tertiary-to-secondary
ratio NTS is 1 and RFB1 is 10kΩ, then RFB2 is calculated
as 90.9kΩ. The application is powered up and the output
is slightly high at 12.2V, so RFB2 is adjusted to 88.7kΩ.
Output Diode Temperature Compensation
Reiterating the equation for VOUT,
Selecting the Actual RFB2 Resistor Value
The LT8315 uses a unique sampling scheme to regulate
the isolated output voltage. Due to its sampling nature,
the scheme exhibits repeatable delays and error sources,
which will affect the output voltage and force a re-evaluation
of the resistor values.
VOUT = 1+
RFB2 1.22V
•
NTS
RFB2
VF
The first term in the VOUT equation is insensitive to temperature, but the output diode forward voltage VF has a
significant negative temperature coefficient (from −1mV/°C
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to −2mV/°C). Such a temperature coefficient produces
approximately 200mV to 400mV output voltage variation
across operating temperature.
At higher output voltages, the resulting variation may be
unimportant as it represents a small fraction of the total
output. However, for lower output voltages, the diode
temperature coefficient accounts for a large output voltage error.
To correct this error, the TC pin provides a buffered
proportional-to-absolute-temperature (PTAT) voltage. At
room temperature, this voltage is equal to the internal 1.22V
reference, and it has a +4.1mV/°C temperature coefficient.
The output diode’s temperature coefficient TCF can easily
be found experimentally by applying a uniform temperature to both the output diode and the LT8315. First, RFB1
and RFB2 are adjusted to give the desired output voltage
at room temperature. The temperature is then raised or
lowered by a known amount to a new temperature, and
the diode temperature coefficient is found as:
TCF =
VOUT(25°C) − VOUT(TNEW)
TNEW – 25°C
ing a nominal TCF value (such as −1.5mV/°C) may yield
a satisfactory result.
With the output diode’s temperature coefficient known,
a resistor RTC is then attached from the TC pin to the FB
pin. Its value can be calculated as:
RTC =
−RFB2 • 4.1mV / °C
TCF • NTS
Example: If the output diode’s temperature coefficient TCF
is found experimentally to be –1.9mV/°C, then with RFB2
= 88.7kΩ, a RTC value of 191kΩ will yield a temperatureinvariant output voltage.
Sense Resistor Selection
The resistor RSNS between the SOURCE pin and GND
should be selected to provide an adequate switch current
to drive the application without exceeding the current limit
threshold.
At maximum current delivery, current limit occurs when
the SOURCE pin voltage is 100mV. In boundary mode,
the maximum output current will depend on the duty cycle
D and is given by:
where
IOUT(MAX)
100mV
• (1 D) • NPS
2 • RSNS
VOUT(25°C) = VOUT measured at room temperature
VOUT(TNEW) = VOUT measured at new temperature
where
TNEW = New temperature in Celsius
NPS = Transformer primary-to-secondary turns ratio
Alternatively, TCF can be found more accurately by measuring VOUT at two extremes of temperature and computing:
TCF = –
ΔVOUT
ΔT
D≈
( VOUT + VF ) • NPS
( VOUT + VF ) • NPS + VIN
VIN = Power supply voltage.
It should be noted that for this measurement, it is critical
that the entire board be heated or cooled uniformly, for
example by an oven. A heat gun or freeze spray will not
suffice, since the heating and cooling will not be uniform,
and dramatic temperature mismatch between the LT8315
and the output diode will cause significant error.
If no method is available to apply uniform heat or cooling,
extrapolating data from the diode’s data sheet or assum-
It should be noted that the worst-case occurs at minimum
VIN, so DVIN(MIN) should be calculated assuming VIN =
VIN(MIN). Solving for the sense resistor value:
RSNS =
1− DVIN(MIN)
IOUT(MAX)
• 50mV • NPS • 80%
A factor of 80% is introduced to compensate for system
delays and tolerances, but it may need adjustment for the
final application.
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Example: A 12V output voltage is generated from a VIN =
350V input that can drop as low as VIN(MIN) = 250V. If a
transformer with primary-to-secondary turns ratio NPS =
10 is selected and it is to supply a maximum output current IOUT(MAX) = 750mA, then the duty cycle is DVIN(MIN) ≈
33% and the sense resistor is calculated RSNS = 356mΩ.
A 330mΩ resistor is selected.
A more accurate value for RSNS can be obtained by finding
D experimentally with an oscilloscope and electronic load.
Output Power
Compared with a buck or a boost converter, a flyback
converter has a complicated relationship between the input
and output currents. Boost converters have relatively constant maximum input current regardless of input voltage,
while buck converters have relatively constant maximum
output current regardless of input voltage, owing to the
fact that they have continuous input and output currents
respectively. A flyback converter, however, has both
discontinuous input and output currents. The duty cycle
affects both input and output currents, making it hard to
predict maximum output power.
The graphs in Figure 1 through Figure 4 show the typical
maximum output power possible for the output voltages
5V, 12V, 24V and 48V. The maximum output power curve
is the calculated output power if the switch voltage is 510V
during the switch-off time. 120V of margin is left for the
leakage inductance voltage spike. To achieve this power
level at a given input, a winding ratio must be calculated
to stress the switch to 510V, resulting in some odd ratio
values. The curves below the maximum output power
curve are examples of common winding ratio values and
the amount of output power at given input voltages.
16
14 THEORETICAL
MAXIMUM
12
MAXIMUM OUTPUT POWER (W)
MAXIMUM OUTPUT POWER (W)
16
NPS = 40
10
NPS = 20
8
6
NPS = 10
4
NPS = 5
2
0
0
100
200
300
VIN (V)
400
NPS = 20
NPS = 10
8
6
NPS = 5
4
NPS = 2
2
0
100
8315 F01
200
300
VIN (V)
400
500
8315 F02
Figure 2. Maximum Power, VOUT = 12V
16
16
14 THEORETICAL
MAXIMUM
12
10
NPS = 10
MAXIMUM OUTPUT POWER (W)
MAXIMUM OUTPUT POWER (W)
10
0
500
Figure 1. Maximum Power, VOUT = 5V
NPS = 5
8
6
NPS = 2
4
NPS = 1
2
0
14 THEORETICAL
MAXIMUM
12
0
100
200
300
VIN (V)
400
500
14 THEORETICAL
MAXIMUM
12
10
8
NPS = 2
6
NPS = 1
4
NPS = 0.5
2
0
0
8315 F03
Figure 3. Maximum Power, VOUT = 24V
NPS = 5
100
200
300
VIN (V)
400
500
8315 F04
Figure 4. Maximum Power, VOUT = 48V
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Table 1. Predesigned Transformers — Typical Specifications
TRANSFORMER PART
NUMBER
LPRI
(mH)
NP:NS:NT
ISOLATION
VENDOR
TARGET APPLICATIONS
PS16-077
4
24:1:4
Reinforced
Sumida
140V–380V to 5V/1.5A
PS16-051
4
10:1:2
Reinforced
Sumida
140V–380V to 12V/0.6A
PS15-195
4
3:1:1
Reinforced
Sumida
100V–500V to 12V/0.2A
PS16-078
4
5:1:1
Reinforced
Sumida
140V–380V to 24V/0.3A
750316022
3.3
24:1:4
Functional
Wurth
140V–380V to 5V/1.5A
7508111324
2.75
10:1:1
Reinforced
Wurth
140V–380V to 12V/0.6A
7508111518
2.4
2.5:1:0.25
Reinforced
Wurth
140V–380V to 48V/0.15A
The following equation calculates output power:
Flyback Transformer Modeling
POUT = 0.5 • η • VIN • D • ISW(MAX)
A flyback transformer can be thought of as an ideal transformer with a parallel magnetizing inductance and series
leakage inductances, as shown in Figure 5.
where
η = Efficiency ≈ 80%
LLEAK(PRI)
( VOUT + VF ) • NPS
D≈
( VOUT + VF ) • NPS + VIN
NPS :1
LLEAK(SEC)
LPRI
ISW(MAX) = Max. switch current limit = 100mV/RSNS
The calculated power is approximate, and does not take
into account timing variations caused by circuit parasitics.
The actual output power must be evaluated on the bench.
Example: Consider a 12V output converter with a VIN(MIN)
of 250V and a VIN(MAX) of 390V. With a ten-to-one primaryto-secondary winding ratio NPS = 10 and a sense resistor
RSNS = 330mΩ, the maximum power output is 11W at
VIN(MAX) = 390V but lowers to 10W at VIN(MIN) = 250V.
Selecting a Transformer
Transformer specification and design is possibly the most
critical part of successfully applying the LT8315. In addition
to the usual list of guidelines dealing with high-frequency
isolated power supply transformer design, the following
information should be carefully considered.
Linear Technology has worked with several leading magnetic component manufacturers to produce pre-designed
flyback transformers for use with the LT8315. Table 1
shows the details of these transformers.
8315 F05
IDEAL
Figure 5. Transformer Model
The magnetizing inductance, which is the mutual inductance shared by both primary and secondary windings, is
essential for absorbing energy and delivering it to the load.
It stores energy in magnetic flux lines that pass through
both primary and secondary windings.
If the leakage inductances are small, the magnetizing
inductance can be measured by leaving the secondary
open-circuited and measuring the inductance of the primary, resulting in an inductance LPRI. The magnetizing
inductance can also be measured from the secondary
by leaving the primary open-circuited and measuring the
secondary inductance LSEC. The relationship between the
primary-referred magnetizing inductance and secondaryreferred magnetizing inductance is given by the primaryto-secondary turns ratio NPS as:
LPRI = LSEC • NPS2
The transformer also has leakage inductances, which are
parasitic inductances associated with each winding. These
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inductances store energy in magnetic flux lines which “leak”
out of the magnetic core and do not pass through both
windings, and therefore represent self-inductances whose
energy cannot be transferred through the transformer. As
such, they contribute to energy loss and reduced converter
efficiency.
If the leakage inductances are small, the combined leakage inductance can be measured by short-circuiting the
secondary and measuring the primary inductance. This
results in a primary-referred inductance,
LLEAK = LLEAK(PRI) + LLEAK(SEC) • NPS2
The leakage inductance and magnetizing inductance are
related by the coupling coefficient k according to the
relation:
k=
L PRI
L PRI + L LEAK / 2
Coupling coefficients of k=99% are common, and are a
function of transformer construction and materials. Increased voltage isolation between primary and secondary
is often desired for safety purposes, but generally reduces
the coupling coefficient and increases leakage inductance.
Bifilar windings maximize the coupling coefficient, but are
often undesirable because of their minimal isolation and
increased primary-to-secondary capacitance. In the end,
a reasonable trade-off between isolation and coupling
coefficient must be made.
Magnetizing Inductance Requirement
The appropriate magnetizing inductance depends on the
LT8315’s minimum switch-on time, its minimum switchoff time, and output power.
The conduction of secondary current reflects the output
voltage onto the tertiary winding during the flyback pulse.
The LT8315 obtains output voltage information from the
reflected output voltage on the FB pin. The sample-andhold error amplifier needs a minimum of 800ns to settle
and sample the reflected output voltage. In order to ensure
proper sampling, the secondary winding needs to conduct
current for at least 800ns.
The minimum value for primary-side magnetizing inductance is given by:
LPRI ≥
tOFF(MIN) • NPS • ( VOUT + VF )
ISW(MIN)
where
tOFF(MIN) = Minimum switch-off time = 800ns
ISW(MIN) = Minimum switch current limit = 20mV/RSNS
The LT8315 has a minimum switch-on time that prevents
the chip from turning on the power switch for a period
shorter than 250ns in order to blank the initial switch
turn-on current spike. If the inductor current exceeds the
minimum switch current limit during that time, the minimum load current will increase. Therefore, the following
equation must also be observed:
LPRI ≥
tON(MIN) • VIN(MAX)
ISW(MIN)
where
tON(MIN) = Minimum Switch-On Time = 250ns
Additionally, the magnetizing inductance must be large
enough to provide sufficient power to the output when the
LT8315 operates at maximum frequency. This creates a
third requirement for magnetizing inductance:
LPRI
2 • (VOUT + VF ) •IOUT(MAX)
•ISW(MAX)2 • fSW(MAX)
where
ISW(MAX) = Maximum switch current = 100mV/RSNS
IOUT(MAX) = Maximum load current
fSW(MAX) = Maximum switching frequency = 140kHz
η = Efficiency ≈ 80%
In general, choose a transformer with its primary magnetizing inductance about 20% to 50% larger than the
minimum values calculated above.
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Example: For a 12V/750mA output converter with VIN(MAX)
= 390V, VF = 300mV, NPS = 10, and RSNS = 330mΩ, the
first equation requires LPRI ≥ 1.64mH, the second equation
requires LPRI ≥ 1.61mH, and the third equation requires
LPRI ≥ 1.83mH. A reasonable standard value for primary
inductance is LPRI = 2.2mH.
Saturation Current
The current in the transformer windings should not exceed
its rated saturation current. Beyond its saturation value, the
inductance drops and the current rises to an uncontrolled
value, causing extra power dissipation and possible failure.
Choose a transformer whose primary saturation current is
at least 30% greater than ISW(MAX), which is 100mV/RSNS.
Turns Ratios
Typically, choose the transformer primary-to-secondary
turns ratio NPS to maximize available output power. For low
output voltages, a larger NPS ratio can be used to maximize
the transformer’s current gain. However, remember that
the DRAIN pin sees a voltage that is equal to VIN plus the
output voltage multiplied by NPS. Additionally, leakage
inductance will cause a voltage spike (VLEAKAGE) that
adds to this reflected voltage. This total quantity needs to
remain below the 630V absolute maximum rating of the
DRAIN pin to prevent breakdown of the internal power
switch. Together these conditions place an upper limit on
the turns ratio NPS for a given application. Choose a turns
ratio low enough to ensure:
NPS <
630V − VIN(MAX) − VLEAKAGE
VOUT + VF
For producing high output voltages, a low ratio NPS may
be used. However, the multiplied capacitance presented
to the DRAIN node may cause ringing that exceeds the
250ns tON(MIN), causing light-load instability. Fully evaluate
these applications before use with the LT8315.
During operation, the LT8315 derives its power from
a tertiary winding through its BIAS pin. BIAS must be
maintained between 10V and 40V for proper operation.
This dictates a tertiary-to-secondary turns ratio NTS of:
10V
VOUT
< N TS <
40V
VOUT
Example: For VOUT = 12V, NTS must lie between 0.83
and 3.33, or a 5:6 and 10:3 tertiary-to-secondary ratio
respectively.
Because the output voltage is measured through the voltage appearing on the third winding, NTS directly affects
the output voltage regulation accuracy. For best results,
make sure the transformer is manufactured with a precise
turns ratio specified within ±1%.
Leakage Inductance and Snubbers
Any leakage inductance on either the primary or secondary
windings causes a voltage spike to appear on the primary
after the power switch turns off. This spike is increasingly
prominent at higher load currents where more energy is
stored in the leakage inductance. This energy cannot be
delivered to the load, and must be dissipated as heat. It
is thus very important to minimize transformer leakage
inductance.
When designing an application, adequate margin should
be kept for the worst-case leakage voltage spikes even
under overload conditions. In most cases, the reflected
output voltage on the primary plus VIN should be kept below 510V, as shown in Figure 6. This leaves 120V margin
for the leakage spike across line and load conditions. A
larger voltage margin will be required for poorly wound
transformers with excessive leakage inductance.
In addition to the voltage spikes, the leakage inductance
also causes the DRAIN pin to ring for a while after the
power switch turns off. To prevent the voltage ringing from
falsely triggering the boundary mode detector, the LT8315
internally blanks the boundary mode detector for 800ns.
Any ringing after 800ns may trigger the power switch
to turn back on again before the secondary current falls
to zero, so the leakage inductance spike and associated
ringing should be limited to less than 800ns.
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