LTC1041
BANG-BANG Controller
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FEATURES
■
■
■
■
■
■
■
DESCRIPTIO
The LTC®1041 is a monolithic CMOS BANG-BANG
controller manufactured using Linear Technology’s
enhanced LTCMOS™ silicon gate process. BANG-BANG
loops are characterized by turning the control element
fully ON or fully OFF to regulate the average value of
the parameter to be controlled. The SET POINT input
determines the average control value and the DELTA input
sets the deadband. The deadband is always 2 x DELTA and
is centered around the SET POINT. Independent control
of the SET POINT and deadband, with no interaction, is
made possible by the unique sampling input structure of
the LTC1041.
Micropower 1.5µW (1 Sample/Second)
Wide Supply Range 2.8V to 16V
High Accuracy
Guaranteed SET POINT Error ±0.5mV Max
Guaranteed Deadband ±0.1% of Value Max
Wide Input Voltage Range V + to Ground
TTL Outputs with 5V Supply
Two Independent Ground-Referred Control Inputs
Small Size 8-Pin SO
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APPLICATIO S
■
■
■
■
An external RC connected to the OSC pin sets the sampling
rate. At the start of each sample, internal power to the
analog section is switched on for ≈ 80µs. During this time,
the analog inputs are sampled and compared. After the
comparison is complete, power is switched off. This
achieves extremely low average power consumption
at low sampling rates. CMOS logic holds the output
continuously while consuming virtually no power.
Temperature Control (Thermostats)
Motor Speed Control
Battery Charger
Any ON-OFF Control Loop
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
To keep system power at an absolute minimum, a switched
power output (VP-P) is provided. External loads, such as
bridge networks and resistive dividers, can be driven by
this switched output.
The output logic sense (i.e., ON = V+) can be reversed
(i.e., ON = GND) by interchanging the VIN and SET POINT
inputs. This has no other effect on the operation of
the LTC1041.
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TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
Ultralow Power 50°F to 100°F (2.4µW) Thermostat
10000
26V AC 2-WIRE THERMOSTAT
56Ω
1000
4.99k
4.32k
5k
2N6660
1
8
2
7
3
LTC1041
4
†
6
10M
IS
400nA
+
5
6.81k
1N4002
(4)
6V
1µF
DELTA = 0.5°F
100
TOTAL SUPPLY
CURRENT
10
1
LTC1041 SUPPLY
CURRENT
0.1
49.9Ω
†
SUPPLY CURRENT, IS (µA)
0.1µF
VS = 6V
LTC1041 • TA01
ALL RESISTORS 1%.
YELLOW SPRINGS INSTRUMENT CO., INC. P/N 44007.
DRIVING THERMISTOR WITH VP-P ELIMINATES 3.8°F ERROR DUE TO SELF-HEATING
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY, fS (Hz)
10000
LTC1041 • TA02
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LTC1041
W W
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PACKAGE/ORDER I FOR ATIO
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ABSOLUTE
RATI GS
(Note 1)
TOP VIEW
Total Supply Voltage (V + to V –) .............................. 18V
Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V)
Operating Temperature Range
LTC1041C ......................................... –40°C to 85°C
LTC1041M (OBSOLETE) .................. – 55°C to125°C
Storage Temperature Range ................. – 55°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Output Short Circuit Duration ....................... Continuous
ON / OFF
1
8
V+
ORDER PART
NUMBER
VIN
2
7
VP-P
SET POINT
3
6
OSC
GND
4
5
DELTA
LTC1041CN8
LTC1041CS8
N8 PACKAGE
S8 PACKAGE
8-LEAD PDIP
8-LEAD PDIP
TJMAX = 110°C, θJA = 150°C/W (N8)
TJMAX = 150°C, θJA = 150°C/W (S8)
J8 PACKAGE
8-LEAD CERDIP
TJMAX = 150°C, θJA = 100°C/W
LTC1041MJ8
OBSOLETE PACKAGE
Consider the N8 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test Conditions: V+ = 5V, unless otherwise specified.
SYMBOL
PARAMETER
SET POINT Error (Note 3)
CONDITIONS
V + = 2.8V to 6V (Note 2)
MIN
●
V + = 6V to 15V (Note 2)
●
Deadband Error (Note 4)
V + = 2.8V to 6V (Note 2)
●
V + = 6V to 15V (Note 2)
●
IOS
Input Current
RIN
Equivalent Input Resistance
Input Voltage Range
Power Supply Range
Power Supply ON
Current (Note 6)
Power Supply OFF
Current (Note 6)
Response Time (Note 7)
ON/OFF Output (Note 8)
Logical “1” Output Voltage
Logical “0” Output Voltage
External Timing Resistor
Sampling Frequency
PSR
IS(ON)
IS(OFF)
tD
VOH
VOL
REXT
fS
V + = 5V, T
A = 25°C, OSC = GND
(VIN, SET POINT and DELTA Inputs)
fS = 1kHz (Note 5)
LTC1041C
LTC1041M
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
% of DELTA
mV
% of DELTA
% of DELTA
nA
16
3
●
●
0.001
0.001
80
0.5
5
100
µA
µA
µs
0.4
10,000
V
V
kΩ
Hz
V + = 5V
60
V + = 4.75V, IOUT = –360µA
V + = 4.75V, IOUT = 1.6mA
Resistor Connected between V+ and OSC Pin
V + = 5V, TA = 25°C,
REXT = 1M CEXT = 0.1µF
% of DELTA
mV
1.2
●
V + = 5V, VP-P OFF
UNITS
mV
●
●
V + = 5V, VP-P ON
MAX
±0.5
+
±0.1
±3
+
±0.1
±1
+
±0.2
±6
+
±0.2
MΩ
V
V
mA
●
10
GND
2.8
TC1041M/LTC1041C
TYP
±0.3
+
±0.05
±1
+
±0.05
±0.6
+
±0.1
±2
+
±0.1
±0.3
●
●
2.4
15
V+
4.4
0.25
100
5
Note 2: Applies over input voltage range limit and includes gain
uncertainty.
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2
LTC1041
ELECTRICAL CHARACTERISTICS
Note 3: SET POINT error ≡
( VU 2+ VL ) – SET POINT
where VU = upper band limit and VL = lower band limit.
Note 4: Deadband error ≡ (VU – VL) – 2 • DELTA where VU = upper band
limit and VL = lower band limit.
Note 5: RIN is guaranteed by design and is not tested.
RIN = 1/(fS x 66pF).
Note 6: Average supply current = tD • IS(ON) • fS + (1 – tD • fS) lS(OFF).
Note 7: Response time is set by an internal oscillator and is independent
of overdrive voltage. tD = VP-P pulse width.
Note 8: Output also capable of meeting EIA/JEDEC standard B series
CMOS drive specifications.
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TYPICAL PERFOR A CE CHARACTERISTICS
Normalized Sampling
Frequency vs V +, Temperature
IS(ON) vs V+
2.2
NORMALIZED SAMPLING FREQUENCY
(fS AT 5V, 25°C)
18
16
12
25°C
10
–55°C
8
6
125°C
4
2
R = 1M, C = 0.1µF
CEXT = 1000pF
1.8
TA = 125°C
1.6
1.4
1.2
TA = 25°C
1.0
10
8
6
12
SUPPLY VOLTAGE, V+ (V)
14
16
0
8
10 12
4
6
SUPPLY VOLTAGE, V+ (V)
2
CEXT = 0.05µF
CEXT = 0.1µF
1
16
14
0.1
100k
1M
REXT (Ω)
10M
LTC1041 • TPC03
LTC1041 • TPC02
LTC1041 • TPC01
Response Time
vs Temperature
Response Time
vs Supply Voltage
300
10
CEXT = 0.01µF
CEXT = 1µF
130
TA = 25°C
V+ = 5V
120
250
RESPONSE TIME, t D (µs)
4
102
0.8
TA = – 55°C
2
Sampling Rate vs REXT, CEXT
2.0
0.6
0
RESPONSE TIME, tD (µs)
IS(ON) (mA)
14
103
SAMPLE RATE, fS (Hz)
20
200
150
100
50
110
100
90
80
70
60
50
0
2
4
10
14
8
12
6
SUPPLY VOLTAGE, V+ (V)
16
LTC1041 • TPC04
40
–50
0
25
–25
75 100
50
AMBIENT TEMPERATURE, TA (°C)
125
LTC1041 • TPC05
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LTC1041
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TYPICAL PERFOR A CE CHARACTERISTICS
RIN vs Sampling Frequency
AVERAGE INPUT RESISTANCE, RIN (1/fS • 66pF) (Ω)
TYPICAL OUTPUT VOLTAGE DROP (V+ – VP-P) (V)
VP-P Output Voltage
vs Load Current
0
0.2
0.4
V+ = 16V
0.6
V+
0.8
1.0
= 10V
V+ = 2.8V
1.2
1.4
V+ = 5V
1.6
1.8
2.0
1
0
2
3 4 5 6 7 8
LOAD CURRENT, IL (mA)
9
10
11
10
1010
109
108
107
10
102
103
SAMPLING FREQUENCY fS (Hz)
1
104
LTC1041 • TPC07
LTC1041 • TPC06
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APPLICATIO S I FOR ATIO
The LTC1041 uses sampled data techniques to achieve
its unique characteristics. It consists of two comparators,
each of which has two differential inputs (Figure 1a).
When the sum of the voltages on a comparator’s inputs is
positive, the output is high and when the sum is negative,
the output is low. The inputs are interconnected such that
the R S flip-flop is reset (ON/OFF = GND) when
VIN > (SET POINT + DELTA) and is set (ON/OFF = V+) when
VIN < (SET POINT – DELTA). This makes a very precise
hysteresis loop of 2 • DELTA centered around the
SET POINT. (See Figure 1b.)
For RS < 10kΩ
VIN
(2)
+
–
+
–
V+
(8)
COMP A
ON/OFF
(1)
4
The dual differential input structure is made with CMOS
switches and a precision capacitor array. Input
impedance characteristics of the LTC1041 can be
determined from the equivalent circuit shown in Figure 2.
The input capacitance will charge with a time constant of
SET POINT
DELTA
(5)
V+
+
–
+
–
DELTA – + DELTA
ON/OFF OUTPUT
SET POINT
(3)
COMP B
GND
(4)
4
CEXT
DEADBAND
V+
REXT
OSC
(6)
V+
TIMING
GENERATOR
VP-P
CIRCUIT
VP-P
(7)
GND
0V
POWER ON
VU
VL
INPUT VOLTAGE, VIN
80µs
LTC1041 • AI01a
(a)
LTC1041 • AI01b
(b)
Figure 1. LTC1041 Block Diagram
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LTC1041
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APPLICATIO S I FOR ATIO
CIN
(≈ 33pF)
S1
RS
The input switches of the LTC1041 are capable of
switching either to the V+ supply or ground. Consequently,
the input voltage range includes both supply rails. This is
a further benefit of the sampling input structure.
+
VIN
CS
S2
–
Input Voltage Range
V–
LTC1041 DIFFERENTIAL INPUT
LTC1041 • AI01
Figure 2. Equivalent Input Circuit
RS • CIN. The ability to fully charge CIN from the signal
source during the controller’s active time is critical in
determining errors caused by the input charging current.
For source resistances less than 10kΩ, CIN fully charges
and no error is caused by the charging current.
For RS > 10kΩ
For source resistances greater than 10kΩ, CIN cannot fully
charge, causing voltage errors. To minimize these errors,
an input bypass capacitor, CS, should be used. Charge is
shared between CIN and CS, causing a small voltage error.
The magnitude of this error is AV = VIN • CIN (CIN + CS). This
error can be made arbitrarily small by increasing CS.
The averaging effect of the bypass capacitor, CS, causes
another error term. Each time the input switches cycle
between the plus and minus inputs, CIN is charged and
discharged. The average input current due to this is
IAVG = VIN • CIN • fS, where fS is the sampling frequency.
Because the input current is directly proportional to the
differential input voltage, the LTC1041 can be said to have
an average input resistance of RIN = VIN/IAVG = I/(fS • CIN).
Since two comparator inputs are connected in parallel, RIN
is one half of this value (see typical curve of RIN versus
Sampling Frequency). This finite input resistance causes
an error due to the voltage divider between RS and RIN.
The input voltage error caused by both of these effects is
VERROR = VIN [2CIN/(2CIN + CS) + RS/(RS + RIN)].
Example: assume fS = 10Hz, RS = 1M, CS = 1µF, VIN = 1V,
VERROR = 1V(66µV + 660µV) = 726µV. Notice that most of
the error is caused by RIN. If the sampling frequency is
reduced to 1Hz, the voltage error from the input
impedance effects is reduced to 136µV.
Error Specifications
The only measurable errors on the LTC1041 are the
deviations from “ideal” of the upper and lower switching
levels (Figure 1b). From a control standpoint, the error in
the SET POINT and deadband is critical. These errors may
be defined in terms of VU and VL.
V +V
SET POINT error ≡ U L – SET POINT
2
deadband error ≡ ( VU – VL ) – 2 • DELTA
The specified error limits (see electrical characteristics)
include error due to offset, power supply variation, gain,
time and temperature.
Pulsed Power (VP-P) Output
It is often desirable to use the LTC1041 with resistive
networks such as bridges and voltage dividers. The power
consumed by these resistive networks can far exceed that
of the LTC1041 itself.
At low sample rates the LTC1041 spends most of its time
off. A switched power output, VP-P, is provided to drive the
input network, reducing its average power as well. VP-P is
switched to V+ during the controller’s active time (≈ 80µs)
and to a high impedance (open circuit) when internal
power is switched off.
Figure 3 shows the VP-P output circuit. The VP-P output
voltage is not precisely controlled when driving a load
(see typical curve of VP-P Output Voltage vs Load Current).
In spite of this, high precision can be achieved in two ways:
(1) driving ratiometric networks and (2) driving fast settling references.
In ratiometric networks all the inputs are proportional to
VP-P (Figure 4). Consequently, the absolute value of VP-P
does not affect accuracy.
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5
LTC1041
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APPLICATIO S I FOR ATIO
V+
8
Q1
In applications where an absolute reference is required,
the VP-P output can be used to drive a fast settling
reference. The LTC1009 2.5V reference settles in ≈ 2µs
and is ideal for this application (Figure 5). The current
through R1 must be large enough to supply the LT1009
minimum bias current (≈ 1mA) and the load current, IL.
P1
80µs
COMPARATOR ON TIME
4
GND
7
VP-P
LTC1041 • AI03
Internal Oscillator
Figure 3. VP-P Output Switch
V+
R1
1
R3
R5
VIN 2
R4
R6
SET POINT 3
8
7 VP-P
LTC1041
6
GND 4
R2
5 DELTA
LTC1041 • AI04
Figure 4. Ratiometric Network Driven by VP-P
V+
R1
8
1
IL
R2
R3
7
2
VIN
SET POINT 3
4
LTC1041
6
5 DELTA
LT1009-2.5
R4
LTC1041 • AI05
Figure 5. Driving Reference with VP-P Output
If the best possible performance is needed, the inputs to
the LTC1041 must completely settle within 4µs of the start
of the comparison cycle (VP-P high impedance to V +
transition). Also, it is critical that the input voltages do not
change during the 80µs active time. When driving resistive
input networks with VP-P, capacitive loading should be
minimized to meet the 4µs settling time requirement.
Further, care should be exercised in layout when driving
networks with source impedances, as seen by the LTC1041,
of greater than 10kΩ (see For RS > 10kΩ).
An internal oscillator allows the LTC1041 to strobe itself.
The frequency of the oscillation, and hence the sampling
rate, is set with an external RC network (see typical curve,
Sampling Rate REXT, CEXT). REXT and CEXT are connected
as shown in Figure 1. To assure oscillation, REXT must be
between 100kΩ and 10MΩ. There is no limit to the size of
CEXT.
At low sampling rates, REXT is very important in
determining the power consumption. REXT consumes
power continuously. The average voltage at the OSC pin
is approximately V+/2, giving a power dissipation of
PREXT = (V+/ 2)2/REXT.
Example: assume REXT = 1MΩ, V+ = 5V, PREXT =
(2.5)2/106 = 6.25/µW. This is approximately four times the
power consumed by the LTC1041 at V+ = 5V and
fS = 1 sample/second. Where power is a premium,
REXT should be made as large as possible. Note that the
power dissipated by REXT is not a function of fS or CEXT.
If high sampling rates are needed and power consumption
is of secondary importance, a convenient way to get the
maximum possible sampling rate is to make REXT = 100kΩ
and CEXT = 0. The sampling rate, set by the controller’s
active time, will nominally be ≈ 10kHz.
To synchronize the Sampling of the LTC1041 to an
external frequency source, the OSC pin can be driven by a
CMOS gate. A CMOS gate is necessary because the input
trip points of the oscillator are close to the supply rails and
TTL does not have enough output swing. Externally driven,
there will be a delay from the rising edge of the OSC input
and the start of the sampling cycle of approximately 5µs.
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LTC1041
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TYPICAL APPLICATIO S
Motor Speed Controller
V+
100k
10k
1N4002
MOTOR*
TACH
V+
1.1k
2N6387
1
8
2
7
3
LTC1041
4
LT1009
320k
24k
6
5
320pF
20k
500Ω
DEADBAND
3k
SPEED
DEMAND
LTC1041 • TA03
*CANNON CKT26-T5-3SAE
Battery Charger
89
GE 106B†
74C00
OUT LT1019-5 IN
5V
74C00
+
1N4002
100µF
24V
1A
115VAC
60 Hz
UTC D0T20
V+
12V
LEAD
ACID
100k
36.5k
40k
2kΩ
1
8
2
7
3
4
2.21k
10k
LTC1041
1N4002
74C00
6
5
0.1µF
1N4022
13Ω
†SCR FIRES AT ZERO CROSSING.
* SET BATTERY VOLTAGE. BATTERY IS
MEASURED WITH ZERO CHARGE CURRENT
LTC1041 • TA04
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
LTC1041
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PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
CORNER LEADS OPTION
(4 PLCS)
.300 BSC
(7.62 BSC)
.008 – .018
(0.203 – 0.457)
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION
.045 – .068
(1.143 – 1.650)
FULL LEAD
OPTION
0° – 15°
.015 – .060
(0.381 – 1.524)
.405
(10.287)
MAX
.005
(0.127)
MIN
.200
(5.080)
MAX
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NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
5
.025
(0.635)
RAD TYP
.220 – .310
(5.588 – 7.874)
1
.045 – .065
(1.143 – 1.651)
6
7
2
3
4
J8 0801
.125
3.175
MIN
.100
(2.54)
BSC
OBSOLETE PACKAGE
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
.400*
(10.160)
MAX
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
)
8
7
6
1
2
3
5
.255 ± .015*
(6.477 ± 0.381)
.120
(3.048) .020
MIN
(0.508)
MIN
.018 ± .003
.100
(2.54)
BSC
4
N8 1002
(0.457 ± 0.076)
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
8
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.050
(1.270)
BSC
7
6
.045 ±.005
.050 BSC
5
N
N
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN
.160 ±.005
N/2
1
1
2
3
4
.030 ±.005
TYP
2
3
N/2
RECOMMENDED SOLDER PAD LAYOUT
SO8 0502
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Linear Technology Corporation
LW/TP 1202 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1985
工商网监
湘ICP备2023018690号
