LTC1152
Rail-to-Rail Input
Rail-to-Rail Output
Zero-Drift Op Amp
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DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
■
Input Common-Mode Range Includes Both Rails
Output Swings Rail to Rail
Output Will Drive 1kΩ Load
No External Components Required
Input Offset Voltage: 10µV Max
Input Offset Drift: 100nV/°C Max
Minimum CMRR: 115dB
Supply Current: 3.0mA Max
Shutdown Pin Drops Supply Current to 5µA Max
Output Configurable to Drive Any Capacitive Load
Operates from 2.7V to 14V Total Supply Voltage
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APPLICATI
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S
Rail-to-Rail Amplifiers and Buffers
High Resolution Data Acquisition Systems
Supply Current Sensing in Either Rail
Low Supply Voltage Transducer Amplifiers
High Accuracy Instrumentation
Single Negative Supply Operation
The LTC®1152 is a high performance, low power zero-drift
op amp featuring an input stage that common modes to
both power supply rails and an output stage that provides
rail-to-rail swing, even into heavy loads. The wide input
common-mode range is achieved with a high frequency
on-board charge pump. This technique eliminates the
crossover distortion and limited CMRR imposed by competing technologies. The LTC1152 is a C-LoadTM of amp,
enabling it to drive any capacitive load.
The LTC1152 shares the excellent DC performance specs
of LTC’s other zero-drift amplifiers. Typical offset voltage
is 1µV and typical offset drift is 10nV/°C. CMRR and PSRR
are 130dB and 120dB and open-loop gain is 130dB. Input
noise voltage is 2µVP-P from 0.1Hz to 10Hz. Gain-bandwidth product is 0.7MHz and slew rate is 0.5V/µs, all with
supply current of 3.0mA max over temperature. The
LTC1152 also includes a shutdown feature which drops
supply current to 1µA and puts the output stage in a high
impedance state.
The LTC1152 is available in 8-pin PDIP and 8-pin SO
packages and uses the standard op amp pinout, allowing
it to be a plug-in replacement for many standard op amps.
, LTC and LT are registered trademarks of Linear Technology Corporation.
C-Load is trademark of Linear Technology Corporation.
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TYPICAL APPLICATI
Input and Output Waveforms
Rail-to-Rail Buffer
5V
5V
2
–
3
+
7
LTC1152
IN
VOUT
2V/DIV
6
OUT
0V
5V
VIN
2V/DIV
4
1152 TA01
0V
1152 TA02
1
LTC1152
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
Total Supply Voltage (V + to V –) ............................. 14V
Input Voltage ............................ V + + 0.3V to V – – 0.3V
Output Short-Circuit Duration (Pin 6) ............. Indefinite
Operating Temperature Range
LTC1152C............................................... 0°C to 70°C
LTC1152I.......................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
SHDN 1
8
CP
–IN 2
7
V+
+IN 3
6
OUT
V– 4
5
COMP
LTC1152CN8
LTC1152CS8
LTC1152IN8
LTC1152IS8
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
1152
1152I
TJMAX = 110°C, θJA = 130°C/ W (N8)
TJMAX = 110°C, θJA = 200°C/ W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VS = 5V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
VOS
Input Offset Voltage
CONDITIONS
TA = 25°C (Note 1)
∆VOS
(Note 1)
Average Input Offset Drift
MIN
●
Input Bias Current
MAX
±10
UNITS
µV
±10
±100
nV/°C
±50
Long-Term Offset Drift
IB
TYP
±1
TA = 25°C (Note 2)
±100
±1000
pA
pA
±20
±200
±500
pA
pA
2
0.5
3
1
●
IOS
Input Offset Current
TA = 25°C (Note 2)
●
en
Input Noise Voltage (Note 3)
RS = 100Ω, 0.1Hz to 10Hz
RS = 100Ω, 0.1Hz to 1Hz
in
Input Noise Current
f = 10Hz
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
PSRR
Power Supply Rejection Ratio
VS = 3V to 12V
nV/√Mo
±10
µVP-P
µVP-P
0.6
fA/√Hz
●
115
130
dB
110
105
120
●
dB
dB
AVOL
Large-Signal Voltage Gain
RL = 10k, VOUT = 0.5V to 4.5V
●
110
130
dB
VOUT
Maximum Output Voltage Swing (Note 4)
RL = 1k, VS = Single 5V
RL = 1k, VS = ±2.5V
RL = 100k, VS = ±2.5V
●
●
4.0
±2.0
4.4
2.2
±2.49
V
V
V
SR
Slew Rate
RL = 10k, CL = 50pF, VS = ±2.5V
GBW
Gain-Bandwidth Product
RL = 10k, CL = 50pF, VS = ±2.5V
IS
Supply Current
No Load
Shutdown = 0V
●
●
2.2
1
3.0
5
mA
µA
IOSD
Output Leakage Current
Shutdown = 0V
●
±10
±100
nA
VCP
Charge Pump Output Voltage
ICP = 0
VIL
Shutdown Pin Input Low Voltage
VIH
Shutdown Pin Input High Voltage
IIN
Shutdown Pin Input Current
fCP
Internal Charge Pump Frequency
TA = 25°C
4.7
MHz
fSMPL
Internal Sampling Frequency
TA = 25°C
2.3
kHz
2
0.5
V/µs
0.7
MHz
7.3
V
2.5
V
4
VSHDN = 0V
●
–1
V
–5
µA
LTC1152
ELECTRICAL CHARACTERISTICS
VS = 3V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
VOS
Input Offset Voltage
CONDITIONS
TA = 25°C (Note 1)
∆VOS
Average Input Offset Drift
(Note 1)
IB
Input Bias Current
TA = 25°C (Note 2)
MIN
●
TYP
±1
MAX
±10
UNITS
µV
±10
±100
nV/°C
±5
±100
±1000
pA
pA
±10
±200
±500
pA
pA
●
IOS
Input Offset Current
TA = 25°C (Note 2)
●
en
Input Noise Voltage (Note 3)
RS = 100Ω, 0.1Hz to 10Hz
RS = 100Ω, 0.1Hz to 1Hz
2
0.75
µVP-P
µVP-P
in
Input Noise Current
f = 10Hz
0.6
fA/√Hz
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 3V
●
130
dB
AVOL
Large-Signal Voltage Gain
RL = 10k, VOUT = 0.5V to 2.5V
●
106
130
dB
VOUT
Maximum Output Voltage Swing (Note 4)
RL = 1k, VS = Single 3V
RL = 100k, VS = ±1.5V
●
2.0
2.5
±1.48
V
V
SR
Slew Rate
RL = 10k, CL = 50pF, VS = ±1.5V
0.4
V/µs
GBW
Gain-Bandwidth Product
RL = 10k, CL = 50pF, VS = ±1.5V
0.5
MHz
IS
Supply Current
No Load
Shutdown = 0V
●
●
1.8
1
IOSD
Output Leakage Current
Shutdown = 0V
●
±10
nA
VCP
Charge Pump Output Voltage
ICP = 0
4.5
V
VIL
Shutdown Pin Input Low Voltage
1.2
V
VIH
Shutdown Pin Input High Voltage
2.3
V
IIN
Shutdown Pin Input Current
VSHDN = 0V
–1
µA
fCP
Internal Charge Pump Frequency
TA = 25°C
4.2
MHz
fSMPL
Internal Sampling Frequency
TA = 25°C
2.1
kHz
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels during automated testing.
Note 2: At T ≤ 0°C these parameters are guaranteed by design and not
tested.
Note 3: 0.1Hz to 10Hz noise is specified DC coupled in a 10-sec window;
0.1Hz to 1Hz noise is specified in a 100-sec window with an RC highpass
2.5
5
mA
µA
filter at 0.1Hz. Contact LTC factory for sample tested or 100% tested noise
parts.
Note 4: All output swing measurements are taken with the load resistor
connected from output to ground. For single supply tests, only the positive
swing is specified (negative swing will be 0V due to the pull-down effect of
the load resistor). For dual supply operation, both positive and negative
swing are specified.
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LTC1152
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TYPICAL PERFORMANCE CHARACTERISTICS
Common-Mode Range vs
Supply Voltage
Supply Current vs Supply Voltage
VS = 5V
TA = 25°C
2
0
–2
–4
POWER SUPPLY CURRENT (mA)
4
SUPPLY CURRENT (mA)
2.5
2.0
1.5
–6
6
3
4
5
2
POWER SUPPLY VOLTAGE (±V)
1
1.0
7
0
2
6
8
10 12
4
TOTAL SUPPLY VOLTAGE (V)
1152 G01
OUTPUT SHORT-CIRCUIT CURRENT (mA)
OUTPUT SWING (±V)
VS = SINGLE 5V
4
VS = SINGLE 3V
VS = ±2.5V
2
VS = ±1.5V
1
0
1
30
SINK
20
10
2
5 10 20 50 100 200
LOAD RESISTANCE (kΩ)
3
4
2
6
8
10
12
TOTAL SUPPLY VOLTAGE (V)
2
4
12
6
8
10
TOTAL SUPPLY VOLTAGE (V)
1152 G07
4
200
150
4
2
6
8
10
12
TOTAL SUPPLY VOLTAGE (V)
Input Bias Current vs Temperature
1000
VS = 5V
TA = 25°C
VS = 5V
2
1
0
14
1152 G06
INPUT BIAS CURRENT (±pA)
CHARGE PUMP VOLTAGE, VCP – V+ (V)
14
100
250
100
14
3
1
75
TA = 25°C
Charge Pump Voltage vs
Load Current
2
0
25
50
TEMPERATURE (°C)
1152 G05
Charge Pump Voltage vs
Supply Voltage
TA = 25°C
–25
Open-Loop Output Resistance vs
Supply Voltage
SOURCE
1152 G04
0
1.5
300
TA = 25°C
0
0.2 0.5
1.6
1152 G03
40
3
1.7
Output Short-Circuit Current vs
Supply Voltage
6
5
1.8
1152 G02
Output Swing vs Load Resistance
TA = 25°C
1.9
1.4
–50
14
OPEN-LOOP OUTPUT RESISTANCE (Ω)
COMMON-MODE RANGE LIMIT (V)
2.0
6
–8
CHARGE PUMP VOLTAGE, VCP – V+ (V)
Supply Current vs Temperature
3.0
8
0
20
40 60 80 100 120 140 160
LOAD CURRENT (µA)
1152 G08
100
10
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1152 G09
LTC1152
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TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Phase Shift vs
Frequency
Common-Mode Rejection Ratio vs
Frequency
PHASE
40
80
60
GAIN
30
40
20
20
10
0
PHASE SHIFT (DEG)
VOLTAGE GAIN (dB)
50
100
0
–10
COMMON-MODE REJECTION RATIO (dB)
60
10k
100k
1M
FREQUENCY (Hz)
TA = 25°C
VS = ±2.5V
100
90
80
70
60
50
40
30
0.1
–20
1k
80
110
120
TA = 25°C
VS = ±2.5V
PIN 5 = NC
10M
10
100
FREQUENCY (kHz)
TA = 25°C
VS = ±2.5V
CCOMP = 1000pF
–PSRR
30
+PSRR
20
10
0
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
1152 G14
0.1Hz to 10Hz Input Noise
2
100
30
40
20
20
10
0
GAIN
–20
1
100
(µV)
60
VOLTAGE NOISE (nV/√Hz)
125
80
40
0
40
Voltage Noise vs Frequency
PHASE SHIFT (DEG)
VOLTAGE GAIN (dB)
50
50
1000
150
120
PHASE
60
1152 G13
Gain and Phase Shift vs
Frequency
70
TA = 25°C
70
–10
1
1152 G10
60
POWER SUPPLY REJECTION RATIO (dB)
70
Power Supply Rejection Ratio vs
Frequency
75
0
50
–1
25
–10
–40
–20
1k
10k
100k
1M
FREQUENCY (Hz)
–60
10M
0
1
Gain and Phase Shift vs
Frequency
50
10k
–2
0
2
6
4
TIME (SEC)
8
10
1152 G18
Small-Signal Transient Response
Large-Signal Transient Response
VS = ±2.5V
AV = 1
VS = ±2.5V
AV = 1
180
TA = 25°C
VS = ±2.5V
CCOMP = 0.1µF
160
140
30
20
120
PHASE
100
10
80
0
–10
60
40
GAIN
–20
20
–30
0
–40
0.01
–20
0.1
1
FREQUENCY (kHz)
10
PHASE SHIFT (DEG)
VOLTAGE GAIN (dB)
40
100
1k
FREQUENCY (Hz)
1152 G15
1152 G11
60
10
1152 G16
1152 G17
1152 G12
5
LTC1152
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APPLICATI
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VCC
(PIN 7)
Rail-to-Rail Operation
The LTC1152 is a rail-to-rail input common-mode range,
rail-to-rail output swing op amp. Most CMOS op amps,
including the entire LTC zero-drift amplifier line, and even
a few bipolar op amps, can and do, claim rail-to-rail output
swing. One obvious use for such a device is to provide a
unity-gain buffer for 0V to 5V signals running from a single
5V power supply. This is not possible with the vast
majority of so-called “rail-to-rail” op amps; although the
output can swing to both rails, the negative input (which
is connected to the output) will exceed the common-mode
input range of the device at some point (generally about
1.5V below the positive supply), opening the feedback
loop and causing unpredictable and sometimes bizarre
behavior.
The LTC1152 is an exception to this rule. It features both
rail-to-rail output swing and rail-to-rail input commonmode range (CMR); the input CMR actually extends beyond either rail by about 0.3V. This allows unity-gain
buffer circuits to operate with any input signal within the
power supply rails; input signal swing is limited only by the
output stage swing into the load. Additionally, signals
occurring at either rail (power supply current sensing, for
example) can be amplified without any special circuitry.
Internal Charge Pump
The LTC1152 achieves its rail-to-rail input CMR by using
a charge pump to generate an internal voltage approximately 2V higher than V +. The input stages of the op amp
are run from this higher voltage, making signals at V +
appear to be 2V below the front end’s power supply (Figure
1). The charge pump is contained entirely within the
LTC1152; no external components are required.
About 100µVP-P of residual charge pump switching noise
will be present on the output of the LTC1152. This
feedthrough is at 4.7MHz, higher than the gain-bandwidth
of the LTC1152, and will generally not cause any problems. Very sensitive applications can reduce this
feedthrough by connecting a capacitor from the CP pin
(pin 8) to V + (pin 7); a 0.1µF capacitor will reduce charge
pump feedthrough to negligible levels. The LTC1152 includes an internal diode from pin 8 to pin 7 to prevent
external parasitic capacitance from lengthening start-up
6
CP (PIN 8)
INTERNAL
CHARGE
PUMP
VCC + 2V
0.1µF*
–IN
–
INPUT
+IN
OUTPUT
RAIL TO RAIL
OUT
+
*OPTIONAL EXTERNAL
CAPACITOR TO REDUCE
CHARGE PUMP FEEDTHROUGH
1152 F01
Figure 1. LTC1152 Internal Block Diagram
time. This diode can stand short-term peak currents of
about 50mA, allowing it to quickly charge external capacitance to ground or V –. Large capacitors (>1µF) should not
be connected between pin 8 and ground or V – to prevent
excessive diode current from flowing at start-up. The
LTC1152 can withstand continuous short circuits between pin 8 and V +; however, short circuiting pin 8 to
ground or V – will cause large amounts of current to flow
through the diode, destroying the LTC1152. Don’t do it.
Output Drive
The LTC1152 features an enhanced output stage that can
sink and source 10mA with a single 5V supply while
maintaining rail-to-rail output swing under most loading
conditions. The output stage can be modeled as a perfect
rail-to-rail voltage source with a resistor in series with it;
this open-loop output resistance limits the output swing
by creating a resistor divider with the output load.
The output resistance drops as total power supply voltage
increases, as shown in the typical performance curves. It
is typically 140Ω with a single 5V supply, allowing a 4.4V
output swing into a 1k resistor with a single 5V supply.
VCC (PIN 7)
LTC1152
OUTPUT
DRIVER
ROUT
OUT (PIN 6)
≈140Ω AT 5V SUPPLY
RLOAD
1152 F02
Figure 2. LTC1152 Output Resistance Model
LTC1152
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APPLICATI
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Compensation/Bandwidth Limiting
The LTC1152 is unity-gain stable with capacitive loads up
to 1000pF. Larger capacitive loads can be driven by
externally compensating the LTC1152. Adding 1000pF
between COMP (pin 5) and OUT (pin 6) allows capacitive
loading of up to 1µF; 0.1µF between pins 5 and 6 allows the
LTC1152 to drive infinite capacitive load (Figure 3).
8
1
2
LTC1152
3
4
V+
7
6
OUTPUT
5
V–
1N4148*
1N4148*
CC
*OPTIONAL DIODES TO PREVENT
LATCH-UP WITH CC > 1µF
1152 F03
Figure 3. Output Compensation Connection
Large compensation capacitors can also be used to limit
the bandwidth of the LTC1152. With 0.1µF from pin 5 to
pin 6, the LTC1152’s gain-bandwidth product is reduced
from 700kHz to around 200Hz. Note that compensation
capacitors greater than 1µF can cause latch-up under
severe output fault conditions; this can be prevented by
clamping pin 5 to each supply with standard signal diodes,
as shown in Figure 3.
Shutdown
The LTC1152 includes a shutdown pin (pin 1). When this
pin is at V +, the LTC1152 operates normally. An internal
1µA pull-up keeps the pin high if it is left floating. When pin
1 is pulled low, the part enters shutdown mode; supply
current drops to 1µA, all internal clocking stops and the
output enters a high impedance state. During shutdown
the voltage at the CP pin (pin 8) will drop to 0.5V below V +.
When pin 1 is brought high again, about 10µs will elapse
before the charge pump regains full voltage. During this
time the LTC1152 will operate normally, but the input CMR
may not include V +. Pin 1 is compatible with CMOS logic
running from the same supply as the LTC1152. Additionally, the input trip levels allow ground referenced CMOS
logic signals to interface directly to pin 1 when the LTC1152
is running from ±5V or ±3V supplies. The internal 1µA
pull-up also allows pin 1 to interface with open-collector/
open-drain devices or discrete transistors.
The high impedance output in shutdown allows several
LTC1152s to be connected together as a MUX, with their
outputs tied in parallel and the active channel selected by
using the shutdown pins. Deselected (shutdown) channels will go to high impedance at the outputs, preventing
them from fighting with the active channel. This works
best when the individual LTC1152s are connected in
noninverting feedback configurations to prevent the feedback resistors from passing signals through deselected
channels. See the Typical Applications section for a circuit
example.
Zero-Drift Operation
The LTC1152 is a zero-drift op amp. Like other LTC zerodrift op amps, it features virtually error-free DC performance, very little drift over time and temperature, and very
low noise at low frequencies. The internal nulling clock
runs at about 2.3kHz (the charge pump frequency of
4.7MHz divided by 2048) and is synchronized to the
internal charge pump to prevent beat frequencies from
appearing at the output. The self-nulling circuit constantly
corrects the input offset voltage, keeping it typically below
±1µV over the entire input common-mode range. This has
the added benefit of providing exceptional CMRR and
PSRR at low frequencies––far better than competing railto-rail op amps.
Because it uses a sampling front end, the LTC1152 will
exhibit aliasing behavior and clock noise at frequencies
near the internal 2.3kHz sampling frequency. The LTC1152
includes an internal anti-aliasing circuit to keep these error
terms to a minimum. As a rule, alias frequencies will be
down by (80dB – ACLG) in most standard amplifier configurations, where ACLG is the closed-loop gain of the
LTC1152 circuit. Clock noise is also dependent on closedloop gain; it will generally consist of spikes of about 100µV
in amplitude, input referred. In general, these error terms
are too small to affect most applications. For a more
detailed explanation of zero-drift amplifier behavior, see
the LTC1051/LTC1053 data sheet.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
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APPLICATI
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High Gain Amplifier with ±1.5V Supplies
10Ω
High Precision Three-Input MUX
1.5V
100k
1.1k
10k
SEL1
2
2
7
–
6
LTC1152
IN
3
+
3
IN 1
AV = 10
AV = 10k
= 80dB
10Ω
–1.5V
6
LTC1152
OUT
0.1µF
4
1
–
+
10k
OUT
1152 TA03
SEL2
2
High-Side Power Supply Current Sensing
–
1
6
LTC1152
CHANGE SENSE RESISTOR
TO CHANGE SENSITIVITY
0.01Ω
5V
0.1µF
3
2
3
+
2
–
SEL3
+
LTC1152
100Ω
IN 2
AV = 1000
TO
MEASURED
CIRCUIT
10k
6
10k
1
6
LTC1152
–
2
10k
–
100k
OUT
1V/100mA
LOAD CURRENT IN
MEASURED CIRCUIT
0.1µF
6
LT1097
3
3
IN 3
AV = 1
+
+
SELECT INPUTS ARE CMOS LOGIC COMPATIBLE.
SELECT ONLY ONE CHANNEL AT ONCE!
1152 TA04
10k
GND
GND
1152 TA05
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic SOIC
N8 Package
8-Lead Plastic DIP
0.189 – 0.197*
(4.801 – 5.004)
0.400*
(10.160)
MAX
8
7
6
8
0.255 ± 0.015*
(6.477 ± 0.381)
1
0.009 – 0.015
(0.229 – 0.381)
(
8
+0.025
0.325 –0.015
+0.635
8.255
–0.381
)
2
3
5
*THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL
NOT EXCEED 0.006 INCH (0.15mm).
0.150 – 0.157*
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
4
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
6
5
*THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL
NOT EXCEED 0.010 INCH (0.254mm).
0.300 – 0.325
(7.620 – 8.255)
7
0.018 ± 0.003
(0.457 ± 0.076)
Linear Technology Corporation
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.015
(0.380)
MIN
1
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 0294
N8 0694
LT/GP 0195 10K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
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