LTC1257CS8#TRPBF

LTC1257 Complete Single Supply 12-Bit Voltage Output DAC in SO-8 FEATURES DESCRIPTION 8-Pin SO Package n Buffered Voltage Output n Built-In 2.048V Reference n 500µV/LSB with 2.048V Full Scale n 1/2LSB Max DNL Error n Guaranteed 12-Bit Monotonic n 3-Wire Cascadable Serial Interface n Wide Single Supply Range: V CC = 4.75V to 15.75V n Low Power: I CC Typ = 350µA with 5V Supply The LTC®1257 is a complete single supply, 12-bit voltage output D/A converter (DAC) in an SO-8 package. The LTC1257 includes an output buffer amplifier, 2.048V voltage reference and an easy to use 3-wire cascadable serial interface. An external reference can be used to override the internal reference and extend the output voltage range to 12V. The power supply current is a low 350µA when operating from a 5V supply, making the LTC1257 ideal for battery-powered applications. The space-saving 8-pin SO package and operation with no external components provide the smallest 12-bit D/A system available. n APPLICATIONS L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Digital Offset/Gain Adjustment n Industrial Process Control n Automatic Test Equipment n TYPICAL APPLICATION Daisy-Chained Control Outputs Differential Nonlinearity vs Input Code 5V CONTROL OUTPUT 1 VCC VOUT LTC1257 GND VREF 0.1µF CONTROL OUTPUT 2 VCC VOUT LTC1257 GND VREF DIN CLK µP LOAD DOUT DNL ERROR (LSBs) 0.1µF 0.5 0.0 DIN CLK LOAD –0.5 DOUT TO NEXT DAC 0 512 1024 1536 2048 2560 3072 3584 4098 CODE 1257 TA05 1257 TA01 1257fc 1 LTC1257 ABSOLUTE MAXIMUM RATINGS (Note 1) VCC to GND.............................................. –0.5V to 16.5V TTL Input Voltage ........................... –0.5V to VCC + 0.5V VOUT................................................. –0.5V to VCC + 0.5V REF.................................................. –0.5V to VCC + 0.5V Operating Temperature Range LTC1257C................................................. 0°C to 70°C LTC1257I.............................................. –40°C to 85°C Maximum Junction Temperature Plastic Package....................................... –65°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW CLK 1 8 VCC DIN 2 7 VOUT CLK 1 8 VCC DIN 2 7 VOUT LOAD 3 6 REF LOAD 3 6 REF DOUT 4 5 GND DOUT 4 5 GND N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 100°C/W TJMAX = 125°C, θJA = 150°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1257CN8#PBF LTC1257CN8#TRPBF LTC1257CN8 8-Lead PDIP 0°C to 70°C LTC1257IN8#PBF LTC1257IN8#TRPBF LTC1257IN8 8-Lead PDIP –40°C to 85°C LTC1257CS8#PBF LTC1257CS8#TRPBF 1257 8-Lead Plastic SO 0°C to 70°C LTC1257IS8#PBF LTC1257IS8#TRPBF 1257I 8-Lead Plastic SO –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted. SYMBOL DAC DNL INL PARAMETER Resolution Differential Nonlinearity Integral Nonlinearity CONDITIONS MIN l Guaranteed Monotonic (Note 4) LTC1257C (Note 4) LTC1257I (Note 4) l l l TYP MAX UNITS ±0.5 ±3.5 ±4.0 Bits LSB LSB LSB 12 1257fc 2 LTC1257 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted. SYMBOL OFF OFFTC PARAMETER Offset Error Offset Error Tempco Gain Error Gain Error Tempco CONDITIONS When Using Internal Reference, LTC1257C When Using Internal Reference, LTC1257I When Using External Reference, LTC1257C When Using External Reference, LTC1257I When Using Internal Reference (Note 2) When Using External Reference (Note 2) MIN TYP l l l l ±0.02 ±15 0.5 ±0.01 l l l (Note 2) l IREF = 0, LTC1257C IREF = 0, LTC1257I IREF = 0 IREF = 0, LTC1257C IREF = 0, LTC1257I 0µA ≤ IREF ≤ 100µA VCC > VREF + 2.7V l l MAX ±8 ±10 ±4 ±5 ±0.066 ±30 ±2 ±0.02 UNITS LSB LSB mV mV LSB/°C µV/°C LSB LSB/°C 2.068 2.078 V V LSB/°C LSB/V LSB/V LSB V kΩ pF mA Reference Reference Output Voltage Reference Output Tempco Reference Line Regulation Reference Load Regulation Reference Input Range Reference Input Resistance Reference Input Capacitance Short-Circuit Current Power Supply Positive Supply Voltage VCC Supply Current ICC Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital I/O Digital Input High Voltage VIH Digital Input Low Voltage VIL Digital Output High Voltage VOH Digital Output Low Voltage VOL Digital Input Leakage ILEAK Digital Input Capacitance CIN Switching (Note 2) DIN Valid to CLK Setup t1 DIN Valid to CLK Hold t2 CLK High Time t3 CLK Low Time t4 l l l l 2.475 8 14 15 l VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 l 5kΩ in Parallel with 100pF To ±1/2LSB, 5kΩ in Parallel with 100pF, VCC = 4.75V (Notes 2, 3) l ±0.4 ±0.7 ±1 12 18 90 l For Specified Performance 4.75V ≤ VCC ≤ 5.25V 4.75V ≤ VCC ≤ 15.75V 4.75 l l 350 800 15.75 600 1500 V µA µA 250 60 60 500 mA mA Ω l l 1.0 V/µs µs nV/s 6 50 l 2.4 0.8 l IOUT = –1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 2) 2.048 ±0.06 l l (Note 2) VREF Shorted to GND 2.028 2.018 l l VCC – 1 0.4 ±10 10 l l l l l l 100 25 350 350 V V V V µA pF ns ns ns ns 1257fc 3 LTC1257 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = TMIN to TMAX. VCC = 4.75V to 15.75V, internal or external reference (2.475V ≤ VREF ≤ VCC – 2.7V), unless otherwise noted. SYMBOL t5 t6 t7 t8 fCLK PARAMETER LOAD Pulse Width LSB CLK to LOAD LOAD High to CLK DOUT Output Delay Maximum Clock Frequency CONDITIONS MIN 150 0 0 35 l l l CLOAD = 15pF l TYP MAX UNITS ns ns ns ns MHz 150 1.4 Note 2: Guaranteed by design; not subject to test. Note 3: DAC switched from all 1s to all 0s, and all 0s to all 1s code. Note 4: Guaranteed with internal VREF or with external VREF range of 2.475V to 12V. Tested at 10V. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. TYPICAL PERFORMANCE CHARACTERISTICS Minimum Supply Voltage vs Load Current #1 Minimum Supply Voltage vs Load Current #2 5.0 4.2 4.0 3.8 3.6 3.4 3.2 3.0 0.01 0.1 1 OUTPUT LOAD CURRENT (mA) VREF = 10V VOUT = FULL SCALE TA = 25°C 14.5 14.0 13.5 13.0 12.5 12.0 0.1 1 OUTPUT LOAD CURRENT (mA) 1257 G01 VCC = 5V TA = 25°C OUTPUT VOLTAGE SWING (V) 0.39 4.0 ZERO SCALE RL TIED TO VCC 3.5 3.0 FULL SCALE RL TIED TO GND 2.5 2.0 1.5 1.0 0.5 1 3 2 LOGIC VOLTAGE (V) 4 5 1257 G04 50 25 75 0 TEMPERATURE (°C) 0 100 125 1257 G03 Pull-Down Voltage vs Output Sink Current Capability 1000 VCC = 5V 4.5 0.44 0 VCC = 4.75V 0.33 0.31 –50 –25 10 5.0 0.59 0.34 0.34 Output Swing vs Load Resistance 0.49 VCC = 5V 0.35 1257 G02 Supply Current vs Logic Input Voltage 0.54 VCC = 5.25V 0.36 0.32 11.5 11.0 0.01 10 0.37 SUPPLY CURRENT (mA) 4.4 0.38 OUTPUT PULL-DOWN VOLTAGE (mV) MINIMUM SUPPLY VOLTAGE (V) 4.6 MINIMUM SUPPLY VOLTAGE (V) VREF = INTERNAL VOUT = FULL SCALE TA = 25°C 4.8 SUPPLY CURRENT (mA) Supply Current vs Temperature 15.0 10 100 1k LOAD RESISTANCE (Ω) 10k 1257 G05 100 10 HOT ROOM 1 0.1 COLD 1 10 100 OUTPUT SINK CURRENT (µA) 1000 1257 G06 1257fc 4 LTC1257 TYPICAL PERFORMANCE CHARACTERISTICS Full-Scale Voltage vs Temperature Zero-Scale Voltage vs Temperature 2.0495 VCC = 5V INTERNAL REFERENCE 2.0480 2.0475 2.0470 50 25 75 0 TEMPERATURE (°C) 100 1.2 0.7 0.8 0.6 0.5 0.4 0.3 –1.2 –1.6 –25 0 25 50 75 TEMPERATURE (°C) 0 512 1024 1536 2048 2560 3072 3584 4098 CODE 100 125 –2.0 VCC = 5V INTERNAL REFERENCE TA = 25°C 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1257 G09 1257 G08 Reference Compensation Resistance vs CL Broadband Noise 70 CODE = FFFH BW = 3Hz TO 1MHz GAIN = 1100× 60 50 40 0.1V/DIV REFERENCE COMPENSATION RESISTANCE (Ω) DNL ERROR (LSBs) –0.5 –0.4 0.1 Differential Nonlinearity (DNL) 0.0 0 –0.8 1257 G07 0.5 0.4 0.2 0 –50 125 1.6 ERROR (LSB) 2.0485 2.0465 –50 –25 VCC = 5V INTERNAL REFERENCE 0.8 ZERO-SCALE VOLTAGE (mV) 2.0490 FULL-SCALE VOLTAGE (V) Integral Nonlinearity (INL) 2.0 0.9 30 20 10 0 0.01 0.1 1257 TA05 1 CL (µF) 10 100 TIME = 5ms/DIV 1257 G12 1257 G11 PIN FUNCTIONS CLK (Pin 1): The TTL level input for the serial interface clock. DIN (Pin 2): The TTL level input for the serial interface data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. LOAD (Pin 3): The TTL level input for the serial interface load control. Data is loaded from the shift register into the DAC register, thus updating the DAC output when LOAD is pulled low. The DAC register is transparent as long as LOAD is held low. DOUT(Pin 4): The output of the shift register which becomes valid on the rising edge of the serial clock. The DOUT pin is driven from GND to VCC by an internal CMOS inverter. Multiple LTC1257s may be cascaded by connecting the DOUT pin to the DIN pin of the next chip. GND (Pin 5): Ground. REF (Pin 6): The output of the 2.048V reference and the input to the DAC resistor ladder. An external reference with voltage from 2.475V to VCC – 2.7V may be used to override the internal reference. 1257fc 5 LTC1257 PIN FUNCTIONS VOUT (Pin 7): The buffered DAC output is capable of sourcing 2mA over temperature while pulling within 2.7V of VCC. The output will pull to ground through an internal 250Ω equivalent resistance. VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤ 15.75V. Requires a bypass capacitor to ground. DEFINITIONS LSB: The least significant bit or the ideal voltage difference between two successive codes. LSB = (VFS – VOS)/2n – 1 n = The number of digital input bits VOS = The zero code error or offset of the DAC VFS = The full-scale output voltage of the DAC measured when all bits are set to 1 Resolution: The resolution is the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. INL: End-point integral nonlinearity is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below ground, the linearity is measured between full-scale and the first code that guarantees a positive output. The INL error at a given input code is calculated as follows: INL = (VOUT – VIDEAL)/LSB VIDEAL = (Code)(LSB) + VOS VOUT = The output voltage of the DAC measured at the given input code DNL: Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB ∆VOUT = The measured voltage difference between two adjacent codes Offset Error: The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below ground. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. 6 OUTPUT VOLTAGE NEGATIVE OFFSET { 0V DAC CODE 1257 F01 Figure 1. Effect of Negative Offset The offset of the part is measured at the first code that produces an output voltage 0.5LSB greater than the previous code: VOS = VOUT – [(Code)(VFS)/(2n – 1)] Full-Scale Error: Full-scale error is the difference between the ideal and measured DAC output voltages with all bits set to one (Code = 4095). The full-scale error includes the offset error and is calculated as follows: FSE = (VOUT – VIDEAL)/LSB VIDEAL = (VREF)(1 – 2–n) – VOS VREF = The reference voltage, either internal or external Gain Error: Gain error is the difference between the ideal and measured slope of the DAC transfer characteristic. Gain error is equal to full-scale error minus offset error. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). 1257fc LTC1257 BLOCK DIAGRAM LOGIC SUPPLY CLK DIN 5V REGULATOR VCC 12-BIT SHIFT REGISTER DOUT 12 LOAD GND 12-BIT LATCH 12 REF 2.048V REFERENCE + DAC VOUT – 1257 BD TIMING DIAGRAM t1 t2 t6 CLK t4 B11 MSB DIN t7 t3 B0 LSB B1 B10 t5 LOAD t8 DOUT B11 (PREVIOUS WORD) B10 B1 B0 B11 CURRENT WORD 1257 TD 1257fc 7 LTC1257 OPERATION Serial Interface Reference The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first and the LSB last. The DAC register loads the data from the shift register when LOAD is pulled low, and remains transparent until LOAD is pulled high and the data is latched. The LTC1257 includes an internal 2.048V reference, making 1LSB equal to 500µV. The internal reference output is turned off when the pin is forced above the reference voltage, allowing an external reference to be connected to the reference pin. The external reference must be greater than 2.475V and less than VCC – 2.7V, and be capable of driving the 10k minimum DAC resistor ladder. An internal 5V regulator provides the supply for the digital logic. By limiting the internal digital signal swings to 5V, digital noise is reduced. The buffered output of the 12-bit shift register is available on the DOUT pin which will swing from GND to VCC. Multiple LTC1257s may be daisy chained together by connecting the DOUT pin to the DIN pin of the next chip, while the clock and load signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the LOAD signal is pulled low to update all of them simultaneously. The maximum clocking rate is 1.4MHz. If the reference output is driving a large capacitive load, a series resistor must be added to insure stability. For any capacitive load greater than 1µF, a 10Ω series resistor will suffice. Voltage Output The LTC1257 voltage output is able to pull within 2.7V of VCC while sourcing 2mA. A internal NMOS transistor with a 200Ω equivalent impedance pulls the output to ground. The output is protected against short circuits and is able to drive up to a 500pF capacitive load without oscillation. If digital noise on the output causes a problem, a simple 100Ω, 0.1µF RC circuit can be used to filter the noise. TYPICAL APPLICATIONS DAC with External Reference Filtering VREF and VOUT 15V VCC IN 0.1µF LT1021-10 GND OUT 0.1µF DIN CLK VCC CONTROL OUTPUT VREF VOUT LTC1257 GND DIN CLK LOAD LOAD µP VCC LTC1257 VOUT DOUT GND 1257 TA03 VOUT 0.1µF VREF 1µF DOUT 100Ω 5% 10Ω 5% 1257 TA06 1257fc 8 LTC1257 TYPICAL APPLICATIONS Auto Ranging 8-Channel ADC with Shutdown 22µF 5V VCC CH0 8 ANALOG INPUT CHANNELS CS DOUT • • • LTC1296 DIN CH7 COM REF + REF – SSO 50k 50k 5V µP CLK 74HC04 0.1µF VCC 100Ω VOUT LTC1257 0.1µF 100Ω VOUT LTC1257 GND VREF LOAD DOUT GND VREF VCC 0.1µF DIN CLK DIN CLK LOAD 1257 TA02 DOUT 12-Bit Single 5V Control System with Shutdown 5V 100k 10k 10µF 2N3906 VCC –IN – + J VIN LTC1297 ADC LT1025A GND COMMON CLK DATA CLK DAC LOAD µP +IN GND + 10µF LTC1050 – VREF 47k 1µF 74k 1k CB/POWER DOWN CS DOUT 0.1µF 1µF 100k VREF CONTROL OUTPUT VCC DIN CLK VOUT LTC1257 LOAD GND DOUT 1257 TA04 1257fc 9 LTC1257 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) .300 – .325 (7.620 – 8.255) ( +.035 .325 –.015 8.255 +0.889 –0.381 .130 ±.005 (3.302 ±0.127) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .008 – .015 (0.203 – 0.381) ) .400* (10.160) MAX 8 7 6 1 2 3 5 .255 ±.015* (6.477 ±0.381) .120 (3.048) .020 MIN (0.508) MIN .018 ±.003 .100 (2.54) BSC 4 N8 REV I 0711 (0.457 ±0.076) NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .050 BSC .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) NOTE: 1. DIMENSIONS IN 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP .008 – .010 (0.203 – 0.254) 7 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 2 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 REV G 0212 1257fc 10 LTC1257 REVISION HISTORY (Revision history begins at Rev C) REV DATE DESCRIPTION C 12/12 Removed MAX Voltage Output Settling Time value in Electrical Characteristics section PAGE NUMBER 3 1257fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1257 TYPICAL APPLICATION Driving LTC1257 with Opto-Isolators 12V 2k 5% MOC5008 CLK 1 1 VOUT LOAD LTC1257 VOUT GND 6 4 2 5 MOC5008 LOAD VREF DIN DOUT 0.1µF 5 MOC5008 DIN CLK VCC 6 4 2 LT1021-5 VOUT VIN 2k 5% 2k 5% 1 6 4 1257 TA07 2 5 RELATED PARTS PART NUMBER DESCRIPTION 12 Bit LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package, VCC: 2.7V to 5.5V LTC1450/LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1451 LTC1452 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1659 14 Bit LTC1658 LTC1654 16 Bit LTC1655(L) Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC = 2.7V to 5.5V 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC = 2.7V to 5.5V Dual 14-Bit VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 COMMENTS LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF, REF Input Can Be Tied to VCC Output Swings from GND to REF, REF Input Can Be Tied to VCC Programmable Speed/Power, SO-8 Footprint VCC = 5V (3V), Low Power, Deglitched, VOUT = 0V to 4.096V (0V to 2.5V) 1257fc 12 Linear Technology Corporation LT 1212 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 1994