LTC1291CCN8#PBF

LTC1291 Single Chip 12-Bit Data Acquisition System U FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Built-In Sample-and-Hold Single Supply 5V Operation Power Shutdown Direct 3- or 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports Two-Channel Analog Multiplexer Analog Inputs Common Mode to Supply Rails 8-Pin DIP Package U KEY SPECIFICATIO S ■ ■ ■ Resolution: 12 Bits Fast Conversion Time: 12µs Max Over Temp. Low Supply Current: 6.0mA (Typ) Active Mode 10µA (Max) Shutdown Mode The LTC®1291 is a data acquisition system that contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform a 12-bit unipolar A/D conversion. The input multiplexer can be configured for either single-ended or differential inputs. An on-chip sample-and-hold is included on the “+” input. When the LTC1291 is idle, it can be powered down in applications where low power consumption is desired. An external reference is not required because the LTC1291 takes its reference from the power supply (VCC). All these features are packaged in an 8-pin DIP. The serial I/O is designed to communicate without external hardware to most MPU serial ports and all MPU parallel I/O ports allowing data to be transmitted over three or four wires. Given the accuracy, ease of use and small package size, this device is well suited for digitizing analog signals in remote applications where minimum number of interconnects, small physical size, and low power consumption are important. , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOSTM is a trademark of Linear Technology Corporation U TYPICAL APPLICATIO 2-Channel 12-Bit Data Acquisition System 22µF TANTALUM Channel-to-Channel INL Matching 5V + 0.5 0.4 0.3 VCC(VREF) DO 0.2 0.1µF CH0 2-CHANNEL MUX* CLK LTC1291 SCK MC68HC11 CH1 DOUT MISO GND DIN MOSI DELTA (LSB) CS 0.1 0 –0.1 –0.2 –0.3 –0.4 1291 TA01 *FOR OVERVOLTAGE PROTECTION, LIMIT THE INPUT CURRENT TO 15mA PER PIN OR CLAMP THE INPUTS TO VCC AND GND WITH 1N4148 DIODES. CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED CHANNEL OR THE OTHER CHANNEL IS OVERVOLTAGED (VIN < GND OR VIN > VCC). SEE SECTION ON OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION. –0.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1291 TA02 1291fa 1 LTC1291 U U W W W AXI U RATI GS W (Notes 1 and 2) U ABSOLUTE PACKAGE/ORDER I FOR ATIO Supply Voltage (VCC) to GND .................................. 12V Voltage Analog Inputs ............................ –0.3V to VCC + 0.3V Digital Inputs ........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1291BC, LTC1291CC, LTC1291DC ............................................ 0°C to 70°C Storage Temperature Range ................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW CS 1 8 VCC (VREF) 2 7 CLK CH1 3 6 DOUT GND 4 5 DIN CH0 LTC1291BCN8 LTC1291CCN8 LTC1291DCN8 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 100°C, θJA = 130°C/ W (N8) LTC1291BCJ8 LTC1291CCJ8 LTC1291DCJ8 J8 PACKAGE 8-LEAD CERAMIC DIP TJMAX = 150°C, θJA = 100°C/ W (J8) OBSOLETE PACKAGE Consider N8 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1291B MIN MAX MAX UNITS Offset Error (Note 4) ● ±3.0 ±3.0 ±3.0 LSB Linearity Error (INL) (Note 4 & 5) ● ±0.5 ±0.5 ±0.75 LSB Gain Error (Note 4) ● ±1.0 ±2.0 ±4.0 LSB ● 12 12 12 Bits Analog Input Range (Note 7) On Channel Leakage Current (Note 8) On Channel = 5V Off Channel = 0V ● ±1 On Channel = 0V Off Channel = 5V ● ±1 On Channel = 5V Off Channel = 0V ● On Channel = 0V Off Channel = 5V ● Off Channel Lekage Current (Note 8) MIN TYP LTC1291D CONDITIONS Minimum Resolution for which No Missing Codes are Guaranteed TYP LTC1291C PARAMETER MAX MIN TYP V – 0.05V to VCC + 0.05V ±1 ±1 µA ±1 ±1 µA ±1 ±1 ±1 µA ±1 ±1 ±1 µA AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1291B/LTC1291C/LTC1291D MIN TYP MAX SYMBOL PARAMETER CONDITIONS fCLK Clock Frequency VCC = 5V (Note 6) tSMPL Analog Input Sample Time See Operating Sequence 2.5 CLK Cycles tCONV Conversion Time See Operating Sequence 12 CLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits (Note 9) 1.0 18 CLK + 500ns ● UNITS MHz Cycles 160 300 ns 1291fa 2 LTC1291 AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1291B/LTC1291C/LTC1291D MIN TYP MAX SYMBOL PARAMETER CONDITIONS UNITS tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 80 150 ns ten Delay Time, CLK↓ to DOUT Enabled See Test Circuits ● 80 200 ns thDI Hold Time, DIN after CLK↑ VCC = 5V (Note 6) 50 thDO Time Output Data Remains Valid after CLK↓ tWHCLK CLK High Time VCC = 5V (Note 6) 300 tWLCLK CLK Low Time VCC = 5V (Note 6) tf DOUT Fall Time See Test Circuits ● tr DOUT Rise Time See Test Circuits ● tsuDI Setup Time, DIN Stable before CLK↑ VCC = 5V (Note 6) tsuCS Setup Time, CS↓ before CLK↑ VCC = 5V (Note 6) 50 ns tWHCS CS High Time During Conversion VCC = 5V (Note 6) 500 ns tWLCS CS Low Time During Data Transfer VCC = 5V (Note 6) 18 CIN Input Capacitance Analog Inputs On Channel Analog Inputs Off Channel Digital Inputs ns 130 ns ns 400 ns 65 130 ns 25 50 ns 50 ns CLK Cycles 100 5 5 pF pF pF U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) LTC1291B/LTC1291C/LTC1291D MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIH High Level Input Current VIN = VCC IIL Low Level Input Current VIN = 0V VOH High Level Output Voltage VCC = 4.75V, IOUT = –10µA VCC = 4.75V, IOUT = – 360µA ● 2.0 UNITS V 0.8 V ● 2.5 µA ● –2.5 µA 2.4 4.7 4.0 V V VOL Low Level Output Voltage VCC = 4.75V, IOUT = 1.6mA ● 0.4 V IOZ High Z Output Leakage VOUT = VCC, CS High VOUT = 0V, CS High ● ● 3 –3 µA µA ISOURCE Output Source Current VOUT = 0V – 20 mA ISINK Output Sink Current VOUT = VCC 20 mA ICC Positive Supply Current CS High ● 6 12 mA CS High Power Shutdown CLK Off ● 5 10 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 5V, CLK = 1.0MHz unless otherwise specified. Note 4: One LSB is equal to VCC divided by 4096. For example, when VCC = 5V, 1LSB = 5V/4096 = 1.22mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 125kHz at 125°C, fCLK ≥ 30kHz at 85°C and fCLK ≥ 3kHz at 25°C. 1291fa 3 LTC1291 U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset vs Supply Voltage 10 10 CLK = 1MHz TA = 25°C CLK = 1MHz VCC = 5V 9 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 6 4 8 7 6 5 2 4 5 4 3 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) 6 SUPPLY VOLTAGE (V) 1291 G01 0.4 0.3 0.2 0.1 0 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) 6.0 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 4.0 Change in Gain Error vs Supply Voltage 4.5 5.5 5.0 SUPPLY VOLTAGE (V) Change in Offset vs Temperature 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) VCC = 5V CLK = 1MHz 0.4 0.3 0.2 0.1 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) 6.0 1291 G05 Change in Linearity vs Temperature 125 1291 G06 Minimum Clock Rate for 0.1 LSB Error Change in Gain vs Temperature 0.5 6.0 0.5 1291 G04 0.5 VCC = 5V CLK = 1MHz MAGNITUDE OF GAIN CHANGE (LSB) MAGNITUDE OF LINEARITY CHANGE (LSB) 0.4 1291 G03 MAGNITUDE OF OFFSET CHANGE (LSB) 0.5 CHANGE IN GAIN ERROR (LSB = 1/4096 × VCC (VREF)) CHANGE IN LINEARITY (LSB = 1/4096 • VCC (VREF)) Change in Linearity vs Supply Voltage 0.5 1291 G02 0.4 0.3 0.2 0.1 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) 125 1291 G07 VCC = 5V VCC = 5V CLK = 1MHz MINIMUM CLK FREQUENCY* (MHz) 0 CHANGE IN OFFSET (LSB = 1/4096 • VCC (VREF)) Supply Current vs Temperature Supply Current vs Supply Voltage 0.4 0.3 0.2 0.1 0 50 25 0 75 100 –50 –25 AMBIENT TEMPERATURE (°C) 125 1291 G08 0.25 0.20 0.15 0.10 0.05 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 125 1291 G09 * AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED 1291fa 4 LTC1291 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 250 MAXIMUM CLK FREQUENCY* (MHz) LSB-FIRST DATA 100 50 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 0.8 +VIN 0.6 RSOURCE– – –IN 0.2 0 100 125 1k 10k RSOURCE – (Ω) 100k 1291 G11 Sample-and-Hold Acquisition Time vs Source Resistance +VIN 1k RFILTER CFILTER ≥1µF + – 100 10 1 10 100 1k CYCLE TIME (µs) 10k 1291 G12 Input Channel Leakage Current vs Temperature 1000 100 VCC = 5V TA = 25°C 0V TO 5V INPUT STEP VIN RSOURCE+ INPUT CHANNEL LEAKAGE CURRENT (nA) S/H AQUISITION TIME TO 0.02% (µs) + +IN 0.4 1291 G10 10 MAXIMUM RFILTER** (Ω) DOUT DELAY TIME FROM CLK↓ (ns) MSB-FIRST DATA 150 10k VCC = 5V CLK = 1MHz VCC = 5V 200 Maximum Filter Resistor vs Cycle Time Maximum Clock Rate vs Source Resistance DOUT Delay Time vs Temperature + – 1 100 1k 10k RSOURCE+ (Ω) 900 GUARANTEED 800 700 600 * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED 500 400 300 200 100 ON CHANNEL OFF CHANNEL 0 –50 –30 –10 10 30 50 70 90 110 130 AMBIENT TEMPERATURE (°C) 1291 G13 **MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED 1291 G14 U U U PI FU CTIO S CS (Pin 1): Chip Select Input. A logic low on this input enables the LTC1291. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer. VCC(VREF) (Pin 8): Positive Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. 1291fa 5 LTC1291 W BLOCK DIAGRA 7 VCC (VREF) DIN CH0 CH1 8 INPUT SHIFT REGISTER 5 2 3 ANALOG INPUT MUX OUTPUT SHIFT REGISTER SAMPLE AND HOLD CLK 6 DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC CONTROL AND TIMING 4 GND 1 CS 1291 BD TEST CIRCUITS Load Circuit for tdis and ten Load Circuit for tdDO, tr and tf 1.4V TEST POINT 3k 3k DOUT TEST POINT 5V tdis WAVEFORM 2, ten DOUT 100pF 100pF tdis WAVEFORM 1 1291 TC02 1291 TC05 On and Off Channel Leakage Current Voltage Waveforms for tdis 2.0V CS 5V ION A ON CHANNEL IOFF A DOUT WAVEFORM 1 (SEE NOTE 1) 90% tdis OFF CHANNEL DOUT WAVEFORM 2 (SEE NOTE 2) 1291 TC06 POLARITY 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1291 TC01 1291fa 6 LTC1291 TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO Voltage Waveforms for DOUT Rise and Fall Times, tr, tf CLK 2.4V DOUT 0.8V tdDO 0.4V 2.4V tr tf DOUT 1291 TC04 0.4V 1291 TC03 Voltage Waveforms for ten CS DIN START CLK 2 1 3 4 5 DOUT B11 0.8V ten U W U UO APPLICATI 1291 TC07 S I FOR ATIO The LTC1291 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, half duplex serial interface 5. Control and timing logic being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. CS DIN 1 DIN 2 DOUT 1 DOUT 2 SHIFT MUX 1 NULL SHIFT A/D CONVERSION ADDRESS IN BIT RESULT OUT DIGITAL CONSIDERATIONS Serial Interface The LTC1291 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface (see Operating Sequence). The clock (CLK) synchronizes the data transfer with each bit 1291 F01 Figure 1 The input data is first received and then the A/D conversion result is transmitted (half duplex). Because of the half duplex operation DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and 1291fa 7 LTC1291 U W U UO APPLICATI S I FOR ATIO the conversion appears MSB-first on the DOUT line. The conversion result is output, bit by bit, as the conversion is performed. At the end of the data exchange, CS should be brought high. This resets the LTC1291 in preparation for the next data exchange. DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls, the LTC1291 looks for a start bit. After the start bit is received, a 4-bit input word is shifted into the DIN input which configures the LTC1291 and starts the conversion. After one null bit, the result of Operating Sequence (Example: Differential Inputs (CH0 +, CH1 –)) MSB-FIRST DATA (MSBF = 1) tCYC CS DON'T CARE CLK START ODD/ SIGN PS DIN DOUT DON'T CARE HI-Z MSBF SGL/ DIFF B11 B1 B0 FILLED WITH ZEROES tCONV tSMPL LSB-FIRST DATA (MSBF = 0) tCYC CS DON’T CARE CLK START ODD/ SIGN PS DON'T CARE DIN DOUT MSBF SGL/ DIFF HI-Z B11 tSMPL B1 B0 B11 B1 tCONV FILLED WITH ZEROES 1291 AI03 Power Shutdown Operating Sequence (Example: Differential Inputs (CH0 +, CH1 –) and MSB-First Data) CS SHUTDOWN* REQUEST POWER SHUTDOWN NEW CONVERSION BEGINS CLK START ODD/ SIGN START PS DIN DOUT ODD/ SIGN PS DON'T CARE HI-Z SGL/ DIFF MSBF B11 DATA NOT VALID B0 FILLED WITH ZEROES HI-Z SGL/ DIFF MSBF 1291 AI04 * STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION CS CAN BE BROUGHT HIGH ONCE DIN HAS BEEN CLOCKED IN 1291fa 8 LTC1291 W U U UO APPLICATI S I FOR ATIO Input Data Word The 4-bit data word is clocked into the DIN pin on the rising edge of the clock after chip select goes low and the start bit has been recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The input word is defined as follows: Multiplexer Channel Selection MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + + – – + GND – – MSB-FIRST/ LSB-FIRST START SGL/ DIFF ODD/ SIGN MUX ADDRESS MSBF PS POWER SHUTDOWN 1291 F02 Figure 2. Input Data Word Start Bit The first␣ “logical one” clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer and all leading zeroes which precede this logical one will be ignored. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. MUX Address The bits of the input word following the START BIT assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. Only the “+” inputs have sample-andholds. Signals applied at the “–” inputs must not change more than the required accuracy during the conversion. MSB-First/LSB-First (MSBF) The output data of the LTC1291 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB-first format. Logical zeroes will be filled in indefinitely following the last data bit to accommodate longer word lengths required by some microprocessors. When the MSBF bit is a logical zero, LSB-first data will follow the normal MSB-first data on the DOUT line (see Operating Sequence). Power Shutdown The power shutdown feature of the LTC1291 is activated by making the PS bit a logical zero. If CS remains low after the PS bit has been received, a 12-bit DOUT word with all logical ones will be shifted out followed by logical zeroes until CS goes high. Then the DOUT line will go into its high impedance state. The LTC1291 will remain in the shutdown mode until the next CS cycle. There is no warm-up or wait period required after coming out of the power shutdown cycle so a conversion can commence after CS goes low (see Power Shutdown Operating Sequence). 1291fa 9 LTC1291 W U U UO APPLICATI S I FOR ATIO Output Code The LTC1291 performs a unipolar conversion. The following shows the output code and transfer curve: Unipolar Transfer Curve Unipolar Output Code 111111111111 • • • 000000000001 000000000000 1291 AI05a Microprocessor Interfaces The LTC1291 can interface directly (without external hardware) to most popular microprocessors’s (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1291. Included here are one serial interface example and one example showing a parallel port programmed to form the serial interface. Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB -first and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. The data is right justified in the two memory locations. ANDing the second byte with 0DHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. VIN VREF 4.9988V 4.9976V • • • 0.0012V 0V VREF–1LSB VREF – 1LSB VREF – 2LSB • • • 1LSB 0V VREF–2LSB 111111111111 111111111110 • • • 000000000001 000000000000 111111111110 1LSB INPUT VOLTAGE 0V OUTPUT CODE INPUT VOLTAGE (VREF = 5V) 1291 AI05b Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1291** PART NUMBER TYPE OF INTERFACE Motorola MC6805S2, S3 SPI MC68HC11 SPI MC68HC05 SPI RCA CDP68HC05 SPI Hitachi HD6305 SCI Synchronous HD6301 SCI Synchronous HD63701 SCI Synchronous HD6303 SCI Synchronous HD64180 SCI Synchronous National Semiconductor COP400 Family MICROWIRE† COP800 Family MCROWIRE/PLUS† NS8050U MICROWIRE/PLUS HPC16000 Family MICROWIRE/PLUS Texas Instruments TMS7002 Serial Port TMS7042 Serial Port TMS70C02 Serial Port TMS70C42 Serial Port TMS32011* Serial Port TMS32020* Serial Port TMS370C050 SPI * Requires external hardware ** Contact LTC marketing for interface information for processors not on this list † MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corporation. 1291fa 10 LTC1291 W U U UO APPLICATI S I FOR ATIO Timing Diagram for Interface to the MC68HC11 CS CLK SGL/ START DIFF DIN ODD/ EVEN MSBF DON'T CARE PS DOUT MPU TRANSMIT WORD 0 0 0 0 0 0 1 ODD/ EVEN MSBF SGL/ DIFF PS ? ? ? B9 B8 X X X X B7 X B6 B5 B4 B3 B2 B1 B0 X X X X X X X B2 B1 B0 BYTE 2 ? ? B10 X BYTE 1 MPU RECEIVED WORD B11 ? ? ? ? ? 0 ? B11 BYTE 3 (DUMMY) B10 B8 B9 B7 B6 B5 BYTE 2 BYTE 1 B4 B3 BYTE 3 LTC1291 AI06 Hardware and Software Interface to Motorola MC68HC11 DOUT FROM LTC1291 STORED IN MC68HC11 RAM MSB #62 0 0 0 0 B11 B10 B9 B8 ANALOG INPUTS LSB #63 B7 B6 B5 B4 CH0 BYTE 1 B3 B2 B1 B0 CS D0 CLK SCK LTC1291 DOUT BYTE 2 CH1 DIN MC68HC11 MISO MOSI LTC1291 AI07 MC68HC11 CODE In this example the DIN word configures the input MUX for a single-ended input to be applied to CH0. The conversion result is output MSB-first. LABEL MNEMONIC LDAA STAA LDAA STAA LDAA STAA LDAA STAA OPERAND #$50 $1028 #$1B $1009 #$03 $50 #$60 $51 COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $50 LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $51 LABEL MNEMONIC LDAA STAA LDX LOOP BCLR LDAA STAA OPERAND #$00 COMMENTS LOAD DUMMY DIN WORD INTO ACC A $52 LOAD DUMMY DIN DATA INTO $52 #$1000 LOAD INDEX REGISTER X WITH $1000 $08,X,#$01 D0 GOES LOW (CS GOES LOW) $50 LOAD DIN INTO ACC A FROM $50 $102A LOAD DIN INTO SPI, START SCK 1291fa 11 LTC1291 W U UO LABEL MNEMONIC LDAA WAIT1 BPL LDAA STAA WAIT2 LDAA BPL LDAA STAA LDAA U APPLICATI S I FOR ATIO OPERAND $1029 WAIT1 $51 $102A $1029 WAIT2 $102A $62 $52 COMMENTS CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD DIN INTO ACC A FROM $51 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1291 MSBs INTO ACC A STORE MSBs IN $62 LOAD DUMMY DIN INTO ACC A FROM $52 Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to show the interface between the LTC1291 and parallel port microprocessors. Usually the signals CS, DIN and CLK are generated on three port lines and the DOUT signal is read on a fourth port line. LABEL MNEMONIC STAA OPERAND $102A WAIT3 LDAA BPL BSET LDAA STAA $1029 WAIT3 $08,X#$01 $102A $63 COMMENTS LOAD DUMMY DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE D0 GOES HIGH (CS GOES HIGH) LOAD LTC1291 LSBs IN ACC STORE LSBs IN $63 LOOP START NEXT CONVERSION JMP This works very well. One can save a line by tying the DIN and DOUT lines together. The 8051 first sends the start bit and MUX Address to the LTC1291 over the line connected to P1.2. Then P1.2 is reconfigured as an input and the 8051 reads back the 12-bit A/D result over the same data line. Timing Diagram for Interface to Intel 8051 PS BIT LATCHED INTO LTC1291 CS 1 3 2 4 5 CLK SGL/ DIFF MSBF ODD/ START SIGN DATA (DIN/DOUT) B11 B10 B9 PS B8 B7 B6 B5 B4 B3 B2 B1 LTC1291 SENDS A/D RESULT BACK TO 8051 P1.2 8051 P1.2 OUTPUT DATA TO LTC1291 B0 LTC1291 AI08 LTC1291 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK 8051 P1.2 RECONFIGURED AS INPUT AFTER THE 5TH RISING CLK BEFORE THE 5TH FALLING CLK Hardware and Software Interface to Intel 8051 DOUT FROM LTC1291 STORED IN 8051 RAM MSB R2 B11 CH0 B10 B9 B8 B7 B6 B5 B4 ANALOG INPUTS LSB R1 B3 B2 B1 B0 0 0 0 CS P1.4 CLK P1.3 DOUT P1.2 LTC1291 0 CH1 8051 DIN MUX ADDRESS LTC1291 AI09 A/D RESULT 1291fa 12 LTC1291 W U U UO APPLICATI S I FOR ATIO 8051 Code In this example the input MUX is configured to accept a differential input between CH0 and CH1. The result from the conversion is clocked out MSB-first. LABEL MNEMONIC SETB CONT MOV CLR MOV LOOP1 RLC CLR MOV SETB DJNZ MOV CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV SETB OPERAND P1.4 A,#98H P1.4 R4,#05H A P1.3 P1.2,C P1.3 R4,LOOP1 P1,#04H P1.3 R4,#09H C,P1.2 A P1.3 P1.3 R4,LOOP R2,A C,P1.2 P1.3 COMMENTS CS GOES HIGH DIN WORD FOR LTC1291 CS GOES LOW LOAD COUNTER ROTATE DIN BIT INTO CARRY CLK GOES LOW OUTPUT DIN BIT TO LTC1291 CLK GOES HIGH NEXT DIN BIT P1.2 BECOMES AN INPUT CLK GOES LOW LOAD COUNTER READ DATA BIT INTO CARRY ROTATE DATA BIT (B3) INTO ACC CLK GOES HIGH CLK GOES LOW NEXT DOUT BIT STORE MSBS IN R2 READ DATA BIT INTO CARRY CLK GOES HIGH LABEL MNEMONIC CLR CLR RLC MOV RLC SETB CLR MOV RLC SETB CLR MOV SETB RRC RRC RRC RRC MOV AJMP Sharing the Serial Interface The LTC1291 can share the same 3-wire serial interface with other peripheral components or other LTC1291s 2 1 OPERAND P1.3 A A C,P1.2 A P1.3 P1.3 C,P1.2 A P1.3 P1.3 C,P1.2 P1.4 A A A A R3,A CONT COMMENTS CLK GOES LOW CLEAR ACC ROTATE DATA BIT (B3) INTO ACC READ DATA BIT INTO CARRY ROTATE DATA BIT (B2) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY ROTATE DATA BIT (B1) INTO ACC CLK GOES HIGH CLK GOES LOW READ DATA BIT INTO CARRY CS GOES HIGH ROTATE DATA BIT (B0) INTO ACC ROTAGE RIGHT INTO ACC ROTAGE RIGHT INTO ACC ROTAGE RIGHT INTO ACC STORE LSBs IN R3 START NEXT CONVERSION (Figure 3). The CS signals decide which LTC1291 is being addressed by MPU. 0 OUTPUT PORT SERIAL DATA MPU 3-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1291s 3 3 3 3 CS LTC1291 CS LTC1291 2 CHANNELS 2 CHANNELS CS LTC1291 2 CHANNELS LTC1291 F03 Figure 3. Several LTC1291s Sharing One 3-Wire Serial Interface 1291fa 13 LTC1291 U W U UO APPLICATI S I FOR ATIO Grounding The LTC1291 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length. Figure 4 shows an example of an ideal LTC1291 ground plane for a two-sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. 22µF TANTALUM LTC1291 ANALOG GROUND PLANE Figure 5. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors 7 3 6 4 5 CS VERTICAL: 0.5mV/DIV 8 2 HORIZONTAL: 10µs/DIV VCC 0.1µF 1 VERTICAL: 0.5mV/DIV ANALOG CONSIDERATIONS VCC HORIZONTAL: 10µs/DIV LTC1291 F04 Figure 4. Example Ground Plane for the LTC1291 Bypassing For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to ground during the conversion cycle can induce error or noise in the output code. VCC noise and ripple can be kept below 0.5mV by bypassing the VCC pin directly to the analog ground plane with a minimum of 22µF tantalum capacitor and with leads as short as possible. A 0.1µF ceramic disk capacitor should also be placed directly across VCC (Pin 8) and GND (Pin 4) as close to the pins as possible. The VCC supply should have a low output impedance such as that obtained from a voltage regulator (e.g., LT323A). Figures 5 and 6 show the effects of good and poor VCC bypassing. Figure 6. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1291 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. If large source resistances are used or if slow settling op amps drive the inputs, take care to insure the transients caused by the current spikes settle completely before the conversion begins. Minimizing Gain and Offset Error Because the LTC1291’s reference is taken from the power supply pin (VCC), proper PC board layout and supply bypassing is important for attaining the best performance from the A/D converter. Any parasitic resistance in the VCC 1291fa 14 LTC1291 W U U UO APPLICATI S I FOR ATIO or GND lead will cause gain errors and offset errors (Figure 7). For the best performance the LTC1291 should be soldered directly to the PC board. If the source can not be placed next to the pin and the gain parameter is important, the pin should be Kelvin-sensed to eliminate parasitic resistances due to long PC traces. For example, 0.1Ω of resistance in the VCC lead can typically cause 0.5LSB (ICC • 0.1Ω/ VCC) of gain error for VCC = 5V. When the input MUX is selected for single-ended input the minus terminal is connected to GND internally on the die. Any parasitic resistance from the GND pin to the ground plane will lead to an offset voltage (ICC • RP2). VCC RP1 LTC1291 D/A 5V REF + REF – – + RP2 GND LTC1291 F07 Figure 7. Parasitic Resistance in the VCC and GND Leads Source Resistance The analog inputs of the LTC1291 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON). CIN gets switched between “+” and “–” inputs once during each conversion cycle. Large external source resistors RSOURCE + “+” INPUT C1 LTC1291 3RD CLK↑ RON = 500Ω “–” INPUT 5TH CLK↓ VIN + RSOURCE – CIN = 100pF VIN – C2 LTC1291 F08 and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time. “+” Input Settling The input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 9). The sample period is 2.5 CLK cycles before a conversion starts. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 2.5µs, RSOURCE+ < 1.0k and C1 < 20pF will provide adequate settle time. “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 9). During the conversion, the “+” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. It is critical that the “–” input voltage be free of noise and settle completely during the first CLK cycle of the conversion. Minimizing RSOURCE – and C2 will improve settling time. If large “–” input source resistance must be used, the time can be extended by using a slower CLK frequency. At the maximum CLK frequency of 1MHz, RSOURCE – < 250Ω and C2 < 20pF will provide adequate settling. Input Op Amps When driving the analog inputs with an op amp, it is important that the op amp settles within the allowed time (see Figure 9). Again the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 2.5µs (“+” input) and 1µs (“–” input) that occurs at the maximum clock rate of 1MHz. Figures 10 and 11 show examples adequate and poor op amp settling. Figure 8. Analog Input Equivalent Circuit 1291fa 15 LTC1291 U W U UO APPLICATI S I FOR ATIO HOLD SAMPLE CS CLK DIN SGL/ DIFF START ODD/ SIGN MSBF PS tSMPL “+” INPUT MUST SETTLE DURING THIS TIME DOUT B11 HI-Z 1ST BIT TEST “–” INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1291 F09 VERTICAL: 5mV/DIV VERTICAL: 5mV/DIV Figure 9. “+” and “–” Input Settling Windows HORIZONTAL: 500ns/DIV Figure 10. Adequate Settling of Op Amp Driving Analog Input HORIZONTAL: 20µs/DIV Figure 11. Poor Op Amp Settling Can Cause A/D Errors (Note Horizontal Scale) 1291fa 16 LTC1291 U W U UO APPLICATI S I FOR ATIO RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 12. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and a large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF • VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 18.5µs, the input current equals 27µA at VIN = 5V. Here a filter resistor of 4.5Ω will cause 0.1LSB of full-scale error. If a large filter resistor must be used, errors can be reduced by increasing the cycle time as shown in the Typical Performance Characteristics curve Maximum Filter Resistor vs Cycle Time. RFILTER IDC VIN – “+” CFILTER LTC1291 “–” LTC1291 F12 Figure 12. RC Input Filtering Input Leakage Current Input leakage currents also can create errors if the source resistance gets too large. For example, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1k will cause a voltage drop of 1mV or 0.8LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical performance characteristics curve Input Channel Leakage Current vs Temperature). allows the LTC1291 to convert rapidly varying signals (see typical performance characteristics curve of S/H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 9. The sampling interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling edge of the PS bit is received. On this falling edge, the S/H goes into the hold mode and the conversion begins. Differential Input With a differential input the A/D no longer converts a single voltage but converts the difference between two voltages. The voltage on the +IN pin is sampled and held and can be rapidly time varying. The voltage on the –IN pin must remain constant and be free of noise and ripple throughout the conversion time. Otherwise the differencing operation will not be done accurately. The conversion time is 12 CLK cycles. Therefore a change in the –IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the –IN input this error would be:   VERROR(MAX) = 2π f(−IN)VPEAK  12   fCLK  ( ) Where f(–IN) is the frequency of the –IN input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. Usually VERROR will not be significant. For a 60Hz signal on the –IN input to generate a 0.25LSB error (300µV) with the converter running at CLK = 1MHz, its peak value would have to be 66mV. Rearranging the above equation, the maximum sinusoidal signal that can be digitized to a given accuracy is given as:  VERROR(MAX)  f(−IN) =    2πVPEAK   fCLK    12  For 0.25LSB error (300µV), the maximum input sinusoid with a 5V peak amplitude that can be digitized is 0.8Hz. SAMPLE-AND-HOLD Single-Ended Input The LTC1291 provides a built-in sample-and-hold (S/H) function on the +IN input for signals acquired in the singleended mode (–IN pin grounded). The sample-and-hold 1291fa 17 LTC1291 U W U UO APPLICATI S I FOR ATIO Overvoltage Protection Applying signals to the LTC1291’s analog inputs that exceed the positive supply or that go below ground will degrade the accuracy of the A/D and possibly damage the device. For example, this condition will occur if a signal is applied to the analog inputs before power is applied to the LTC1291. It can also happen if the input source is operating from supplies of larger value than the LTC1291 supply. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp, or current limit the input source. There are two ways to protect the inputs. In Figure 13 diode clamps from the inputs to VCC and GND are used. The second method is to put resistors in series with the analog inputs for current limiting. Limit the current to 15mA per channel. The +IN input can accept a resistor value of 1k but the –IN input cannot accept more than 250Ω when clocked at its maximum clock frequency of 1MHz. If the LTC1291 is clocked at the maximum clock frequency and 250Ω is not enough to current limit the input source, then the clamp diodes are recommended (Figures 14 and 15). The reason for the limit on the resistor value is that the MSB bit test is affected by the value of the resistor placed at the –IN input (see discussion on Analog Inputs and the typical performance characteristics Maximum CLK Rate vs Source Resistance). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device. 1N4148 DIODES CS 5V VCC (VREF) CH0 CLK LTC1291 CH1 DOUT GND DIN LTC1291 F13 Figure 13. Overvoltage Protection for Inputs CS VCC (VREF) 5V 1k CH0 250Ω CLK LTC1291 CH1 DOUT GND DIN LTC1291 F14 Figure 14. Overvoltage Protection for Inputs 1N4148 DIODES CS VCC (VREF) 5V 1k CH0 CLK LTC1291 CH1 DOUT GND DIN LTC1291 F15 Figure 15. Overvoltage Protection for Inputs 1291fa 18 LTC1291 W U U UO APPLICATI S I FOR ATIO A “Quick Look” Circuit for the LTC1291 Users can get a quick look at the function and timing of the LTC1291 by using the following simple circuit (Figure 16). DIN is tied to VCC. This requires VIN be applied to CH1 with respect to the ground plane. The data is output MSB-first. CS is driven at 1/64, the clock frequency by the 74HC393 and DOUT outputs the data. The output data from the DOUT pin can be viewed on a oscilloscope that is set up to trigger on the falling edge of CS (Figure 17). 22µF TANTALUM + 5V f/64 CS 0.1µF CH0 VIN CLK LTC1291 CH1 DOUT GND 0.1µF A1 VCC CLR1 A2 1QA CLR2 1QB 74HC393 2QA 1QC 2QB 1QD 2QC GND 2QD VCC (VREF) f DIN CLOCK IN 1MHz TO OSCILLOSCOPE LTC1291 F16 Figure 16. “Quick Look” Circuit for the LTC1291 CLK CS DOUT NULL BIT MSB (B11) LSB (B0) FILLS WITH ZEROES VERTICAL: 5V/DIV HORIZONTAL: 5µs/DIV Figure 17. Scope Trace of the LTC1291 "Quick Look" Circuit Showing Output 101010101010 (AAAHEX) 1291fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1291 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .200 (5.080) MAX .300 BSC (7.62 BSC) CORNER LEADS OPTION (4 PLCS) .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) .405 (10.287) MAX .005 (0.127) MIN 8 7 6 5 .025 (0.635) RAD TYP .220 – .310 (5.588 – 7.874) 0° – 15° 1 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .045 – .065 (1.143 – 1.651) .014 – .026 (0.360 – 0.660) .100 (2.54) BSC 2 3 4 .125 3.175 MIN J8 0801 OBSOLETE PACKAGE N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .065 (1.651) TYP ) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ± .015* (6.477 ± 0.381) .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 (0.457 ± 0.076) N8 1002 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1298 12-bit, 2-Channel, Micropower ADC in SO-8 11.1ksps, Autoshutdown LTC1861 12-bit, 2-Channel, 250ksps ADC in MSOP 850µA Supply Current, 2µA at 1ksps LTC1865 16-bit, 2-Channel, 250ksps ADC in MSOP 850µA Supply Current, 2µA at 1ksps 1291fa 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT/TP 0703 1K REV A • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 1992