LTC1329ACS8-50#TRPBF

LTC1329-10/ LTC1329-50/LTC1329A-50 Micropower 8-Bit Current Output D/A Converter U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC ®1329-10/LTC1329-50/LTC1329A-50 are micropower 8-bit current output D/A converters (DACs) with an output range of 0µA to 10µA for the LTC1329-10 and 0µA to 50µA for the LTC1329-50/LTC1329A-50. The DAC current output can be biased from – 15V to 2V or – 15V to 2.5V in 3.3V and 5V systems, respectively. Supply current is only 95µA for the LTC1329-50/LTC1329A-50 and 75µA for LTC1329-10. A shutdown mode drops the supply current to 0.2µA. Guaranteed Precision Full-Scale DAC Output Current at 25°C: LTC1329A-50 50µA ±1% LTC1329-10 10µA ±3% LTC1329-50 50µA ±3% Wide Output Voltage DC Compliance: – 15V to 2.5V Wide Supply Range: 2.7V ≤ VCC ≤ 6.5V Supply Current in Shutdown: 0.2µA Low Supply Current: 75µA for LTC1329-10, 95µA for LTC1329-50/LTC1329A-50 Available in 8-Pin SO Triple ModeTM Interface Modes 1. Standard 3-Wire Mode 2. Pulse Mode 1-Wire Interface: Increment-Only 3. Pulse Mode 2-Wire Interface: Increment/Decrement Can Read Back the 8-Bit DAC Value in 3-Wire Mode DAC Powers Up at Midrange DAC Contents Are Retained in Shutdown The LTC1329 can communicate with external circuitry by using one of three interface modes: standard 3-wire serial mode and two pulse modes. Upon power-up, the internal counter resets to 1000 0000B, the DAC output assumes midrange and the chip is configured in 3-wire or pulse mode depending on the signal level at CS. In 3-wire mode, the system MPU can serially transfer 8-bit data to and from the LTC1329. In pulse mode, the upper six bits of the DAC output can be programmed for increment-only (1-wire interface) or increment/decrement (2-wire interface) operation depending on the signal level at DIN. U APPLICATIONS ■ ■ ■ ■ LCD Contrast Control Backlight Brightness Control Battery Charger Current/Voltage Adjustment Power Supply Voltage Adjustment Trimmer Pot Elimination LTC1329 is available in 8-pin SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Triple Mode is a trademark of Linear Technology Corporation. U ■ TYPICAL APPLICATION Digitally Controlled LCD Bias Generator VIN 5V 47Ω L1* 100µH 1N4148 200k 0.1µF 1 ILIM + 47µF VIN SW1 LT ®1173 FB GND SW2 2 3 4.7µF 10.1k 4 1N5818 + 22µF *GOWANDA GA10-103K OR COILTRONICS CTX100-4 DOUT VCC DIN 8 7 LTC1329-50 + 1N5818 IOUT SHDN CLK GND CS 6 MPU (e.g., 8051) 5 P1.2 P1.1 P1.0 220k VOUT –22V at 40mA 1329 TA01 1 LTC1329-10/ LTC1329-50/LTC1329A-50 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Supply Voltage (VCC) ................................................ 7V Input Voltage (All Inputs)............ – 0.3V to (VCC + 0.3V) Output Voltage IOUT ......................................... – 15V to (VCC + 0.3V) DOUT ....................................... – 0.3V to (VCC + 0.3V) Short-Circuit Duration (All Outputs) ............... Indefinite Operating Temperature Range .................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW IOUT 1 8 DOUT VCC 2 7 DIN (UP/DN) SHDN 3 6 GND CLK 4 LTC1329CS8-10 LTC1329CS8-50 LTC1329ACS8-50 5 CS S8 PART MARKING 13291 1329A5 13295 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 150°C/ W Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VCC ICC Supply Current DAC Resolution DAC Full-Scale Current DAC Zero-Scale Current DAC Differential Nonlinearity Supply Voltage Rejection IIH, IIL VIH VIL VOH VOL IOZ 2 VCC = 3.3V, TA = 25°C, unless otherwise specified. LTC1329-10 MIN TYP MAX 2.7 6.5 75 130 LTC1329-50/LTC1329A-50 MIN TYP MAX 2.7 6.5 95 150 0.2 8 10 10 10.3 10.5 0.2 8 50 50 50 50 ● ±0.3 200 ±0.9 ● ±1 ±2 ● ±2.5 ±4 ● ±0.25 CONDITIONS ● VSHDN = VDIN = VCS = VCC, VCLK = 0V, DOUT = NC, IOUT = NC Shutdown Output Voltage at IOUT = 0.45V, TA = 25°C (LTC1329-10, LTC1329-50) Output Voltage at IOUT = 0.45V, TA = 25°C (LTC1329A-50) Output Voltage at IOUT = 0.45V Monotonicity Guaranteed VCC = 3V to 5.5V, IOUT = Full Scale, Output Voltage at IOUT = 0.45V VCC = 2.7V to 6.5V, Full Scale, Output Voltage at IOUT = 0.45V Output Voltage Rejection VCC = 5V, IOUT = Full Scale, Output Voltage at IOUT = – 15V to 0V VCC = 5V, IOUT = Full Scale, Output Voltage at IOUT = 0V to 2.5V Logic Input Current 0V ≤ VIN ≤ VCC High Level Input Voltage VCC = 5V VCC = 3.3V Low Level Input Voltage VCC = 5V VCC = 3.3V High Level Output Voltage VCC = 5V, IO = 400µA VCC = 3.3V, IO = 400µA Low Level Output Voltage VCC = 5V, IO = 2mA VCC = 3.3V, IO = 1mA Three-State Output Leakage VCS = VCC ● ● ● 9.7 9.5 51.5 52.5 50.5 51.0 200 ±0.9 µA Bits µA µA µA µA nA LSB ±1 ±2 LSB ±2.5 ±4 LSB ±1 ±0.25 LSB ±1.5 ±1.5 LSB ±1 µA V V V V V V V V µA 5 ● ● ● ● ● 2.0 1.9 ● ● ● 5 2.0 1.9 0.80 0.45 ● ● ● ● 48.5 47.5 49.5 49.0 ±1 ● UNITS V µA 2.4 2.1 0.80 0.45 2.4 2.1 0.4 0.4 ±5 0.4 0.4 ±5 LTC1329-10/ LTC1329-50/LTC1329A-50 U U U U WW RECO E DED OPERATI G CO DITIO S SYMBOL PARAMETER VCC = 3.3V, unless otherwise specified. (Notes 2, 3) CONDITIONS MIN TYP MAX UNITS Serial Interface fCLK Clock Frequency ● tCKS Setup Time, CLK↓ Before CS↓ ● 150 ns tCSS Setup Time, CS↓ Before CLK↑ ● 400 ns tDV CS↓ to DOUT Valid ● 150 ns tDS DIN Setup Time Before CLK↑ ● 150 ns tDH DIN Hold Time After CLK↑ ● 150 ns tDO CLK↓ to DOUT Valid ● 150 ns tCKHI CLK High Time ● 200 ns tCKLO CLK Low Time ● 250 ns tCSH CLK↓ Before CS↑ ● 150 tDZ CS↑ to DOUT in Hi-Z tCKH CS↑ Before CLK↑ tCSLO CS Low Time tCSHI CS High Time See Test Circuits See Test Circuits See Test Circuits fCLK = 2MHz (Note 4) VCLK = 0V 2 MHz ns ● 400 ns ● 400 ns ● ● 4550 400 ns ns ● 400 ns Note 2: Timing for all input signals is measured at 0.8V for a High-to-Low transition and at 2V for a Low-to-High transition. Note 3: Timing specification are guaranteed but not tested. Note 4: This is the minimum time required for valid data transfer. The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. U W TYPICAL PERFORMANCE CHARACTERISTICS LTC1329-10 DNL vs Code TA = 25°C VCC = 3.3V V(IOUT) = 0.45V 0.8 0.6 1.0 TA = 25°C VCC = 3.3V V(IOUT) = 0.45V 0.8 0.6 0.6 0.4 0.2 0.2 0.2 0 DNL (LSB) 0.4 –0.2 0 –0.2 0 –0.2 –0.4 –0.4 –0.4 –0.6 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 0 32 64 96 128 160 192 224 256 CODE 1392 G01 TA = 25°C VCC = 3.3V V(IOUT) = 0.45V 0.8 0.4 INL (LSB) DNL (LSB) LTC1329-50 DNL vs Code LTC1329-10 INL vs Code 1.0 1.0 –1.0 0 32 64 96 128 160 192 224 256 CODE 1329 • TPC02 0 32 64 96 128 160 192 224 256 CODE 1392 G03 3 LTC1329-10/ LTC1329-50/LTC1329A-50 U W TYPICAL PERFORMANCE CHARACTERISTICS LTC1329-10/LTC1329-50 FullScale Current vs Temperature LTC1329-50 INL vs Code 2 3 0.6 FULL-SCALE IOUT ERROR (LSB) TA = 25°C VCC = 3.3V V(IOUT) = 0.45V 0.8 0.4 0.2 0 –0.2 –0.4 –0.6 VCC = 3.3V V(IOUT) = 0.45V 2 FULL-SCALE IOUT ERROR (LSB) 1.0 INL (LSB) LTC1329-10/LTC1329-50 Supply Voltage Rejection 1 0 LTC1329-50 –1 LTC1329-10 –2 TA = 25°C V(IOUT) = 0.45V 1 LTC1329-50 0 LTC1329-10 –1 –0.8 –3 –1.0 0 32 64 96 128 160 192 224 256 CODE 0 10 40 30 50 20 TEMPERATURE (°C) ZERO-SCALE IOUT CURRENT (nA) FULL-SCALE IOUT ERROR (LSB) 0.3 0.2 LTC1329-50 0 LTC1329-10 –0.1 –0.2 –0.3 50 6.5 40 6.0 30 20 0 –10 –30 –40 –50 –15 –12 6 LTC1329-10 –20 –0.5 –15 –12 3 LTC1329-50 10 –0.4 –6 –3 0 –9 IOUT BIAS VOLTAGE (V) 1 4 3 5 2 SUPPLY VOLTAGE (V) 6 7 Maximum IOUT Bias Voltage vs Supply Voltage MAXIMUM IOUT BIAS VOLTAGE (V) 0.5 TA = 25°C VCC = 3.3V 0 1329 G06 LTC1329-10/LTC1329-50 Bias Voltage Rejection (Zero-Scale Current) LTC1329-10/LTC1329-50 Bias Voltage Rejection (Full-Scale Current) 0.1 –2 70 1329 G05 1329 • TPC04 0.4 60 TA = 25°C IOUT = FULL-SCALE CURRENT 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 –6 –3 0 –9 IOUT BIAS VOLTAGE (V) 1329 G07 3 6 1329 G08 2.7 3.2 3.7 4.2 4.7 5.2 5.7 SUPPLY VOLTAGE (V) 6.2 6.7 1329 • TPC09 U U U PIN FUNCTIONS IOUT (Pin 1): DAC Current Output. In 3.3V or 5V systems, the DAC current output can be biased from – 15V to 2V or – 15V to 2.5V respectively. VCC (Pin 2): Voltage Supply (2.7V ≤ VCC ≤ 6.5V). This supply must be kept free from noise and ripple by bypassing directly to the ground plane. SHDN (Pin 3): Shutdown. A logic low puts the chip into Shutdown mode. The digital setting for the DAC is retained. CLK (Pin 4): Shift Clock. This clock synchronizes the serial data in 3-wire mode. This pin has a Schmitt trigger input. 4 CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low on this CS pin enables the LTC1329. Upon power-up, a logic high at CS puts the chip into pulse mode. If CS ever goes low, the chip is configured in 3-wire mode until the next power is cycled. GND (Pin 6): Ground. Ground should be tied directly to a ground plane. DIN (UP/DN)(Pin 7): Data Input. In 3-wire mode, the DAC data is shifted into DIN on the rising edge of CLK. In pulse mode, upon power-up a logic high at DIN puts the counter into increment-only mode. If DIN ever goes low, the LTC1329-10/ LTC1329-50/LTC1329A-50 U U U PIN FUNCTIONS counter is configured in increment/decrement mode until the power is cycled. DOUT (Pin 8): Data Output. In 3-wire mode, on every conversion DOUT serially outputs the previous 8-bit DAC data. In pulse mode, DOUT is three-stated. W BLOCK DIAGRA LATCH AND LOGIC POWER-ON RESET VOLTAGE REFERENCE SHDN V CC UP ONLY/ UP/DN LATCH AND LOGIC SHDN MODE SELECT 0 = PULSE 1 = 3-WIRE 8-BIT CURRENT DAC IOUT 8 CLK CLK 8-BIT DAC REGISTER/COUNTER UP/DN DIN (UP/DN) CONTROL LOGIC CS SHDN 8 8 CLK 9-BIT SHIFT REGISTER DOUT DOUT DIN 1329 BD TEST CIRCUITS Voltage Waveforms for tDO Voltage Waveforms for t DZ, tDV CLK 2.0V CS 0.8V 0.8V t DO 2.4V DOUT 0.4V 1329 TC03 90% 2.4V DOUT HI-Z SET HIGH DOUT HI-Z SET LOW HI-Z t DZ t DV HI-Z 0.4V 10% 1329 TC04 Load Circuit for t DO Load Circuit for t DZ, t DV 1.4V 3k 3k DOUT 5V t DZ WAVEFORM 2, t DV DOUT 100pF 1329 TC01 100pF t DZ WAVEFORM 1 1329 TC02 5 LTC1329-10/ LTC1329-50/LTC1329A-50 U U SERIAL I/O OPERATI G SEQUE CE tCSLO tCSHI CS tCKS tCKHI tCSH CLK tCSS DIN tDS D6 D7 D5 D4 D3 D2 DOUT D1 D0 tDO tDV Hi-Z tCKH tCKLO tDH D7′ D6′ D5′ D4′ D3′ tDZ D2′ D1′ D0′ D7 Hi-Z 1329 F01 Figure 1. 3-Wire Interface Timing Specification U W U U APPLICATIONS INFORMATION 8-BIT CURRENT OUTPUT DAC The LTC1329-10/LTC1329-50/LTC1329A-50 are 8-bit, current output digital-to-analog (DAC) converters. For each part, the 8-bit DAC output is guaranteed monotonic and is digitally adjustable in 256 equal steps. Upon power up, the internal DAC register resets to 10000000B and the DAC output assumes midrange. The current output (IOUT) can be biased from – 15V to 2V or – 15V to 2.5V in 3.3V and 5V systems, respectively. The LTC1329-10 features a fullscale output of 10µA trimmed to ±3% at room temperature (±5% over temperature), while the LTC1329-50 features a 50µA full scale and two accuracy grades; ±1% at room temperature (±2% over temperature) for the LTC1329A-50 and ±3% at room temperature (±5% over temperature) for the LTC1329-50. All versions include a flexible serial digital interface which allows easy interconnection to a variety of digital systems. If the CS line ever goes low (as it will at the beginning of a valid 3-wire serial transfer) the chip immediately reconfigures itself into 3-wire mode and remains in this mode until the next time the power is cycled. If CS stays high, the LTC1329 family stays in pulse mode and watches the UP/DN pin to determine whether to switch to 2-wire mode. If UP/DN ever goes low (as it will the first time a “down” command is given) the chip switches into 2-wire pulse mode and remains in this mode until the next time the power is cycled. In a properly configured 1-wire system, CS and UP/DN will stay high continuously and the LTC1329-10/LTC1329-50/LTC1329A-50 will remain in 1wire pulse mode. 2-wire pulse mode systems should give a single “down” pulse sometime before the first data pulses are sent to prevent the LTC1329 family from staying in 1-wire mode if the first several pulses happen to be “ups”. POWER-UP DIGITAL INTERFACE Automatic Mode Selection The LTC1329 family includes a serial interface capable of communicating with the host system using one of three protocols; standard 3-wire mode, a 2-wire up/down pulse mode and a 1-wire increment-only pulse mode. The LTC1329 family is designed to auto-configure itself depending on the way data is presented to it. A diagram illustrating this auto detection behavior is shown in Figure 2. At power-up, the interface is set to 1-wire pulse mode. 6 CS STAYS HIGH CS GOES LOW 3-WIRE MODE PULSE MODE DIN (UP/DN) GOES LOW DIN STAYS HIGH INCREMENT/ DECREMENT INCREMENTONLY 1329 F02 Figure 2. LTC1329 Operating Modes LTC1329-10/ LTC1329-50/LTC1329A-50 U U W U APPLICATIONS INFORMATION Standard 3-Wire Mode (Figure 3) Refer to the Serial Interface Operating Sequence in Figure 1. When operating in 3-wire mode, the LTC1329-10/ LTC1329-50/LTC1329A-50 will interface directly with most standard 3- or 4-wire serial interface systems. The clock (CLK) input synchronizes the data transfer with each input bit captured at the rising edge of CLK and each output data bit shifted out through DOUT at the falling edge. A falling edge at CS initiates the data transfer and brings the DOUT pin out of three-state. The serial 8-bit data representing the new DAC setting is shifted into the DIN pin. Simultaneously, the previous DAC setting is shifted out of the DOUT pin. After the new data is shifted in, a rising edge at CS transfers the data from the input shift register into the DAC register. The DAC output assumes the new value and the DOUT pin returns to a high-impedance state. IOUT = (B7 B6 B5 B4 B3 B2 B1 B0)IFULLSCALE/255 IOUT 1 2 VCC IOUT DOUT VCC DIN 8 7 LTC1329 0.1µF SHDN CLK 3 4 SHDN GND CLK CS 6 5 IOUT 1 2 VCC IOUT DOUT VCC DIN 8 7 LTC1329 0.1µF SHDN CLK 3 4 SHDN GND CLK CS 6 5 1329 F04 Figure 4. Pulse Mode: Increment Only (1-Wire Control by CLK) 2-Wire Interface (Pulse Mode, Figure 5) In 2-wire pulse mode, a logic HIGH at UP/DN programs the DAC register to increment and each rising edge at CLK increments the upper six bits of the register by one count. Similarly, a logic LOW at UP/DN set the DAC register to decrement and a rising edge at CLK decrements the upper six bits of the register by one count. Each count in 2-wire mode changes the DAC output by a single four LSB step. The DAC register stops incramenting at 11111100B and stops decrementing at 00000000B and will not roll over in 2-wire pulse mode. The last two LSBs are always zero in pulse mode. IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 CS DIN DOUT 1329 F03 DIN AND DOUT CAN BE TIED TOGETHER FOR HALF DUPLEX DATA TRANSFER To configure the LTC1329-10/LTC1329-50/LTC1329A-50 in 2-wire pulse mode, tie CS to VCC and bring the UP/DN pin low at least once during power-up. Figure 3. 3-Wire Mode; Serial Interface (3-Wire Control by CS, CLK and DIN) 1-Wire Interface (Pulse Mode, Figure 4) In 1-wire pulse mode, each rising edge at CLK increments the upper six bits of the DAC register by one count. When incramented beyond 11111100B, the counter rolls over and sets the DAC to the minimum value (00000000B). In this way, a single pulse applied to CLK increases the DAC output by a single 4-LSB step and 63 pulses decrease the DAC output by one step. The last two LSBs are always zero in pulse mode. IOUT 1 2 VCC IOUT DOUT VCC DIN 8 7 LTC1329 0.1µF SHDN CLK 3 4 SHDN CLK UP/DN GND CS 6 5 1329 TA04 Figure 5. Pulse Mode; Increment/Decrement (2-Wire Control by CLK and UP/DN) IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255 To configure the LTC1329-10/LTC1329-50/LTC1329A-50 in 1-wire pulse mode, tie both the CS and DIN pins to VCC. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7 LTC1329-10/ LTC1329-50/LTC1329A-50 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) 0.189 – 0.197* (4.801 – 5.004) (LTC DWG # 05-08-1610) 7 8 0.010 – 0.020 × 45° (0.254 – 0.508) 0.053 – 0.069 (1.346 – 1.752) 0.008 – 0.010 (0.203 – 0.254) 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 0.050 (1.270) TYP 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 6 1 2 3 4 SO8 0996 U TYPICAL APPLICATIONS Pulse Mode: Increment-Only (1-Wire Control by CLK) with Voltage Output VOUT 6 VCC 7 – RFB 100k LT1006 + 4 1 2 2 VBIAS IOUT DOUT VCC DIN 0.1µF 3 SHDN VEE CLK 8 7 LTC1329 3 4 GND SHDN CS CLK 6 5 FOR VCC = 3.3V, –15V ≤ VBIAS ≤ 2V FOR VCC = 5V, –15V ≤ VBIAS ≤ 2.5V VOUT = (–IOUT)(RFB + VBIAS) VEE < VBIAS + VOUT 1329 TA02 Digitally Controlled Power Supply Adjustment VIN 3V L1* 33µH 47Ω 1N5817 + 510k ILIM + 47µF VOUT 5V (150mA) TO 30V (14mA) IOUT DOUT VCC DIN 8 7 LTC1329-50 3 LT1107 GND 2 100µF VIN SW1 FB SW2 1 4 SHDN CLK 22k *COILTRONICS CTX33-4 GND CS 6 MPU (e.g., 8051) 5 P1.2 P1.1 P1.0 1329 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1451 12-Bit Micropower Serial Input VOUT DAC Higher Resolution, 8-Pin SO LTC1452 12-Bit Multiplying Serial Input VOUT DAC Higher Resolution, 8-Pin SO LTC8043 12-Bit Multiplying Serial Input IOUT DAC Higher Resolution, 8-Pin SO 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1329f LT/TP 0297 5K • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 1997