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LTC1344AIG#PBF

LTC1344AIG#PBF

  • 厂商:

    LINEAR(凌力尔特)

  • 封装:

    SSOP24_8.2X5.3MM

  • 描述:

    Cable Terminator 6 Terminations 24-SSOP

  • 数据手册
  • 价格&库存
LTC1344AIG#PBF 数据手册
LTC1344A Software-Selectable Cable Terminator U DESCRIPTION FEATURES ■ ■ The LTC ®1344A features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 (V.11) 100Ω minimum differential load, V.35 T-network load or an open circuit for use with RS232 (V.28) or RS423 (V.10) transceivers that provide their own termination. When combined with the LTC1543 and LTC1544, the LTC1344A forms a complete software-selectable multiprotocol serial port. A data bus latch feature allows sharing of the select lines between multiple interface ports. Software-Selectable Cable Termination for: RS232 (V.28) RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35 V.36 X.21 Outputs Won’t Load the Line with Power Off The LTC1344A is similar to the LTC1344 except for a difference in the Mode Selection table. U APPLICATIONS ■ ■ Data Networking CSU and DSU Data Routers , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ The LTC1344A is available in a 24-lead SSOP. TYPICAL APPLICATION DTE or DCE Multiprotocol Serial Interface with DB-25 Connector LL CTS DSR DCD DTR RTS RXD TXC RXC Daisy-Chained Control Outputs D3 R4 R3 R2 D2 TXD D2 D1 LTC1543 LTC1544 D4 SCTE D3 D1 R3 R1 R1 R2 LTC1344A 18 13 5 10 8 22 6 23 20 19 4 1 7 16 3 17 12 15 11 24 14 2 TXD A (103) TXD B SCTE A (113) TXC A (114) SCTE B TXC B RXC A (115) RXC B RXD A (104) RXD B SG (102) SHIELD (101) RTS A (105) RTS B DTR A (108) DCD A (107) DTR B DCD B DSR A (109) CTS A (106) DSR B CTS B LL A (141) DB-25 CONNECTOR 9 1344A TA01 1 LTC1344A U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) Positive Supply Voltage (VCC) ................................... 7V Negative Supply Voltage (VEE) ........................... – 13.2V Input Voltage (Logic Inputs) .................... (VEE – 0.3V) to (VCC + 0.3V) Input Voltage (Load Inputs) .................................. ±18V Power Dissipation .............................................. 600mW Operating Temperature Range LTC1344AC ............................................ 0°C to 70°C LTC1344AI ......................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C TOP VIEW M0 1 24 M1 VEE 2 23 M2 R1C 3 22 DCE/DTE R1B 4 21 LATCH R1A 5 20 R6B R2A 6 19 R6A R2B 7 18 R5A R2C 8 17 R5B R3A 9 16 R4A R3B 10 15 R4B R3C 11 14 VCC GND 12 13 GND ORDER PART NUMBER LTC1344ACG LTC1344AIG G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 100°C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 5V ±5%, VEE = – 5V ±5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Current All Digital Pins = GND or VCC ● 0.4 1.0 mA All Loads (Figure 1), – 2V ≤ VCM ≤ 2V (Commercial) All Loads (Figure 2), – 2V ≤ VCM ≤ 2V (Commercial) ● ● 90 135 104 153 110 165 Ω Ω All Loads (Figure 1), – 2V ≤ VCM ≤ 2V (Industrial) All Loads (Figure 2), – 2V ≤ VCM ≤ 2V (Industrial) ● ● 90 130 104 153 115 170 Ω Ω All Loads (Figure 1), VCM = 0V (Commercial) All Loads (Figure 1), – 7V ≤ VCM ≤ 7V (Commercial) ● 100 100 104 104 110 Ω Ω All Loads (Figure 1), VCM = 0V (Industrial) All Loads (Figure 1), – 7V ≤ VCM ≤ 7V (Industrial) ● 95 100 104 104 115 Ω Ω All Loads, – 7V ≤ VCM ≤ 7V ● ±1 ±50 µA Supplies ICC Terminator Pins RV.35 RV.11 ILEAK Differential Mode Impedance Common Mode Impedance Differential Mode Impedance High Impedance Leakage Current Logic Inputs VIH Input High Voltage All Logic Input Pins ● VIL Input Low Voltage All Logic Input Pins ● 0.8 V IIN Input Current All Logic Input Pins ● ±10 µA The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 2 2 V Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Note 3: All typicals are given at VCC = 5V, VEE = – 5V, TA = 25°C. LTC1344A U W TYPICAL PERFORMANCE CHARACTERISTICS V.11 or V.35 Differential Mode Impedance vs Supply Voltage (VCC) V.11 or V.35 Differential Mode Impedance vs Common Mode Voltage V.11 or V.35 Differential Mode Impedance vs Temperature 105 VCM = –2V 110 VCM = 0V 105 VCM = 7V 100 –40 –20 0 20 40 60 80 108 106 104 102 100 100 TA = 25°C –6 – 4 –2 0 2 4 6 COMMON MODE VOLTAGE (V) 1344 G01 104 4.6 8 V.35 Common Mode Impedance vs Common Mode Voltage 165 158 TA = 25°C 104 – 5.2 – 5.0 – 4.8 VEE VOLTAGE (V) 160 VCM = –2V 155 VCM = 0V 150 VCM = 2V 145 – 40 –20 103 – 4.6 COMMON MODE IMPEDANCE (Ω) COMMON MODE IMPEDANCE (Ω) TA = 25°C 60 40 20 TEMPERATURE (°C) 0 1344 G04 80 156 154 152 150 –2 100 0 –1 1 COMMON MODE VOLTAGE (V) 1344 G05 Supply Current vs Temperature 500 154 153 2 1344 G06 V.35 Common Mode Inpedance vs Negative Supply Voltage (VEE) V.35 Common Mode Impedance vs Supply Voltage (VCC) TA = 25°C 152 151 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4 1344 G07 153 SUPPLY CURRENT (µA) COMMON MODE IMPEDANCE (Ω) TA = 25°C 4.6 5.4 1344 G03 V.35 Common Mode Impedance vs Temperature 105 – 5.4 4.8 5.0 5.2 VCC VOLTAGE (V) 1344 G02 V.11 or V.35 Differential Mode Impedance vs Negative Supply Voltage (VEE) DIFFERENTIAL MODE IMPEDANCE (Ω) TA = 25°C 103 –8 TEMPERATURE (°C) COMMON MODE IMPEDANCE (Ω) DIFFERENTIAL MODE IMPEDANCE (Ω) VCM = –7V 115 DIFFERENTIAL MODE IMPEDANCE (Ω) DIFFERENTIAL MODE IMPEDANCE (Ω) 120 152 151 150 – 5.4 – 5.2 – 4.8 – 5.0 VEE VOLTAGE (V) – 4.6 1344 G08 420 340 260 180 –40 –20 0 40 60 20 TEMPERATURE (°C) 80 100 1344 G09 3 LTC1344A U U U PIN FUNCTIONS M0 (Pin 1): TTL Level Mode Select Input. The data on M0 is latched when LATCH is high. R4B (Pin 15): Load 4 Node B. VEE (Pin 2): Negative Supply Voltage Input. Can connect directly to the LTC1543 VEE pin. Connect a 1µF capacitor to ground. R5B (Pin 17): Load 5 Node B. R1C (Pin 3): Load 1 Center Tap. R6A (Pin 19): Load 6 Node A. R1B (Pin 4): Load 1 Node B. R6B (Pin 20): Load 6 Node B. R1A (Pin 5): Load 1 Node A. LATCH (Pin 21): TTL Level Logic Signal Latch Input. When LATCH is low the input buffers on M0, M1, M2 and DCE/ DTE are transparent. When LATCH is high the logic pins are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple I/O ports. R2A (Pin 6): Load 2 Node A. R2B (Pin 7): Load 2 Node B. R2C (Pin 8): Load 2 Center Tap. R3A (Pin 9): Load 3 Node A. R4A (Pin 16): Load 4 Node A. R5A (Pin 18): Load 5 Node A. DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE mode is selected when high and DTE mode when low. The data on DCE/DTE is latched when LATCH is high. R2B (Pin 10): Load 2 Node B. R3C (Pin 11): Load 3 Center Tap. GND (Pin 12): Ground Connection for Load 1 to Load 3. GND (Pin 13): Ground Connection for Load 4 to Load 6. VCC (Pin 14): Positive Supply Input. 4.75V ≤ VCC ≤ 5.25V. M2 (Pin 23): TTL Level Mode Select Input 1. The data on M2 is latched when LATCH is high. M1 (Pin 24): TTL Level Mode Select Input 2. The data on M1 is latched when LATCH is high. TEST CIRCUITS C C LTC1344A A LTC1344A R1 51.5Ω Ω S1 ON S2 OFF R1 51.5Ω S1 ON R3 124Ω S2 ON R3 124Ω A, B R2 51.5Ω R2 51.5Ω Ω B V ±7V OR ±2V 1344 F01 Figure 1. Differential V.11 or V.35 Impedance Measurement 4 V ±2V 1344 F02 Figure 2. V.35 Common Mode Impedance Measurement LTC1344A W U ODE SELECTIO LTC1344A MODE NAME DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6 V.10/RS423 X 0 0 0 Z Z Z Z Z Z RS530A 0 1 0 0 0 0 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 RS530 0 1 0 0 1 1 0 0 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 X.21 0 1 0 0 1 1 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 V.35 0 1 1 1 0 0 0 0 V.35 V.35 V.35 V.35 Z V.35 V.35 Z V.35 V.35 V.35 V.35 RS449/V.36 0 1 1 1 0 0 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 V.28/RS232 X 1 1 0 Z Z Z Z Z Z No Cable X 1 1 1 V.11 V.11 V.11 V.11 V.11 V.11 X = don’t care, 0 = logic low, 1 = logic high C A R1 51.5Ω S1 ON S2 OFF C LTC1344A A R1 51.5Ω S1 ON R3 124Ω R2 51.5Ω B S2 ON C LTC1344A R1 51.5Ω S1 OFF R3 124Ω R2 51.5Ω B V.11 Mode A S2 OFF LTC1344A R3 124Ω R2 51.5Ω B V.35 Mode High-Z Mode 1344 F03 Figure 3. LTC1344A Modes 5 LTC1344A U W U U APPLICATIONS INFORMATION Multiprotocol Cable Termination GENERATOR One of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. But the biggest problem still remains: how to switch the various cable termination required by the different standards. BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A A' C C' 1344 F04 Figure 4. Typical V.10 Interface A Traditional implementations have included switching resistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head. Another method uses separate termination built on the board, and a custom cable which routes the signals to the appropriate termination. Switching the termination using FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. 51.5Ω S1 OFF S2 OFF V.10 RECEIVER LTC1344A Z 124Ω Z 51.5Ω B C IZ 3.25mA –10V –3V Z The LTC1344A solves the cable termination switching problem via software control. The LTC1344A provides termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. RECEIVER 3V – 3.25mA VZ 10V 1344 F05 Figure 5. V.10 Interface Using the LTC1344A V.10 (RS423) Termination V.11 (RS422) Termination A typical V.10 unbalanced interface is shown in Figure 4. A V.10 single-ended generator output A with ground C is connected to a differential receiver with input A' connected to A and input C' connected to the signal return ground C. Usually no cable termination is required for V.10 interfaces but the receiver inputs must be compliant with the impedance curve shown in Figure 5. A typical V.11 balanced interface is shown in Figure 6. A V.11 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.11 interface requires a differential termination at the receiver end that has a minimum value of 100Ω. The receiver inputs must also be compliant with the impedance curve shown in Figure 7. In V.10 mode, both switches S1 and S2 are turned off so the only cable termination is the input impedance of the V.10 receiver. 6 In V.11 mode, switch S1 is turned on and S2 is turned off so the cable is terminated with a 103Ω impedance. LTC1344A U U W U APPLICATIONS INFORMATION BALANCED INTERCONNECTING CABLE GENERATOR LOAD GENERATOR BALANCED INTERCONNECTING CABLE CABLE TERMINATION RECEIVER A A' B B' C C' LOAD CABLE TERMINATION RECEIVER 100Ω MIN A A' C C' 1344 F08 1344 F06 Figure 8. Typical V.28 Interface Figure 6. Typical V.11 Interface A A 51.5Ω S1 ON S2 OFF V.11 RECEIVER LTC1344A 51.5Ω S1 OFF Z 124Ω S2 OFF V.28 RECEIVER LTC1344A 124Ω 5k Z 51.5Ω 51.5Ω B B C C IZ 3.25mA –10V 1344 F09 Figure 9. V.28 Interface Using the LTC1344A –3V Z 3V – 3.25mA VZ 10V 1344 F07 Figure 7. V.11 Interface Using the LTC1344A V.28 (RS232) Termination A typical V.28 unbalanced interface is shown in Figure 8. A V.28 single-ended generator output A with ground C is connected to a single-ended receiver with input A' connected to A, ground C' connected via the signal return ground to C. The V.28 standard requires a 5k terminating resistor to ground which is included in almost all compliant receivers as shown in Figure 9. Because the termination is included in the receiver, both switches S1 and S2 in the LTC1344A are turned off. V.35 Termination A typical V.35 balanced interface is shown in Figure 10. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.35 interface requires a T-network termination at the receiver end and the generator end. In V.35 mode both switches S1 and S2 in the LTC1344A are turned on as shown in Figure 11. The differential impedance measured at the connector must be 100Ω ±10Ω and the impedance between shorted terminals A' and B' to ground C' must be 150Ω ±15Ω. The input impedance of the V.35 receiver is connected in parallel with the T-network inside the LTC1344A, which could cause the overall impedance to fail the specification 7 LTC1344A U U W U APPLICATIONS INFORMATION A BALANCED INTERCONNECTING CABLE GENERATOR LOAD V.35 DRIVER CABLE TERMINATION RECEIVER A' A 50Ω 125Ω 125Ω 50Ω LTC1344A 51.5Ω 124Ω S2 ON S1 ON 51.5Ω B 50Ω B B' C C' 50Ω C1 100pF Figure 12. V.35 Driver Using the LTC1344A Figure 10. Typical V.35 Interface A 51.5Ω S1 ON S2 ON The generator differential impedance must be 50Ω to 150Ω and the impedance between shorted terminals A and B to ground C must be 150Ω ±15Ω. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure 12. V.35 RECEIVER LTC1344A Z 124Ω Z 51.5Ω B C IZ 1mA –7V –3V Z 3V –0.8mA VZ 12V 1344 F11 Figure 11. V.35 Receiver Using the LTC1344A if the receiver input impedance is on the low side. All of Linear Technology’s V.35 receivers meet the RS485 input impedance specification as shown in Figure 11, which insures compliance with the V.35 specification when used with the LTC1344A. 8 C 1344 F12 1344 F10 Any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the A and B terminals. The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable. The LATCH Pin The LATCH pin (21) allows the select lines (M0, M1, M2 and DCE/DTE) to be shared with multiple LTC1344As, each with its own LATCH signal. When the LATCH pin is held low the select line input buffers are transparent. When the LATCH pin is pulled high, the select line input buffers latch the state of the Select pins so that changes on the select lines are ignored until LATCH is pulled low again. If the latch feature is not used, the LATCH pin should be tied to ground. LTC1344A U TYPICAL APPLICATIONS N Controller Selectable Multiprotocol DTE/DCE Port with DB-25 Connector C6 C7 C8 100pF 100pF 100pF 3 8 11 12 13 LTC1344A VCC 5V 14 44 C5 1µF 41 LTC1343 D1 6 DTE_TXD/DCE_RXD D2 7 DTE_SCTE/DCE_RXC VEE C12 1µF 8 5 DTE_LL/DCE_TM 2 C4 3.3µF D3 5 4 6 7 9 10 M0 CHARGE PUMP 4 3 21 C2 1µF 43 42 M1 C1 1µF LATCH VCC M2 2 + C3 1µF C13 1µF DCE/DTE 1 16 15 18 17 19 20 22 23 24 1 39 18 38 2 37 14 36 24 35 11 DTE DCE LL A TM A TXD A RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A 34 9 DTE_TXC/DCE_TXC R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD R3 16 DTE_TM/DCE_LL 20 22 11 25 R1 100k 33 D4 10 12 13 R4 CTRL DCE LATCH M2 INVERT M1 423SET M0 GND EC C10 1µF VCC LB 1 VCC 2 VDD 3 VEE GND 4 D2 DTE_CTS/DCE_RTS DTE_RL/DCE_RL 6 R1 7 R2 8 R3 10 R4 9 11 12 13 14 DCE/DTE M2 M1 M0 17 29 9 28 3 27 16 26 25 21 7 19 1 18 TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B TM A LL A SG SHIELD 17 24 28 C11 1µF 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A D3 LTC1544 DTE_DSR/DCE_DTR 30 TXC B DB-25 CONNECTOR D1 5 DTE_DCD/DCE_DCD 12 23 C9, 1µF DTE_DTR/DCE_DSR 15 31 VCC 40 LB DTE_RTS/DCE_CTS 32 22 8 21 10 20 6 19 22 18 5 17 13 16 21 DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B RL A RL A D4 M0 INVERT 15 NC M1 M2 DCE/DTE 1344A TA04 9 LTC1344A U TYPICAL APPLICATIONS N Cable Selectable Multiprotocol DTE/DCE Port with DB-25 Connector C6 C7 C8 100pF 100pF 100pF 3 8 11 12 13 LTC1344A VCC 5V 14 4 D2 7 R1 9 DTE_RXC/DCE_SCTE R2 10 DTE_RXD/DCE_TXD 11 12 NC 13 14 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 VCC 2 23 14 22 24 21 11 DTE DCE TXD A RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B D3 8 DTE_TXC/DCE_TXC VEE 24 D1 6 C4 3.3µF C12 1µF LTC1543 5 DTE_SCTE/DCE_RXC 2 25 C5 1µF DTE_TXD/DCE_RXD C2 1µF 26 CHARGE PUMP 2 21 M0 27 M1 1 M2 28 LATCH VCC DCE/DTE C1 1µF 3 + C3 1µF C13 1µF R3 20 15 19 12 18 17 17 9 16 3 15 16 M0 7 M1 M2 1 DCE/DTE SG SHIELD DB-25 CONNECTOR VCC C9, 1µF 1 VCC 2 VDD C10 1µF VEE GND 25 DCE/DTE 21 M1 18 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B 28 C11 1µF 27 26 3 DTE_RTS/DCE_CTS D1 24 4 DTE_DTR/DCE_DSR D2 5 6 R1 7 DTE_DSR/DCE_DTR R2 8 DTE_CTS/DCE_RTS R3 10 R4 9 11 12 NC 13 14 23 22 8 21 10 CTS B DSR A DSR B 20 6 19 22 18 5 17 13 CABLE WIRING FOR MODE SELECTION MODE V.35 RS449, V.36 RS232 M0 M1 DCE/DTE INVERT DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B 16 D4 M2 DCD A 15 PIN 18 PIN 7 NC PIN 7 PIN 21 PIN 7 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC NC 1344A TA05 10 CTS A D3 LTC1544 DTE_DCD/DCE_DCD 25 LTC1344A U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 – 0.328* (8.07 – 8.33) 24 23 22 21 20 19 18 17 16 15 14 13 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.002 – 0.008 (0.05 – 0.21) G24 SSOP 0595 11 LTC1344A U TYPICAL APPLICATIO Figure 13 shows a typical application for the LTC1344A using the LTC1543 mixed mode transceiver chip to generate the clock and data signals for a serial interface. The LTC1344A VEE supply is generated from the LTC1543 charge pump and the select lines M0, M1, M2 and DCE/DTE are shared by both chips. Each driver output and receiver input is connected to one of the LTC1344A termination ports. Each electrical protocol can then be chosen using the digital select lines. 100pF 100pF 100pF 3 M0 M1 M2 DCE/DTE 1 8 11 12 9 10 13 M0 24 M1 23 M2 22 LTC1344A DCE/DTE 21 LATCH VCC VEE 14 C1 1µF 4 5 2 4 6 7 16 15 18 17 19 20 C2 3.3µF 26 LTC1543 11 M0 12 M1 13 M2 14 DCE/DTE 24 DTE TXD+ DCE RXD+ 23 TXD– RXD– SCTE + RXC+ 21 SCTE – RXC – 20 TXC + TXC + 19 18 TXC – RXC + TXC – SCTE+ RXC – RXD+ SCTE– TXD+ RXD– TXD– 5 22 6 7 8 9 17 16 10 15 1344 F13 Figure 13. Typical Application Using the LTC1344A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1334 Single Supply RS232/RS485 Transceiver 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs LTC1343 Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface LTC1345 Single Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1346A Dual Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1543 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Data and CLK Signals LTC1544 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Control Signals 12 Linear Technology Corporation 1344af, sn1344a LT/TP 0898 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1998
LTC1344AIG#PBF 价格&库存

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