LTC1418
Low Power, 14-Bit, 200ksps
ADC with Serial and Parallel I/O
FEATURES
DESCRIPTION
Single Supply 5V or ±5V Operation
nn Sample Rate: 200ksps
nn ±1.25LSB INL and ±1LSB DNL Max
nn Power Dissipation: 15mW (Typ)
nn Parallel or Serial Data Output
nn No Missing Codes Over Temperature
nn Power Shutdown: Nap and Sleep
nn External or Internal Reference
nn Differential High Impedance Analog Input
nn Input Range: 0V to 4.096V or ±2.048V
nn 81.5dB S/(N + D) and –94dB THD at Nyquist
nn 28-Lead SSOP Package
The LTC®1418 is a low power, 200ksps, 14-bit A/D converter. Data output is selectable for 14-bit parallel or serial
format. This versatile device can operate from a single 5V
or ±5V supply. An onboard high performance sample-andhold, a precision reference and internal timing minimize
external circuitry requirements. The low 15mW power
dissipation is made even more attractive with two user
selectable power shutdown modes.
nn
APPLICATIONS
The LTC1418 converts 0V to 4.096V unipolar inputs from
a single 5V supply and ±2.048V bipolar inputs from ±5V
supplies. DC specs include ±1.25LSB INL, ±1LSB DNL
and no missing codes over temperature. Outstanding AC
performance includes 82dB S/(N + D) and 94dB THD at
the Nyquist input frequency of 100kHz.
Remote Data Acquisition
nn Battery Operated Systems
nn Digital Signal Processing
nn Isolated Data Acquisition Systems
nn Audio and Telecom Processing
nn Medical Instrumentation
The flexible output format allows either parallel or serial
I/O. The SPI/MICROWIRE compatible serial I/O port can
operate as either master or slave and can support clock
frequencies from DC to 10MHz. A separate convert start
input and a data ready signal (BUSY) allow easy control
of conversion start and data transfer.
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Low Power, 200kHz, 14-Bit Sampling A/D Converter
Typical INL Curve
5V
1.0
10μF
VDD
SER/PAR
LTC1418
AIN–
REFCOMP
10μF
VREF
1μF
0.5
S/H
14-BIT ADC
14
4.096V
SELECTABLE
SERIAL/
PARALLEL
PORT
BUFFER
8k
TIMING AND
LOGIC
2.5V
REFERENCE
AGND
VSS
(0V OR – 5V)
DGND
D5
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (DOUT)
D0 (EXT/INT)
BUSY
CS
RD
CONVST
SHDN
INL (LSBs)
AIN+
D13
0
–0.5
–1.0
1418 TA01
0
4096
8192
12288
16384
OUTPUT CODE
1418 TA02
1418fa
For more information www.linear.com/LTC1418
1
LTC1418
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1, 2)
Supply Voltage (VDD) ..................................................6V
Negative Supply Voltage (VSS)
Bipolar Operation Only.............................. –6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only.......................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation.................... –0.3V to (VDD + 0.3V)
Bipolar Operation............(VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation.................................. –0.3V to 10V
Bipolar Operation..........................(VSS – 0.3V) to 10V
Digital Output Voltage
Unipolar Operation.................... –0.3V to (VDD + 0.3V)
Bipolar Operation............(VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation............................................... 500mW
Operation Temperature Range
LTC1418C.................................................. 0°C to 70°C
LTC1418I...............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
TOP VIEW
AIN+
AIN –
1
28 VDD
2
27 VSS
VREF
3
26 BUSY
REFCOMP
4
25 CS
AGND
5
24 CONVST
D13 (MSB)
6
23 RD
D12
7
22 SHDN
D11
8
21 SER/PAR
D10
9
20 D0 (EXT/INT)
D9 10
19 D1 (DOUT)
D8 11
18 D2 (CLKOUT)
D7 12
17 D3 (SCLK)
D6 13
16 D4 (EXTCLKIN)
DGND 14
G PACKAGE
28-LEAD PLASTIC SSOP
15 D5
OBSOLETE PACKAGE
N PACKAGE
28-LEAD NARROW PDIP
TJMAX = 110°C, θJA = 95°C/W (G)
TJMAX = 110°C, θJA = 100°C/W (N)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1418ACG#PBF
LTC1418ACG#TRPBF
1418ACG
28-Lead Plastic SSOP
0°C to 70°C
LTC1418CG#PBF
LTC1418CG#TRPBF
1418CG
28-Lead Plastic SSOP
0°C to 70°C
LTC1418AIG#PBF
LTC1418AIG#TRPBF
1418AIG
28-Lead Plastic SSOP
–40°C to 85°C
LTC1418IG#PBF
LTC1418IG#TRPBF
1418IG
28-Lead Plastic SSOP
–40°C to 85°C
LTC1418ACN#PBF
LTC1418ACN#TRPBF
1418ACN
28-Lead PDIP
0°C to 70°C
LTC1418CN#PBF
LTC1418CN#TRPBF
1418CN
28-Lead PDIP
0°C to 70°C
LTC1418AIN#PBF
LTC1418AIN#TRPBF
1418AIN
28-Lead PDIP
–40°C to 85°C
LTC1418IN#PBF
LTC1418IN#TRPBF
1418IN
28-Lead PDIP
–40°C to 85°C
OBSOLETE PACKAGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
1418fa
For more information www.linear.com/LTC1418
LTC1418
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6)
LTC1418
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
Integral Linearity Error
l
(Note 7)
Differential Linearity Error
Offset Error
(Note 8)
Full-Scale Error
Internal Reference
External Reference = 2.5V
Full-Scale Tempco
IOUT(REF) = 0, Internal Reference, Commercial
IOUT(REF) = 0, Internal Reference, Industrial
IOUT(REF) = 0, External Reference
LTC1418A
TYP
MAX
13
MIN
TYP
MAX
UNITS
14
Bits
l
±0.8
±2
±0.5
±1.25
LSB
l
±0.7
±1.5
±0.35
±1
LSB
l
±5
±20
±2
±10
LSB
±10
±5
±60
±30
±20
±5
±60
±15
LSB
LSB
±10
±20
±1
±45
ppm/°C
ppm/°C
ppm/°C
±15
l
±5
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
VIN
Analog Input Range (Note 9)
l
4.75V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, –5.25V ≤ VSS ≤ –4.75V (Bipolar) l
IIN
Analog Input Leakage Current
CS = High
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold Acquisition Time
Commercial
Industrial
TYP
MAX
0 to 4.096
±2.048
V
V
±1
l
25
5
300
300
l
l
UNITS
µA
pF
pF
1000
1000
ns
ns
DYNAMIC
ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
97.5kHz Input Signal
l
THD
Total Harmonic Distortion
100kHz Input Signal, First 5 Harmonics
l
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
l
IMD
Intermodulation Distortion
fIN1 = 97.7kHz, fIN2 = 104.2kHz
Full Power Bandwidth
Full Linear Bandwidth
S/(N + D) ≥ 77dB
MIN
TYP
79
81.5
–94
86
95
–90
MAX
UNITS
dB
–86
dB
dB
dB
5
MHz
0.5
MHz
1418fa
For more information www.linear.com/LTC1418
3
LTC1418
INTERNAL
REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0, Commercial
IOUT = 0, Industrial
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
–5.25V ≤ VSS ≤ –4.75V
VREF Output Resistance
0.1mA ≤ | IOUT | ≤ 0.1mA
MIN
TYP
MAX
2.480
2.500
2.520
±10
±20
±45
l
0.05
0.05
UNITS
V
ppm/°C
ppm/°C
LSB/V
LSB/V
8
kΩ
DIGITAL
INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
l
VIL
Low Level Input Voltage
VDD = 4.75V
l
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDD = 4.75V, IO = –10μA
VDD = 4.75V, IO = –200µA
VDD = 4.75V, IO = 160μA
VDD = 4.75V, IO = 1.6mA
MIN
l
Hi-Z Output Leakage D13 to D0
VOUT = 0V to VDD, CS High
l
l
MAX
UNITS
2.4
4.0
V
1.4
pF
4.74
V
V
0.05
0.10
l
IOZ
TYP
0.4
V
V
±10
µA
COZ
Hi-Z Output Capacitance D13 to D0
CS High (Note 9)
ISOURCE
Output Source Current
VOUT = 0V
–10
15
mA
pF
ISINK
Output Sink Current
VOUT = VDD
10
mA
POWER
REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage (Notes 10, 11)
VSS
IDD
4.75
5.25
V
Negative Supply Voltage (Note 10)
Bipolar Only (VSS = 0V for Unipolar)
–4.75
–5.25
V
Positive Supply Current
l
l
Nap Mode
Sleep Mode
Unipolar, RD High (Note 5 )
Bipolar, RD High (Note 5)
SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)
3.0
3.9
570
2
4.3
4.5
mA
µA
µA
Bipolar, RD High (Note 5)
SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)
l
Nap Mode
Sleep Mode
1.4
0.1
0.1
1.8
mA
µA
µA
Unipolar
Bipolar
l
l
15.0
26.5
21.5
31.5
mW
mW
ISS
Negative Supply Current
PDIS
Power Dissipation
4
TYP
MAX
UNITS
1418fa
For more information www.linear.com/LTC1418
LTC1418
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX)
tCONV
tACQ
tACQ + tCONV
t1
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition Plus Conversion Time
CS to RD Setup Time
CONDITIONS
t2
t3
t4
t5
t6
t7
CS↓ to CONVST↓ Setup Time
CS↓ to SHDN↓ Setup Time to Ensure Nap Mode
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY↑
MIN
l
l
l
l
(Notes 9, 10)
l
0
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
(Notes 10, 11)
CL = 25pF
l
l
40
40
l
40
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 10)
MAX
3.4
0.3
3.7
4
1
5
500
l
l
t8
t9
t10
TYP
200
l
l
20
15
500
–5
CL = 25pF
35
35
70
15
30
40
40
55
20
25
30
l
CL = 100pF
20
l
t11
Bus Relinquish Time
8
Commercial
Industrial
t12
t13
t14
t15
fSCLK
fEXTCLKIN
tdEXTCLKIN
tH SCLK
tL SCLK
tH EXTCLKIN
tL EXTCLKIN
RD Low Time
CONVST High Time
Delay Time, SCLK↓ to DOUT Valid
Time from Previous Data Remain Valid After SCLK↓
Shift Clock Frequency
External Conversion Clock Frequency
Delay Time, CONVST↓ to External Conversion Clock Input
SCLK High Time
SCLK Low Time
EXTCLKIN High Time
EXTCLKIN Low Time
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VCC without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = 0V or –5V, fSAMPLE = 200kHz, tr = tf = 5ns unless
otherwise specified.
l
l
l
CL = 25pF (Note 9)
CL = 25pF (Note 9)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
t10
40
l
l
15
0
0.03
35
25
70
12.5
4.5
533
10
20
250
250
UNITS
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
µs
ns
ns
ns
ns
Note 6: Linearity, offset and full-scale specifications apply for a singleended input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1µs after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
1418fa
For more information www.linear.com/LTC1418
5
LTC1418
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity
vs Output Code
Typical INL Curve
1.0
SIGNAL/(NOISE + DISTORTION) (dB)
0.5
DNL ERROR (LSBs)
0
–0.5
0
– 0.5
0
4096
8192
12288
–1.0
16384
0
4096
OUTPUT CODE
12288
8192
OUTPUT CODE
Signal-to-Noise Ratio
vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
SIGNAL-TO -NOISE RATIO (dB)
80
70
60
50
40
30
20
10
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
–60
3RD
–80
THD
–100
–120
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
–40
–60
–80
1418 G07
100k
INPUT FREQUENCY (Hz)
–60
–80
1M
1418 G06
Intermodulation Distortion Plot
fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz
– 20
–40
–120
1M
–20
–120
10k
fSAMPLE = 200kHz
fIN = 97.509765kHz
SFDR = 94.29
SINAD = 81.4
– 40
– 60
– 80
–100
–100
–100
100k
10k
INPUT FREQUENCY (Hz)
–100
AMPLITUDE (dB)
–80
1k
0
–20
AMPLITUDE (dB)
AMPLITUDE (dB)
10
1418 G05
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
–60
VIN = –60dB
20
Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
–40
6
2ND
0
10 20
30
0
–40
0
0
40
Spurious-Free Dynamic Range
vs Input Frequency
–20
Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
–120
50
1418 G03
0
1418 G04
–20
VIN = –20dB
60
Distortion vs Input Frequency
90
VIN = 0dB
70
1418 G02
1418 G01
0
80
0
16384
SPURIOUS-FREE DYNAMIC RANGE (dB)
INL (LSBs)
90
1.0
0.5
–1.0
S/(N + D) vs Input Frequency
and Amplitude
0
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 G08
–120
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 G09
1418fa
For more information www.linear.com/LTC1418
LTC1418
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
COMMON MODE REJECTION (dB)
DISTORTION (dB)
–20
–40
–60
VSS
–80
VDD
DGND
–100
–120
1k
10k
100k
1M
FREQUENCY (Hz)
90
10
80
9
CHANGE IN OFFSET VOLTAGE (LSB)
0
Input Offset Voltage Shift
vs Source Resistance
70
60
50
40
30
20
10
0
10M
1
10
100
1k
10k 100k
INPUT FREQUENCY (Hz)
8
7
6
5
4
3
2
1
0
1M
10
100
100k
1k
10k
INPUT SOURCE RESISTANCE (Ω)
1M
1418 G12
1418 G11
1418 G10
VDD Supply Current vs
Temperature (Unipolar Mode)
VDD Supply Current vs
Temperature (Bipolar Mode)
5
5
4
4
VSS Supply Current vs
Temperature (Bipolar Mode)
2.0
3
2
1
VSS SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
1.8
3
2
1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
–75 –50 –25
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1418 G14
1418 G13
VDD Supply Current vs Sampling
Frequency (Unipolar Mode)
1418 G13
VDD Supply Current vs Sampling
Frequency (Bipolar Mode)
5
5
4
4
0 25 50 75 100 125 150
TEMPERATURE (°C)
VSS Supply Current vs Sampling
Frequency (Bipolar Mode)
2.0
3
2
1
VSS SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
1.8
3
2
1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
100
150
200
250
50
SAMPLING FREQUENCY (kHz)
300
1418 G16
0
0
50
150
200
250
100
SAMPLING FREQUENCY (kHz)
300
1418 G17
0
0
50
150
200
250
100
SAMPLING FREQUENCY (kHz)
300
1418 G18
1418fa
For more information www.linear.com/LTC1418
7
LTC1418
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN– (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin. Bypass
to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs (Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output (Parallel). Conversion clock input (serial) when Pin 20 (EXT/
INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables
the internal conversion clock. An input high indicates
an external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also
sets the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
VSS (Pin 27): Negative Supply, –5V for Bipolar Operation.
Bypass to AGND with 10µF tantalum in parallel with 0.1µF
ceramic. Analog ground for unipolar operation.
VDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Timing
5V
5V
1k
1k
DBN
DBN
DBN
1k
CL
DGND
A) HI-Z TO VOH AND VOL TO VOH
DBN
1k
CL
30pF
DGND
B) HI-Z TO VOL AND VOH TO VOL
A) VOH TO HI-Z
1418 TC01
8
30pF
B) VOL TO HI-Z
1418 TC02
1418fa
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LTC1418
BLOCK DIAGRAM
CSAMPLE
AIN+
VDD: 5V
CSAMPLE
AIN–
VREF
2.5V
8k
VSS: 0V FOR UNIPOLAR MODE
– 5V FOR BIPOLAR MODE
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
14-BIT CAPACITIVE DAC
–
REFCOMP
4.096V
AGND
DGND
14
SUCCESSIVE APPROXIMATION
REGISTER
INTERNAL
CLOCK
SHIFT
REGISTER
D13
•
•
•
D0
D3/(SCLK)
MUX
CONTROL LOGIC
D1/(DOUT)
1418 BD
D4 (EXTCLKIN)
D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY
NOTE: PIN NAMES IN PARENTHESES
REFER TO SERIAL MODE
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel or serial output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section
for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
AIN+
AIN–
CSAMPLE+
SAMPLE
ZEROING SWITCHES
HOLD
CSAMPLE–
SAMPLE
HOLD
HOLD
HOLD
CDAC+
+
CDAC–
VDAC+
COMP
–
VDAC–
SAR
14
OUTPUT
LATCH
D13
D0
1418 F01
Figure 1. Simplified Block Diagram
1418fa
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9
LTC1418
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
The LTC1418 has excellent high speed sampling capability.
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 2a shows
a typical LTC1418 FFT plot.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2b shows a typical spectral content with
a 200kHz sampling rate and a 10kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 100kHz.
10
0
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4
AMPLITUDE (dB)
–20
–40
–60
–80
–100
–120
0
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a
Figure 2a. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 10kHz
0
fSAMPLE = 200kHz
fIN = 97.509765kHz
SFDR = 94.29
SINAD = 81.4
–20
AMPLITUDE (dB)
Referring to Figure 1, the AIN+ and AIN– inputs are connected
to the sample-and-hold capacitors (CSAMPLE) during the
acquire phase and the comparator offset is nulled by the
zeroing switches. In this acquire phase, a minimum delay
of 1µs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal. During the convert
phase, the comparator zeroing switches open, putting the
comparator into compare mode. The input switches the
CSAMPLE capacitors to ground, transferring the differential
analog input charge onto the summing junction. This input
charge is successively compared with the binary weighted
charges supplied by the differential capacitive DAC. Bit
decisions are made by the high speed comparator. At the
end of a conversion, the differential DAC output balances
the AIN+ and AIN– input charges. The SAR contents (a
14‑bit data word) which represent the difference of AIN+
and AIN– are loaded into the 14-bit output latches.
–40
–60
–80
–100
–120
0
10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b
Figure 2b. LTC1418 Nonaveraged, 4096 Point FFT,
Input Frequency = 97.5kHz
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement
of the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution
and S/(N + D) is expressed in dB. At the maximum
sampling rate of 200kHz, the LTC1418 maintains near
ideal ENOBs up to the Nyquist input frequency of 100kHz
(refer to Figure 3).
1418fa
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LTC1418
APPLICATIONS INFORMATION
14
Intermodulation Distortion
13
12
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
EFECTIVE BITS
11
10
9
8
7
6
5
4
3
2
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1418 F03
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD ( fa + fb) = 20Log
0
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz
– 20
AMPLITUDE (dB)
V22 + V32 + V42 +...VN 2
THD = 20Log
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through nth harmonics. THD vs Input Frequency
is shown in Figure 4. The LTC1418 has good distortion
performance up to the Nyquist frequency and beyond.
Amplitude at ( fa + fb)
Amplitude at fa
– 40
– 60
– 80
–100
–120
0
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F05
–20
Figure 5. Intermodulation Distortion Plot
–40
Peak Harmonic or Spurious Noise
–60
THD
–100
–120
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
3RD
–80
1k
10k
100k
INPUT FREQUENCY (Hz)
2ND
1M
1418 F04
Figure 4. Distortion vs Input Frequency
1418fa
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11
LTC1418
APPLICATIONS INFORMATION
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at
which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1418 has been designed to optimize
input bandwidth, allowing the ADC to undersample
input signals with frequencies above the converter’s
Nyquist Frequency. The noise floor stays very low at
high frequencies; S/(N + D) becomes dominated by
distortion at frequencies far beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1418 are easy
to drive. The inputs may be driven differentially or as a
single-ended input (i.e., the AIN– input is grounded). The
AIN+ and AIN– inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at the
end of conversion. During conversion, the analog inputs
draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1418 inputs
can be driven directly. As source impedance increases so
will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier
must be used. The only requirement is that the amplifier
driving the analog input(s) must settle after the small
current spike before the next conversion starts—1µs for
full throughput rate.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (
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