LTC1421CSW-2.5#PBF

LTC1421/LTC1421-2.5 Hot Swap Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1421/LTC1421-2.5 are Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a programmable rate. Two high side switch drivers control the Nchannel gates for supply voltages ranging from 3V to 12V. Allows Safe Board Insertion and Removal from a Live Backplane System Reset and Power Good Control Outputs Programmable Electronic Circuit Breaker User Programmable Supply Voltage Power-Up Rate High Side Driver for Two External N-Channels Controls Supply Voltages from 3V to 12V Connection Inputs Detect Board Insertion or Removal Undervoltage Lockout Power-On Reset Input A programmable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with staggered connector pins to indicate board insertion or removal. The power-on reset input can be used to cycle the board power or clear the circuit breaker. U APPLICATIO S ■ ■ Hot Board Insertion Electronic Circuit Breaker The trip point of the ground sense comparator is set at 0.1V for LTC1421 and 2.5V for LTC1421-2.5. The LTC1421/LTC1421-2.5 are available in 24-pin SO and SSOP packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Q3 1/2 Si4936DY C3 0.47µF VEE R4 20k 5% Q2 R2 1 0.025Ω 2 1/2 Si4936DY VDD 3 R1 Q1 1 0.005Ω 2 MTB50N06E STAGGERED CONNECTOR VCC 3 23 D1 VCCLO R3 1k LTC1421 GND 12 GND DATA BUS 19 FAULT 3 POR 1 CON1 POR 20 DISABLE 5 1 BEA VCC 13 BEB 12 GND QS3384 QuickSwitch® BACKPLANE 18 VDD 12V 1A + CLOAD 10k 21 CLOAD + 4 SETLO GATELO VOUTLO VCCHI 2 CON2 24 AUXVCC C1 1µF 4 FAULT 4 22 VEE – 12V 1A 17 C2 0.1µF 16 SETHI GATEHI VOUTHI RAMP CPON COMP – COMP + REF FB COMPOUT PWRGD RESET 10 9 14 13 8 11 15 6 7 R5 16k 5% 1µF R6 20k 1% + CLOAD VCC 5V 5A R7 7.15k 1% µP I/O I/O RESET DATA BUS 1421 TA01 QuickSwitch IS A REGISTERED TRADEMARK OF QUALITY SEMICONDUCTOR CORPORATION. PC BOARD 1 LTC1421/LTC1421-2.5 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCCLO, VCCHI, AUXVCC) .............. 13.2V Input Voltage (Analog Pins) ..... – 0.3V to (VCCHI + 0.3V) Input Voltage (Digital Pins) ................... – 0.3V to 13.2V Output Voltage (Digital Pins) .. – 0.3V to (VCCLO + 0.3V) Output Voltage (CPON) ......... – 13.2V to (VCCLO + 0.3V) Output Voltage (VOUTLO, VOUTHI) ........... – 0.3V to 13.2V Output Voltage (GATELO, GATEHI) ........... – 0.3V to 20V Operating Temperature Range LTC1421C ............................................... 0°C to 70°C LTC1421I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW CON1 1 24 AUXVCC CON2 2 23 VCCLO POR 3 22 SETLO FAULT 4 21 GATELO DISABLE 5 20 VOUTLO PWRGD 6 19 VCCHI RESET 7 18 SETHI REF 8 17 GATEHI CPON 9 16 VOUTHI RAMP 10 15 COMPOUT FB 11 14 COMP – GND 12 13 COMP + LTC1421CG LTC1421CSW LTC1421CG-2.5 LTC1421CSW-2.5 LTC1421IG LTC1421ISW LTC1421IG-2.5 LTC1421ISW-2.5 G PACKAGE SW PACKAGE 24-LEAD PLASTIC SSOP 24-LEAD PLASTIC SO TJMAX = 125°C, θJA = 100°C/W (G) TJMAX = 125°C, θJA = 85°C/W (SW) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.5 3 mA mA DC Characteristics ICCLO VCCLO Supply Current CON1 = CON2 = GND, POR = VCCLO ● ICCHI VCCHI Supply Current CON1 = CON2 = GND, POR = VCCLO ● VLKO Undervoltage Lockout VLKH Undervoltage Lockout Hysteresis VCCLO and VCCHI VCCLO and VCCHI VREF Reference Output Voltage No Load ● ∆VLNR Reference Line Regulation 3V ≤ VCCLO ≤ 12V, No Load ● ∆VLDR Reference Load Regulation IO = 0mA to – 5mA, Sourcing Only ● IRSC Reference Short-Circuit Current VREF = 0V VCOF Comparator Offset Voltage 0V ≤ VCM ≤ (VCCLO − 1.3V) ● VCPSR Comparator Power Supply Rejection 0V ≤ VCM ≤ (VCCLO − 1.3V), 3V ≤ VCCLO ≤ 12V ● VCHST Comparator Hysteresis 0V ≤ VCM ≤ (VCCLO − 1.3V) VRST Reset Voltage Threshold (VOUTLO) FB = VOUTLO FB = Floating FB = GND VRHST Reset Threshold Hysteresis (VOUTLO) FB = VOUTLO FB = Floating FB = GND 7 12 15 mV mV mV RFB FB Pin Input Resistance 0V ≤ VFB ≤ VCCLO 95 kΩ VCB Circuit Breaker Trip Voltage VCB = (VCCLO – VSETLO) or VCB = (VCCHI – VSETHI) VTRIP Output Voltage for Re-Power-Up LTC1421 (Note 3) LTC1421-2.5 (Note 4) 2 0.6 1 2.28 2.45 2.60 1.220 1.232 1.244 4 8 mV 1 3 mV 100 mV – 45 ±10 1 ● 2.80 4.50 5.75 40 2.90 4.65 5.88 50 0.1 2.5 V mA 7 ● ● ● V mV mV/V mV 3.00 4.75 6.01 60 V V V mV V V LTC1421/LTC1421-2.5 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN IRAMP RAMP Pin Output Current Charge Pump On, VRAMP = 0.4V ICP Charge Pump Output Current Charge Pump On, GATEHI = 0V GATELO = 0V ∆VGATEHI GATEHI N-Channel Gate Drive ● 11 TYP MAX 17 23 UNITS µA µA µA – 600 – 300 VGATEHI − VOUTHI 6 16 V ∆VGATELO GATELO N-Channel Gate Drive VGATELO − VOUTLO 10 16 V VAUXVCC Auxiliary VCC Output Voltage VCCLO = 5V, Unloaded VIL Input Low Voltage CON1, CON2, POR ● VIH Input High Voltage CON1, CON2, POR ● 2 IIN Input Current CON1, CON2, POR = GND ● – 30 VOL Output Low Voltage RESET, COMPOUT, PWRGD, DISABLE, FAULT, IO = 3mA VOH IPU Output High Voltage Logic Output Pull-Up Current 4.5 V 0.8 V V – 90 µA ● 0.4 V CPON, IO = 3mA ● 1.45 V DISABLE, IO = – 3mA ● 4 V CPON, IO = – 1mA ● 3.4 V RESET, PWRGD, FAULT = GND – 60 µA – 15 AC CHARACTERISTICS t1 CON1 or CON2↓ to CPON↑ Figure 1, CL = 15pF t2 PWRGD↑ to RESET↑ Figure 1, RL = 10k to VCCLO, CL = 15pF t3 PWRGD↑ to DISABLE↓ ● 15 20 30 ms ● 160 140 200 200 240 280 ms ms ● 160 140 200 200 240 280 ms ms ● 15 20 30 ms Figure 1, CL = 15pF t4 POR↓ to CPON↓ Figure 1, CL = 15pF t5 PWRGD↓ to RESET↓ Figure 1, RL = 10k to VCCLO, CL = 15pF 32 µs t6 POR↑ to CPON↑ Figure 1, CL = 15pF 50 ns t7 CON1 or CON2↑ to CPON↓ Figure 1, CL = 15pF 50 ns t9 Short-Circuit Detect to FAULT↓ Figure 1, RL = 10k to VCCLO, CL = 15pF VCCLO – SETLO = 0mV to 100mV 20 µs t10 Short-Circuit Detect to CPON↓ Figure 2, CL = 15pF VCCLO – SETLO = 0mV to 100mV 20 µs t11 POR↑ to FAULT↑ Figure 2, RL = 10k to VCCLO, CL = 15pF 20 ns tCHL Comparator High to Low COMP – = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF ● 0.25 0.5 µs tCLH Comparator Low to High COMP – = 1.232V, 10mV Overdrive RL = 10k to VCCLO, CL = 15pF ● 1 1.5 µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. Note 3: After power-on reset, the VOUTLO and VOUTHI have to drop below the VTRIP point before the charge pump is restarted. Note 4: After power-on reset, the VOUTLO has to drop below the VTRIP point before the charge pump is restarted. 3 LTC1421/LTC1421-2.5 U W TYPICAL PERFORMANCE CHARACTERISTICS Reference Voltage vs Temperature 1.238 1.245 24 VCCLO = 5V VCCHI = 12V 23 GATE VOLTAGE (V) 1.234 1.232 1.230 1.228 VCCLO = 5V VCCHI = 12V REFERENCE VOLTAGE (V) VCCLO = 5V VCCHI = 12V 1.236 REFERENCE VOLTAGE (V) Reference Voltage vs Source Current Gate Voltage vs Temperature 22 GATEHI 21 20 19 GATELO 1.226 50 25 75 0 TEMPERATURE (°C) 100 17 – 50 – 25 125 1.220 50 25 75 0 TEMPERATURE (°C) 100 26 26 VCCHI = 12V VCCLO = 5V 18 16 10 14 VCCLO = 5V VCCHI = 12V 1500 ICCLO SUPPLY CURRENT (µA) GATEHI VOLTAGE (V) 20 6 8 4 SOURCE CURRENT (mA) ICCLO Supply Current vs Temperature 24 22 2 0 1421 G03 GATEHI Voltage vs VCCHI Voltage 24 GATELO VOLTAGE (V) 125 1421 G02 GATELO Voltage vs VCCLO Voltage 22 20 18 16 1400 1300 14 12 12 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14 0 8 6 10 4 VCCHI VOLTAGE (V) 2 12 1421 G04 14 600 VOLTAGE (mV) 545 535 VCCLO = 5V VCCHI = 12V 2.0 COMPOUT PWRGD RESET 400 300 FAULT 200 530 0 50 25 75 0 TEMPERATURE (°C) 100 125 1421 G07 1.5 1.0 0.5 100 525 125 2.5 VCCLO = 5V VCCHI = 12V 500 100 CPON Voltage vs Sink Current (Charge Pump Off) CPON VOLTAGE (V) VCCLO = 5V VCCHI = 12V 540 50 25 75 0 TEMPERATURE (°C) 1421 G06 VOL vs ISINK 555 520 – 50 – 25 1200 – 50 – 25 1421 G05 ICCHI Supply Current vs Temperature ICCHI SUPPLY CURRENT (µA) 1.230 1.225 1421 G01 4 1.235 18 1.224 – 50 – 25 550 1.240 0 2 4 6 SINK CURRENT (mA) 8 10 1421 G08 0 0 0.5 1.0 1.5 2.0 SINK CURRENT (mA) 2.5 3.0 1421 G09 LTC1421/LTC1421-2.5 U W TYPICAL PERFORMANCE CHARACTERISTICS ICCLO Supply Current vs VCCLO Voltage CPON Voltage vs Source Current (Charge Pump On) 5 7 VCCLO = 5V VCCHI = 12V ICCLO SUPPLY CURRENT (mA) CPON VOLTAGE (V) 4 3 2 1 0 VCCHI = 12V 6 5 4 3 2 1 0 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 SOURCE CURRENT (mA) – 3.0 1421 G10 0 0 2 8 6 10 4 VCCLO VOLTAGE (V) 12 14 1421 G11 U U U PIN FUNCTIONS CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO. Together with CON2, it is used to indicate board connection. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON1 and CON2 must be the shortest and must be placed at opposite corners of the connector. Board insertion is assumed after CON1 and CON2 are both held low for 20ms after power-up. CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO. Together with CON1 it is used to indicate board connection. POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO. When the pin is pulled low for at least 20ms, a hard reset is generated. Both VOUTLO and VOUTHI will turn off at a controlled rate. A power-up sequence will not start until the POR pin is pulled high. If POR is pulled high before VOUTLO and VOUTHI are fully discharged, a power-up sequence will not begin until the voltage at VOUTLO and VOUTHI are below VTRIP. The electronic circuit breaker will be reset by pulling POR low. FAULT (Pin 4): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when an overcurrent fault is detected at VOUTLO or VOUTHI. DISABLE (Pin 5): CMOS Output. The signal is used to disable the board’s data bus during insertion or removal. PWRGD (Pin 6): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low immediately after VOUTLO falls below its reset threshold voltage. The pin is pulled high immediately after VOUTLO rises above its reset threshold voltage. RESET (Pin 7): Open Drain Output to GND with a Weak Pull-Up to VCCLO. The pin is pulled low when a reset condition is detected. A reset will be generated when any of the following conditions are met: Either CON1 or CON2 is high, POR is pulled low, VCCLO or VCCHI are below their respective undervoltage lockout thresholds, PWRGD goes low or an overcurrent fault is detected at VOUTLO or VOUTHI. RESET will go high 200ms after PWRGD goes high. On power failure, RESET will go low 32µs after PWRGD goes low. REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V ±1%. The reference can source up to 5mA of current. A 1µF bypass capacitor is recommended. CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a – 5V to – 12V supply. 5 LTC1421/LTC1421-2.5 U U U PIN FUNCTIONS RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to 20µA/CRAMP. A 10k resistor in series with the capacitor enhances the ESD performance at the GATEHI pin. FB (Pin 11): Analog Feedback Input. FB is used to set the reset threshold voltage on VCCLO. For a 5V supply leave FB floating. For a 3.3V supply, short FB to VCCLO. GND (Pin 12): Ground COMP + (Pin 13): Noninverting Comparator Input. COMP – (Pin 14): Inverting Comparator Input. COMPOUT (Pin 15): Open Drain Comparator Output. VOUTHI (Pin 16): High Supply Voltage Output. This must be the higher of the two supply voltage outputs. GATEHI (Pin 17): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least 6V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips, GATEHI is immediately pulled to GND. SETHI (Pin 18): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path between VCCHI and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20µs. To disable the circuit breaker, VCCHI and SETHI should be shorted together. 6 VCCHI (Pin 19): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage lockout circuit disables the chip until the voltage at VCCHI is greater than 2.45V. VOUTLO (Pin 20): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs. GATELO (Pin 21): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 10V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND. SETLO (Pin 22): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path between VCCLO and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more than 20µs. To disable the circuit breaker, VCCLO and SETLO should be shorted together. VCCLO (Pin 23): The Positive Supply Input. VCCLO must be equal to or lower voltage than VCCHI. An undervoltage lockout circuit disables the chip until the voltage at VCCLO is greater than 2.45V. AUXVCC (Pin 24): The supply input for the GATELO and GATEHI discharge circuitry. Connect a 1µF capacitor to ground. AUXVCC is powered from VCCLO via an internal Schottky diode and series resistor. LTC1421/LTC1421-2.5 W BLOCK DIAGRAM VCC 24 23 22 19 18 21 10 17 16 20 VCCLO SETLO VCCHI SETHI GATELO RAMP GATEHI VOUTHI VOUTLO AUXVCC 50mV + – 50mV AUXVCC + – CHARGE PUMP N2 CP1 N1 CP3 CP2 + + – VCC UNDERVOLTAGE LOCKOUT 73.5k + – VTRIP CP4 71.5k – 9 CPON FB 11 REF 8 PWRGD 6 RESET 7 26.7k + 1.232V REFERENCE VCC VCC 20µA 4 20µA FAULT VCC DIGITAL CONTROL 1 CON1 2 CON2 20µA 3 RESET TIMING POR + 5 12 DISABLE CP5 COMPOUT 15 COMP – 14 COMP + 13 – GND 1421 BD U W W SWITCHI G TI E WAVEFOR S t1 t2 t5 t9 t7 CON1 VCCLO – SETLO CON2 FAULT CPON CPON PWRGD PWRGD RESET RESET DISABLE POR POR 1421 F01 t3 t4 t5 t11 t2 1421 F02 t10 t6 t6 Figure 1. Nominal Operation Switching Waveforms Figure 2. Fault Detection Switching 7 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION Hot Circuit Insertion 12V When circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the board’s data pins make or break connection. The LTC1421 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides a disable signal for the board’s data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board. Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure 3). R1 and R2 provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I = C • dV/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection. 1 12V R2 2 Q2 VOUTHI + 4 3 CLOAD 5V 1 VCCLO 2 Q1 RRAMP 4 3 23 1 R1 2 CON1 22 21 20 19 SETLO GATELO VOUTLO VCCHI LTC1421 18 17 + SLOPE = 20µA/CRAMP VOUTLO 5V t1 t2 SETHI GATEHI VOUTHI RAMP and GATEHI pins. The voltage at the GATEHI pin is clamped one Schottky diode drop below GATELO. The ramp time for each supply is equal to: t = (VCC) (CRAMP)/20µA. During power down the gates are actively pulled down by two internal NFETs. A negative supply voltage can be controlled using the CPON pin as shown in Figure 5. When the board makes connection, the transistor Q3 is turned off because it’s gate is pulled low to –12V by R4. CPON is also pulled to –12V. When the charge pump is turned on, CPON is pulled to VCCLO and the gate of Q3 will ramp up with a time constant determined by R4, R5 and C2. When the charge pump is turned off, CPON goes into a high impedance state, the gate of Q3 is discharged to VEE with a time constant determined by R4 and C2, and Q3 turns off. –12V FROM CONNECTOR CRAMP 10 Q3 1/2 MMDF3N0HD C2 0.047µF CON2 1421 F03 Figure 3: Supply Control Circuitry When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON1 and CON2 are both held low for at least 20ms, a 20µA reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins to rise with a slope equal to 20µA/CRAMP (Figure 4), where CRAMP is an external capacitor connected between the 8 1421 F4a Figure 4. Supplies Turning On CLOAD 16 RAMP VOUTLO VOUTHI R4 20k 5% + CLOAD VEE –12V 1A B R5 16k 5% 9 5V CPON –12V 0V CPON B LTC1421 –12V 0V VEE –12V ~1ms ~1ms Figure 5. Negative Supply Control 1421 F05 LTC1421/LTC1421-2.5 U U W U APPLICATIONS INFORMATION PWRGD and RESET The LTC1421 uses a 1.232V bandgap reference, internal resistive divider and a precision voltage comparator to monitor VOUTLO (Figure 6). The reset threshold voltage for VOUTLO is determined by the FB pin connection as summarized in Table 1. VOUTLO VCCLO 20µA 73.5k 71.5k COMP1 – PWRGD FB VCCLO 26.7k + 20µA When VOUTLO drops below its reset threshold, the comparator output goes high, and PWRGD is immediately pulled low (time point 2). After a 32µs delay, RESET is pulled low. The RESET delay allows the PWRGD signal to be used as an early warning that a reset is about to occur. If the PWRGD signal is used as a interrupt input to a microprocessor, a short power-down routine can be run before the reset occurs. If VOUTLO rises above the reset threshold for less than 200ms, the PWRGD output will trip, but the RESET output is not affected (time point 3). If VOUTLO drops below the reset threshold for less than 32µs, the PWRGD output will trip, but again the RESET output will not be affected (time point 5). Voltage Comparator RESET RESET TIMING REF 1.232V 1421 F06 Figure 6. Supply Monitor Block Diagram Table 1 FEEDBACK PIN VOUTLO RESET VOLTAGE Floating 4.65V VOUTLO 2.90V GND 5.88V When the VOUTLO voltage rises above its reset threshold voltage, the comparator output goes low, and PWRGD is immediately pulled high to VCCLO by a weak pull-up current source or external resistor (Figure 7, time points 1 and 4). After a 200ms delay, RESET is pulled high. The weak pull-up current source to VCCLO on PWRGD and RESET have a series diode so the pins can be pulled above VCCLO by an external pull-up resistor without forcing current back into VCCLO. The uncommitted voltage comparator (COMP2) can be used to monitor output voltages other than VOUTLO. Figure 8a shows how the comparator can be used to monitor a 12V supply (VOUTHI), while the 5V supply (VOUTLO) generates a reset when it dips below 4.65V. When the 12V supply drops below 10.8V, COMPOUT will pull low. The FB pin is left floating. Figure 8b shows how the comparator can be used to monitor the 5V supply (VOUTHI) while the 3.3V supply (VOUTLO) generates a reset when it dips below 2.9V. When the 5V supply drops below 4.65V, COMPOUT will pull low. The FB pin is tied to VOUTLO. 5V 12V 20 LTC1421 VCCLO 16 73.5k 20µA COMP1 6 71.5k – VCCLO 10k 5% 26.7k + 1 2 V2 3 V1 V2 4 V1 5 V2 V2 VOUTLO V1 7 COMP2 PWRGD RESET 200ms