LTC1454/LTC1454L
Dual 12-Bit Rail-to-Rail
Micropower DACs
U
DESCRIPTION
FEATURES
■
■
■
■
■
■
■
■
■
■
■
The LTC®1454/LTC1454L are complete single supply,
dual rail-to-rail voltage output, 12-bit digital-to-analog
converters (DACs) in a 16-lead SO package. They include
an output buffer amplifier with variable gain (×1 or × 2)
and an easy-to-use 3-wire cascadable serial interface.
12-Bit Resolution
Buffered True Rail-to-Rail Voltage Output
5V Operation, ICC: 700µA Typ (LTC1454)
3V Operation, ICC: 450µA Typ (LTC1454L)
Built-In Reference: 2.048V (LTC1454)
1.220V (LTC1454L)
CLR Pin
Power-On Reset
16-Lead SO Package
3-Wire Cascadable Serial Interface
Maximum DNL Error: 0.5LSB
Low Cost
The LTC1454 has an onboard reference of 2.048V and a
full-scale output of 4.095V in a × 2 gain configuration. It
operates from a single 4.5V to 5.5V supply.
The LTC1454L has an onboard 1.22V reference and a fullscale output of 2.5V in a × 2 gain configuration. It operates
from a single 2.7V to 5.5V supply.
U
APPLICATIONS
■
■
■
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
■
Low power supply current, excellent DNL and small size
allow these parts to be used in a host of applications where
size, DNL and single supply operation are important.
TYPICAL APPLICATION
Daisy-Chained
Outputs
Functional Block
Diagram: Control
Dual 12-Bit
Rail-to-Rail DAC
9, 15
VCC
LTC1454: 2.048V
10 LTC1454L: 1.22V
0.5
REFOUT
REFHI B 14
0.3
+
4 DIN
µP
3 CLK
5 CS/LD
6 DOUT
24-BIT
SHIFT
REG
AND
DAC
LATCH
VOUT B 16
–
12-BIT
DAC B
X1/X2 B 1
REFHI A
+
12-BIT
DAC A
0.4
11
DNL ERROR (LSB)
LTC1454: 5V
LTC1454L: 3V TO 5V
Differential Nonlinearity
vs Input Code
0.2
0.1
0
–0.1
–0.2
–0.3
VOUT A 8
–0.4
–
–0.5
0
X1/X2 A
POWER-ON
RESET
512 1024 1536 2048 2560 3072 3584 4095
CODE
1454 G08
REFLO
CLR
2
7
12
GND
13
1454 BD02
1
LTC1454/LTC1454L
W
U
U
W W
W
VCC to GND .............................................. – 0.5V to 7.5V
Logic Inputs to GND ................................ – 0.5V to 7.5V
VOUT A , VOUT B, X1/X2 A ,
X1/X2 B ..................................... – 0.5V to VCC + 0.5V
REFHI A , REFHI B, REFLO ............. – 0.5V to VCC + 0.5V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1454C/LTC1454LC ............................ 0°C to 70°C
LTC1454I/LTC1454LI ........................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
16 VOUT B
X1/X2 B 1
CLR 2
15 VCC
CLK 3
14 REFHI B
DIN 4
13 GND
CS/LD 5
12 REFLO
DOUT 6
11 REFHI A
X1/X2 A 7
10 REFOUT
9
VOUT A 8
LTC1454CN
LTC1454IN
LTC1454CS
LTC1454IS
LTC1454LCN
LTC1454LIN
LTC1454LCS
LTC1454LIS
VCC
N PACKAGE
S PACKAGE
16-LEAD PDIP 16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 100°C/W (N)
TJMAX = 125°C, θJA = 150°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, VOUT and REFOUT unloaded,
TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
●
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 1)
INL
Integral Nonlinearity
TA = 25°C
(Note 1)
VOS
Offset Error
VOSTC
Offset Error Temperature
Coefficient
VFS
Full-Scale Voltage
VFSTC
12
Bits
± 0.5
LSB
●
±2.0
±2.5
±4.0
±4.5
LSB
LSB
●
±2.0
±4.0
±12
±18
mV
mV
●
TA = 25°C
±15
µV/°C
When Using Internal Reference, LTC1454, TA = 25°C
LTC1454
●
4.065
4.045
4.095
4.095
4.125
4.145
V
V
When Using Internal Reference, LTC1454L, TA = 25°C
LTC1454L
●
2.470
2.460
2.500
2.500
2.530
2.540
V
V
Full-Scale Voltage
Temperature Coefficient
When Using Internal Reference
Reference Output Voltage
LTC1454
LTC1454L
± 24
ppm/°C
Reference
●
●
2.008
1.195
Reference Line Regulation
Reference Load Regulation
0 ≤ IOUT ≤ 100µA, LTC1454
LTC1454L
Reference Input Range
VREFHI ≤ VCC – 1.5V
Reference Input Resistance
ppm/°C
0.7
±2.0
LSB/V
●
●
0.2
0.6
1.5
3.0
LSB
LSB
40
kΩ
120
mA
VCC / 2
●
15
24
V
15
REFOUT Shorted to GND
V
V
●
Reference Input Capacitance
2
2.088
1.245
±20
Reference Output
Temperature Coefficient
Short-Circuit Current
2.048
1.220
●
40
pF
LTC1454/LTC1454L
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, VOUT and REFOUT unloaded,
TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
5.5
V
V
Power Supply
VCC
Positive Supply Voltage
For Specified Performance, LTC1454
LTC1454L
●
●
4.5
2.7
ICC
Supply Current
4.5V ≤ VCC ≤ 5.5V (Note 4), LTC1454
2.7V ≤ VCC ≤ 5.5V (Note 4), LTC1454L
●
●
700
450
1250
1100
µA
µA
Short-Circuit Current Low
VOUT Shorted to GND
●
70
120
mA
Short-Circuit Current High
VOUT Shorted to VCC
●
80
120
mA
Output Impedance to GND
Input Code = 0
●
40
Ω
Voltage Output Slew Rate
(Note 2)
●
1.0
V/µs
Voltage Output Settling Time
(Notes 2, 3) to ±0.5LSB
14
µs
0.3
nV • s
AC Feedthrough
REFHI = 1kHz, 2VP-P, (Code: All 0s)
– 95
dB
Signal-to-Noise + Distortion
REFHI = 1kHz, 2VP-P, (Code: All 1s)
85
dB
Op Amp DC Performance
AC Performance
0.5
Digital Feedthrough
SINAD
VCC = 5V (LTC1454), 3V (LTC1454L), TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1454
TYP
MAX
MIN
LTC1454L
TYP
MAX
UNITS
Digital I/O
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
2.4
2.0
VOH
Digital Output High Voltage
IOUT = – 1mA
●
VOL
Digital Output Low Voltage
IOUT = 1mA
●
0.4
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
±10
µA
CIN
Digital Input Capacitance
Guaranteed by Design
●
10
10
pF
0.8
VCC – 1.0
V
0.6
V
VCC – 0.7
V
Switching
t1
DIN Valid to CLK Setup
●
40
60
ns
t2
DIN Valid to CLK Hold
●
0
0
ns
t3
CLK High Time
●
40
60
ns
t4
CLK Low Time
●
40
60
ns
t5
CS/LD Pulse Width
●
50
80
ns
t6
LSB CLK to CS/LD
●
40
60
ns
t7
CS/LD Low to CLK
●
20
30
ns
t8
DOUT Output Delay
t9
CLK Low to CS/LD Low
CLOAD = 15pF
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to code 4095 (full scale).
150
●
●
20
220
30
ns
ns
Note 2: Load is 5kΩ in parallel with 100pF.
Note 3: DAC switched between all 1s and the code corresponding to VOS
for the part.
Note 4: Digital inputs at 0V or VCC.
3
LTC1454/LTC1454L
U W
TYPICAL PERFORMANCE CHARACTERISTICS
LTC1454
Integral Nonlinearity
2.0
0.4
1.6
0.3
1.2
0.2
0.8
0.1
0
–0.1
–0.2
Minimum Supply Headroom for
Full Output Swing vs Load Current
1.0
0.4
0
–0.4
–1.2
–0.4
–1.6
0
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
3.5
–55°C
500
400
300
OUTPUT SWING (V)
600
3.0
2.5
2.0
RL
1.5
3.0
VCC
2.5
1.5
1.0
1.0
100
0.5
0.5
0.1
0
5
10
15
20
25
OUTPUT SINK CURRENT (mA)
30
0
100
1k
LOAD RESISTANCE (Ω)
10
100
1k
LOAD RESISTANCE (Ω)
LTC1454 Supply Current vs
Logic Input Voltage
LTC1454
Supply Current vs Temperature
2.6
760
4.110
10k
1458 G06
1454 G05
LTC1454 Full-Scale Voltage vs
Temperature
SUPPLY CURRENT (µA)
4.100
4.095
4.090
4.085
VCC = 5.5V
740
730
720
VCC = 5V
710
700
–25
5
35
65
TEMPERATURE (°C)
95
125
1454 G02
SUPPLY CURRENT (mA)
750
4.105
4
10
10k
1454 G04
4.080
–55
RL
2.0
200
0
REFLO = GND
X1/X2 = GND
4.0
3.5
700
OUTPUT SWING (V)
OUTPUT PULL-DOWN VOLTAGE (mV)
800
30
4.5
REFLO = GND
X1/X2 = GND
4.0
25°C
25
LTC1454 Output Swing vs
Load Resistance
4.5
125°C
10
15
20
LOAD CURRENT (mA)
1454 G03
LTC1454 Output Swing vs
Load Resistance
1000
900
5
1454 G07
LTC1454 Minimum Output
Voltage vs Output Sink Current
SFULL-SCALE VOLTAGE (V)
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
1454 G08
REFLO = GND
X1/X2 = GND
0.4
0.2
–2.0
0
0.6
–0.8
–0.3
–0.5
∆VOUT < 1LSB
REFLO = GND
X1/X2 = GND
CODE: ALL 1's
VOUT = 4.095V
0.8
VCC – VOUT (V)
0.5
INL ERROR (LSB)
DNL ERROR (LSB)
LTC1454
Differential Nonlinearity
690
–55
2.1
1.6
1.1
VCC = 4.5V
0.6
–25
35
65
5
TEMPERATURE (°C)
95
125
1454 G01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE (V)
1454 G09
LTC1454/LTC1454L
U
U
U
PIN FUNCTIONS
X1/X2 B, X1/X2 A (Pins 1, 7): For LTC1454, when this pin
is grounded, the gain will be 2. When connected to VOUT
the gain will be 1. In a gain of 2 configuration, the output
full scale will be 2 × REFHI. When using the internal
reference, this value is 4.096V. For the LTC1454L, when
this pin is grounded, the gain will be 2.05. When connected
to VOUT the gain will be 1. In a gain of 2 configuration, the
output full scale will be 2.05 × REFHI. When using the
internal reference this value is 2.5V.
CS/LD (Pin 5): The Serial Interface Enable and Load
Control Input. When CS/LD is low the CLK signal is
enabled so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
CLR (Pin 2): The Clear Pin for the DAC. Clears both DACs
to zero scale when pulled low. This pin should be tied to
VCC for normal operation.
VCC (Pins 9, 15): The Positive Supply Input. 4.5 ≤ VCC
≤ 5.5V (LTC1454), 2.7V ≤ VCC ≤ 5.5V (LTC1454L). Requires a bypass capacitor to ground.
CLK (Pin 3): The Serial Interface Clock Input.
REFOUT (Pin 10): The Output of the Internal Reference.
DIN (Pin 4): The Serial Data Input. Data on the DIN pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded as one 24-bit word. The first 12 bits
are for DAC A, MSB-first and the second 12 bits are for
DAC B, MSB-first.
REFHI A , REFHI B (Pins 11,14): The Inputs to the DAC
Resistor Ladder for DAC A/B.
DOUT (Pin 6): The Output of the Shift Register which
Becomes Valid on the Rising Edge of the Serial Clock.
VOUT A, VOUT B (Pins 8, 16): The Buffered DAC Outputs.
REFLO (Pin 12): The Bottom of the DAC Resistor Ladder
for Both DACs. This can be used to offset zero-scale above
ground. REFLO should be connected to ground when no
offset is required.
GND (Pin 13): Ground.
5
LTC1454/LTC1454L
W
BLOCK DIAGRA
R
R
X1/X2 B
1
16
VOUT B
CLR
2
15
VCC
CLK
3
14
REFHI B
13
GND
12
REFLO
11
REFHI A
10
REFOUT
9
VCC
–
DIN
CS/LD
5
DOUT
6
X1/X2 A
LD
4
12-BIT
DAC B
REGISTER
+
DAC B
24-BIT
SHIFT
REGISTER
LD
12-BIT
DAC A
REGISTER
+
DAC A
A
REFERENCE
LTC1454: 2.048V
LTC1454L: 1.22V
–
POWER-ON
RESET
7
R
VOUT A
B
R
8
1454 BD01
WU
W
TI I G DIAGRA
CLK
DIN
t4
B0 B
PREVIOUS WORD
B11 A
MSB
CS/LD
DOUT
t2
t6
B11 B
MSB
B0 B
LSB
t1
t9
t3
B0 A
LSB
t5
t8
B11 A
PREVIOUS WORD
B10 A
PREVIOUS WORD
t7
B0 A
PREVIOUS WORD
B11 B
PREVIOUS WORD
B0 B
PREVIOUS WORD
B11 A
CURRENT WORD
1454/5 • TD01
6
LTC1454/LTC1454L
U
U
DEFI ITIO S
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2n) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (VOS): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
0V
Nominal LSBs:
LTC1454
LTC1454L
LSB = 4.095V/4095 = 1mV
LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated
as follows:
INL = [VOUT – VOS – (VFS – VOS)(Code/4095)]/LSB
VOUT = The output voltage of the DAC measured at
the given input code
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/4095
DAC CODE
LTC1454/5 • F01
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification:
VOS = VOUT – (Code)(VFS)/(2n – 1)
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
∆VOUT = The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
7
LTC1454/LTC1454L
U
OPERATIO
Serial Interface
Reference
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 24-bit
word, DAC A first, then DAC B. The MSB is loaded first for
each DAC. The DAC registers load the data from the shift
register when CS/LD is pulled high. The CLK is disabled
internally when CS/LD is high. Note: CLK must be low
before CS/LD is pulled low to avoid an extra internal clock
pulse.
The LTC1454L has an internal reference of 1.22V with a full
scale of 2.5V (gain of 2 configuration). The LTC1454
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than VCC /2 and be
capable of driving the 15k minimum DAC resistor ladder.
With a gain of 1 configuration the external reference must
be less than VCC – 1.5V.
The buffered output of the 24-bit shift register is available
on the DOUT pin which swings from ground to VCC.
Voltage Output
Multiple LTC1454/LTC1454Ls may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
8
The rail-to-rail buffered output of the LTC1454 family can
source or sink 5mA when operating with a 5V supply while
pulling to within 300mV of the positive supply voltage or
ground. The output swings to within a few millivolts of
either supply rail when unloaded and has an equivalent
output resistance of 40Ω when driving a load to the rails.
The output can drive 1000pF without going into oscillation.
LTC1454/LTC1454L
U
U
W
U
APPLICATIONS INFORMATION
ground of 1.22V. The outputs will swing from 0V to 2.44V,
as shown by the equation with the figure. Since the signal
ground is around 1.22V, REFLO is offset above ground by
using an LT1034CS8-1.2 as shown.
A Single Supply, 4-Quadrant Multiplying DAC
The LTC1454 can also be used for 4-quadrant multiplying
with an offset signal ground of 1.22V. This application is
shown in Figure 2. The inputs are connected to REFHI B or
REFHI A and have a 1.22V amplitude around a signal
5V
0.1µF
X1/X2 B
VOUT B
VOUT B
CLR
VCC
CLK
CLK
REFHI B
DIN
DIN
VINB
1.22V ± 1.22V
10k
GND
LTC1454
CS/LD
VOUT A
CS/LD
REFLO
DOUT
REFHI A
X1/X2 A
REFOUT
VOUT A
VINA
1.22V ± 1.22V
LT1034CS8-1.2
VCC
(
)
(
)
DIN
VOA/B = VIN – VREFLO GAIN
– 1 +1 + VREFLO
4096
(
)
(
= VIN – 1.22 2.0
)
DIN
– 1.0 + 1.22V
4096
1454 F02
Figure 2
9
LTC1454/LTC1454L
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.025
0.325 –0.015
+0.635
8.255
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
0.018 ± 0.003
(0.457 ± 0.076)
N16 0695
LTC1454/LTC1454L
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
7
0.050
(1.270)
TYP
S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1454/LTC1454L
U
TYPICAL APPLICATION
LTC1454: 4.5V TO 5.5V
LTC1454L: 2.7V TO 5.5V
X1/X2 B
µP
TO NEXT DAC
FOR DAISY-CHAINING
OUTPUT A
LTC1454: 0V TO 4.095V
LTC1454L: 0V TO 2.5V
VOUT B
CLR
VCC
CLK
REFHI B
OUTPUT B
LTC1454: 0V TO 4.095V
LTC1454L: 0V TO 2.5V
0.1µF
LTC1454 GND
LTC1454L
CS/LD
REFLO
DIN
DOUT
REFHI A
X1/X2 A
REFOUT
VOUT A
VCC
LTC1454: 2.048V
LTC1454L: 1.22V
1454 TA01
RELATED PARTS
PART NUMBER
LTC1257
LTC1446/LTC1446L
DESCRIPTION
Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,
Reference Can Be Overdriven up to 12V, i.e., FSMAX = 12V
Dual 12-Bit Rail-to-Rail Output DACs in an SO-8 Package
LTC1450/LTC1450L
Single 12-Bit Rail-to-Rail Output DACs with Parallel Interface
LTC1451
LTC1452
Single 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V
Single 12-Bit Rail-to-Rail Output VOUT Multiplying DAC,
VCC: 2.7V to 5.5V
Single 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, VCC: 4.5V to 5.5V
Quad 12-Bit Rail-to-Rail Output DACs
LTC1453
LTC1456
LTC1458/LTC1458L
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
COMMENTS
5V to 15V Single Supply, Complete VOUT DAC in
SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
Low Power, Complete VOUT DAC in SO-8 Package
Low Power, Multiplying VOUT DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
3V, Low Power, Complete VOUT DAC in SO-8 Package
Low Power, Complete VOUT DAC in SO-8 Package, with
Clear Pin
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
sn1454 1454lfs LT/TP 0397 7K • PRINTED IN
USA
LINEAR TECHNOLOGY CORPORATION 1996
工商网监
湘ICP备2023018690号
