LTC1481IS8#PBF

LTC1481 Ultralow Power RS485 Transceiver with Shutdown U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Power: ICC = 120µA Max with Driver Disabled Drivers/Receivers Have ±10kV ESD Protection 1µA Quiescent Current in Shutdown Mode High Speed: Up to 2.5Mbits/s Data Rate ICC = 500µA Max with Driver Enabled, No Load Single 5V Supply – 7V to 12V Common Mode Range Permits ±7V Ground Difference Between Devices on the Data Line Thermal Shutdown Protection Power Up/Down Glitch-Free Driver Outputs Permit Live Insertion or Removal of Transceiver Driver Maintains High Impedance in Three-State or with the Power Off Up to 32 Transceivers on the Bus 30ns Typical Driver Propagation Delays with 5ns Skew Pin Compatible with the LTC485 U APPLICATIO S ■ ■ The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open. The LTC1481 is fully specified over the commercial and extended industrial temperature range and is available in 8-pin PDIP and SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Battery-Powered RS485/RS422 Applications Low Power RS485/RS422 Transceiver Level Translator U ■ The LTC®1481 is an ultralow power differential line transceiver designed for data transmission standard RS485 applications. It will also meet the requirements of RS422. The CMOS design offers significant power savings over its bipolar counterparts without sacrificing ruggedness against overload or ESD damage. Typical quiescent current is only 80µA while operating and less than 1µA in shutdown. TYPICAL APPLICATIO Supply Current vs Temperature 350 R VCC1 RE1 Rt DE1 DI1 D GND1 Rt RO2 R THERMAL SHUTDOWN WITH DRIVER ENABLED 300 VCC2 SUPPLY CURRENT (µA) RO1 250 DRIVER ENABLED 200 150 100 DRIVER DISABLED RE2 50 DE2 DI2 D GND2 LTC1481 • TA01 0 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1481 TA02 1481fa 1 LTC1481 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) .............................................. 12V Control Input Voltage ..................... – 0.5V to VCC + 0.5V Driver Input Voltage ....................... – 0.5V to VCC + 0.5V Driver Output Voltage ........................................... ±14V Receiver Input Voltage .......................................... ±14V Receiver Output Voltage ................ – 0.5V to VCC + 0.5V Operating Temperature Range LTC1481C ....................................... 0°C ≤ TA ≤ 70°C LTC1481I .................................... – 40°C ≤ TA ≤ 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW RO 1 R RE 2 DE 3 DI 4 D N8 PACKAGE 8-LEAD PDIP 8 VCC 7 B 6 A 5 GND S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 130°C/ W (N8) TJMAX = 125°C, θJA = 150°C/ W (S8) LTC1481CN8 LTC1481IN8 LTC1481CS8 LTC1481IS8 S8 PART MARKING 1481 1481I Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3) unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOD1 Differential Driver Output Voltage (Unloaded) IO = 0 ● MIN VOD2 Differential Driver Output Voltage (with Load) R = 50Ω (RS422) R = 27Ω (RS485), Figure 1 ● ● TYP 2.0 1.5 MAX UNITS 5 V 5 V V 0.2 V ∆VOD Change in Magnitude of Driver Differential Output Voltage for Complementary Output States R = 27Ω or R = 50Ω, Figure 1 ● VOC Driver Common Mode Output Voltage R = 27Ω or R = 50Ω, Figure 1 ● 3 V ∆VOC Change in Magnitude of Driver Common Mode Output Voltage for Complementary Output States R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V VIH Input High Voltage DE, DI, RE ● VIL Input Low Voltage DE, DI, RE ● 0.8 V IIN1 Input Current DE, DI, RE ● ±2 µA IIN2 Input Current (A, B) DE = 0, VCC = 0V or 5.25V, VIN = 12V DE = 0, VCC = 0V or 5.25V, VIN = – 7V ● ● 1.0 – 0.8 mA mA VTH Differential Input Threshold Voltage for Receiver – 7V ≤ VCM ≤ 12V ● 0.2 V ∆VTH Receiver Input Hysteresis VCM = 0V ● VOH Receiver Output High Voltage IO = – 4mA, VID = 200mV ● VOL Receiver Output Low Voltage IO = 4mA, VID = – 200mV ● 0.4 V IOZR Three-State (High Impedance) Output Current at Receiver VCC = Max, 0.4V ≤ VO ≤ 2.4V ● ±1 µA RIN Receiver Input Resistance – 7V ≤ VCM ≤ 12V ● ICC Supply Current No Load, Output Enabled No Load, Output Disabled ● ● ISHDN Supply Current in Shutdown Mode DE = 0, RE = VCC IOSD1 Driver Short-Circuit Current, VOUT = HIGH – 7V ≤ VO ≤ 12V ● IOSD2 Driver Short-Circuit Current, VOUT = LOW – 7V ≤ VO ≤ 12V IOSR Receiver Short-Circuit Current 0V ≤ VO ≤ VCC 2 V – 0.2 45 mV 3.5 V 12 kΩ 300 80 500 120 µA µA 1 10 µA 35 250 mA ● 35 250 mA ● 7 85 mA 1481fa 2 LTC1481 U SWITCHI G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX tPLH Driver Input to Output tPHL Driver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3, 5) tSKEW Driver Output to Output ● tr, tf Driver Rise or Fall Time ● tZH Driver Enable to Output High CL = 100pF (Figures 4, 6), S2 Closed tZL Driver Enable to Output Low tLZ Driver Disable Time from Low tHZ tPLH tPHL Receiver Input to Output tSKD tPLH – tPHL Differential Receiver Skew tZL Receiver Enable to Output Low tZH Receiver Enable to Output High tLZ tHZ fMAX Maximum Data Rate ● 2.5 tSHDN Time to Shutdown DE = 0, RE = ● 50 tZH(SHDN) Driver Enable from Shutdown to Output High CL = 100pF (Figures 4, 6), S2 Closed tZL(SHDN) Driver Enable from Shutdown to Output Low tZH(SHDN) Receiver Enable from Shutdown to Output High tZL(SHDN) Receiver Enable from Shutdown to Output Low UNITS ● 10 30 60 ns ● 10 30 60 ns 5 10 ns 3 15 40 ns ● 40 70 ns CL = 100pF (Figures 4, 6), S1 Closed ● 40 70 ns CL = 15pF (Figures 4, 6), S1 Closed ● 40 70 ns Driver Disable Time from High CL = 15pF (Figures 4, 6), S2 Closed ● 40 70 ns Receiver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3, 7) ● 30 140 200 ns ● 30 140 200 ns ● 13 CRL = 15pF (Figures 2, 8), S1 Closed ● 20 50 ns CRL = 15pF (Figures 2, 8), S2 Closed ● 20 50 ns Receiver Disable from Low CRL = 15pF (Figures 2, 8), S1 Closed ● 20 50 ns Receiver Disable from High CRL = 15pF (Figures 2, 8), S2 Closed ● 20 50 ns 200 600 ns ● 40 100 ns CL = 100pF (Figures 4, 6), S1 Closed ● 40 100 ns CL = 15pF (Figures 2, 8), S2 Closed ● 3500 ns CL = 15pF (Figures 2, 8), S1 Closed ● 3500 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. ns Mbits/s Note 3: All typicals are given for VCC = 5V and TA = 25°C. U W TYPICAL PERFOR A CE CHARACTERISTICS Driver Differential Output Voltage vs Temperature Driver Differential Output Voltage vs Output Current 2.5 TA = 25°C DIFFERENTIAL VOLTAGE (V) OUTPUT CURRENT (mA) 60 50 40 30 20 10 0 1 2 4 3 OUTPUT VOLTAGE (V) 5 1481 G01 TA = 25°C 60 2.3 2.2 2.1 2.0 1.9 1.8 50 40 30 20 1.7 10 1.6 0 70 RL = 54Ω 2.4 OUTPUT CURRENT (mA) 70 Driver Output Low Voltage vs Output Current 1.5 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 0 0 1 2 3 4 OUTPUT VOLTAGE (V) 1481 G02 1481 G03 1481fa 3 LTC1481 U W TYPICAL PERFOR A CE CHARACTERISTICS Receiver tPLH – tPHL vs Temperature Driver Output High Voltage vs Output Current 0 TA = 25°C 3.0 12 2.5 –20 10 –40 –50 2.0 TIME (ns) –30 TIME (ns) OUTPUT CURRENT (mA) –10 Driver Skew vs Temperature 14 8 6 –60 1.5 1.0 4 –70 0.5 2 –80 –90 0 1 2 3 OUTPUT VOLTAGE (V) 0 –50 –25 5 4 50 25 75 0 TEMPERATURE (°C) 1481 G04 100 0 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 125 1481 G05 1481 G05 U U U PI FU CTIO S RO (Pin 1): Receiver Output. If the receiver output is enabled (RE low), then if A > B by 200mV, RO will be high. If A < B by 200mV, then RO will be low. RE (Pin 2): Receiver Output Enable. A low enables the receiver output, RO. A high input forces the receiver output into a high impedance state. DE (Pin 3): Driver Outputs Enable. A high on DE enables the driver output. A, B and the chip will function as a line driver. A low input will force the driver outputs into a high impedance state and the chip will function as a line receiver. If RE is high and DE is low, the part will enter a low power (1µA) shutdown state. DI (Pin 4): Driver Input. If the driver outputs are enabled (DE high) then a low on DI forces the outputs A low and B high. A high on DI with the driver outputs enabled will force A high and B low. GND (Pin 5): Ground. A (Pin 6): Driver Output/Receiver Input. B (Pin 7): Driver Output/Receiver Input. VCC (Pin 8): Positive Supply. 4.75V < VCC < 5.25V. U U FU CTIO TABLES LTC1481 Receiving LTC1481 Transmitting INPUTS INPUTS OUTPUTS OUTPUTS RE DE DI B A RE DE A–B RO X 1 1 0 1 0 0 ≥ 0.2V 1 0 ≤ – 0.2V 0 X 1 0 1 0 0 0 0 X Z Z 0 0 Inputs Open 1 1 0 X Z* Z* 1 0 X Z* *Shutdown mode for LTC1481 *Shutdown mode for LTC1481 1481fa 4 LTC1481 TEST CIRCUITS A R VOD 1k VCC VOC R S1 TEST POINT RECEIVER OUTPUT 1k CRL S2 B LTC1481 • F01 LTC1481 • F02 Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load 3V DE A DI CL1 S1 VCC RO RDIFF B A B CL2 15pF RE 500Ω OUTPUT UNDER TEST S2 CL LTC1481 • F03 LTC1481 • F04 Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load U W W SWITCHI G TI E WAVEFOR S 3V f = 1MHz, tr ≤ 10ns, tf ≤ 10ns 1.5V DI 1.5V 0V t PLH 1/2 VO t PHL B VO A VO 0V –VO tSKEW 1/2 VO t SKEW 90% 90% 10% VDIFF = V(A) – V(B) 10% tr LTC1481 • F05 tf Figure 5. Driver Propagation Delays 3V f = 1MHz, tr ≤ 10ns, tf ≤ 10ns 1.5V DE 1.5V 0V 5V A, B t ZL(SHDN), t ZL 2.3V OUTPUT NORMALLY LOW 0.5V 2.3V OUTPUT NORMALLY HIGH 0.5V VOL VOH A, B t LZ 0V t ZH(SHDN), t ZH t HZ LTC1481 • F06 Figure 6. Driver Enable and Disable Times 1481fa 5 LTC1481 U W W SWITCHI G TI E WAVEFOR S VOH 1.5V RO 1.5V OUTPUT VOL f = 1MHz, tr ≤ 10ns, tf ≤ 10ns t PHL VOD2 A–B –VOD2 0V t PLH 0V INPUT LTC1481 • F07 Figure 7. Receiver Propagation Delays 3V 1.5V RE t ZL(SHDN), tZL 5V RO RO 1.5V f = 1MHz, tr ≤ 10ns, tf ≤ 10ns 0V t LZ 1.5V OUTPUT NORMALLY LOW 0.5V 1.5V OUTPUT NORMALLY HIGH 0.5V 0V t ZH(SHDN), tZH t HZ LTC1481 • F08 Figure 8. Receiver Enable and Disable Times U W U U APPLICATIO S I FOR ATIO Basic Theory of Operation Traditionally, RS485 transceivers have been designed using bipolar technology because the common mode range of the device must extend beyond the supplies and the device must be immune to ESD damage and latch-up. Unfortunately, most bipolar devices draw a large amount of supply current, which is unacceptable for the numerous applications that require low power consumption. The LTC1481 is a CMOS RS485/RS422 transceiver which features ultralow power consumption without sacrificing ESD and latch-up immunity. The LTC1481 uses a proprietary driver output stage, which allows a common mode range that extends beyond the power supplies while virtually eliminating latch-up and providing excellent ESD protection. Figure 9 shows the LTC1481 output stage while Figure 10 shows a conventional CMOS output stage. When the conventional CMOS output stage of Figure 10 enters a high impedance state, both the P-channel (P1) and the N-channel (N1) are turned off. If the output is then driven above VCC or below ground, the P+/N -well diode (D1) or the N+/P-substrate diode (D2) respectively will turn on and clamp the output to the supply. Thus, the output stage is no longer in a high impedance state and is not able to meet the RS485 common mode range requirement. In addition, the large amount of current flowing through either diode will induce the well-known CMOS latch-up condition, which could destroy the device. The LTC1481 output stage of Figure 9 eliminates these problems by adding two Schottky diodes, SD3 and SD4. The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the output stage is operating normally, the Schottky diodes are forward biased and have a small voltage drop across them. When the output is in the high impedance state and is driven above VCC or below ground, the parasitic diode D1 or D2 still turns on, but SD3 or SD4 will reverse bias and prevent current from flowing into the N-well or the substrate. Thus the high impedance state is maintained even with the output voltage beyond the supplies. With no minority carrier current flowing into the N-well or substrate, latch-up is virtually eliminated under power-up or power-down conditions. 1481fa 6 LTC1481 U W U U APPLICATIO S I FOR ATIO Low Power Operation VCC SD3 P1 D1 OUTPUT LOGIC SD4 N1 D2 ESD Shutdown Mode LTC1481 • F09 Figure 9. LTC1481 Output Stage VCC P1 D1 OUTPUT LOGIC N1 The LTC1481 is designed to operate with a quiescent current of 120µA max. With the driver in three-state, ICC will drop to this 120µA level. With the driver enabled there will be additional current drawn by the internal 12k resistor. Under normal operating conditions this additional current is overshadowed by the current drawn by the external bus impedance. D2 Both the receiver output (RO) and the driver outputs (A, B) can be placed in three-state mode by bringing RE high and DE low respectively. In addition, the LTC1481 will enter shutdown mode when RE is high and DE is low. In shutdown the LTC1481 typically draws only 1µA of supply current. In order to guarantee that the part goes into shutdown, DE must be low and RE must be high for at least 600ns simultaneously. If this time duration is less than 50ns the part will not enter shutdown mode. Toggling either RE or DE will wake the LTC1481 back up within 3.5µs. Propagation Delay Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and receiver. Figure 11 shows the test circuit for the LTC1481 propagation delay. LTC1481 • F10 Figure 10. Conventional CMOS Output Stage The LTC1481 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either VCC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is well beyond the RS485 operating range. Because the ESD injected current in the N-well or substrate consists of majority carriers, latch-up is prevented by careful layout techniques. An ESD cell protects output against multiple 10kV human body model ESD strikes. The receiver delay times are: tPLH – tPHL = 13ns Typ, VCC = 5V The drivers skew times are: Skew = 5ns Typ, VCC = 5V 10ns Max, VCC = 5V, TA = – 40°C to 85°C 100pF TTL IN t r, t f < 6ns D R 54Ω R RECEIVER OUT LTC1481 • F11 100pF Figure 11. Receiver Propagation Delay Test Circuit 1481fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 7 LTC1481 U PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .300 – .325 (7.620 – 8.255) ( +0.889 8.255 –0.381 .130 ± .005 (3.302 ± 0.127) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .008 – .015 (0.203 – 0.381) +.035 .325 –.015 .400* (10.160) MAX ) 8 7 6 1 2 3 5 .255 ± .015* (6.477 ± 0.381) .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 .100 (2.54) BSC 4 N8 1002 (0.457 ± 0.076) NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .010 – .020 × 45° (0.254 – 0.508) .004 – .010 (0.101 – 0.254) .053 – .069 (1.346 – 1.752) .008 – .010 (0.203 – 0.254) NOTE: 1. DIMENSIONS IN 7 6 .045 ±.005 5 .050 BSC N N 0°– 8° TYP .016 – .050 (0.406 – 1.270) 8 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .050 (1.270) BSC .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .245 MIN .160 ±.005 N/2 1 SO8 0502 1 2 3 4 .030 ±.005 TYP 2 3 N/2 RECOMMENDED SOLDER PAD LAYOUT RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC486 Quad RS485 Driver Fits 75172 Pinout, Only 110µA IQ LTC488 Quad RS485 Receiver Fits 75173 Pinout, Only 7µA IQ LTC490 Full Duplex RS485 Transceiver Fits 75179 Pinout, Only 300µA IQ LTC1485 Differential Bus Transceiver Fits 75176A Pinout, Only 1.7mA IQ 1481fa 8 Linear Technology Corporation LT/TP 0303 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 1994