LTC1530
High Power Synchronous
Switching Regulator Controller
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FEATURES
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DESCRIPTIO
The LTC®1530 is a high power synchronous switching
regulator controller optimized for 5V to 1.3V-3.5V output
applications. Its synchronous switching architecture drives
two external N-channel MOSFET devices to provide high
efficiency. The LTC1530 contains a precision trimmed
reference and feedback system that provides worst-case
output voltage regulation of ±2% over temperature, load
current and line voltage shifts. Current limit circuitry
senses the output current through the on-resistance of
the topside N-channel MOSFET, providing an adjustable
current limit without requiring an external low value sense
resistor.
High Power Buck Converter from 5V or 3.3V Input
Adjustable Current Limit in S0-8 with
Topside FET RDS(ON) Sensing
No External Sense Resistor Required
Hiccup Mode Current Limit Protection
Adjustable, Fixed 1.9V, 2.5V, 2.8V and 3.3V Output
All N-Channel MOSFET Synchronous Driver
Excellent Output Regulation: ±2% over Line, Load
and Temperature Variations
High Efficiency: Over 95% Possible
Fast Transient Response
Fixed 300kHz Frequency Operation
Internal Soft-Start Circuit
Quiescent Current: 1mA; 45µA in Shutdown
The LTC1530 includes a fixed frequency PWM oscillator
that free runs at 300kHz, providing greater than 90%
efficiency in converter designs from 1A to 20A of output
current. Shutdown mode drops the LTC1530 supply current to 45µA.
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APPLICATIO S
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Power Supply for Pentium® II, AMD-K6®-2, SPARC,
ALPHA and PA-RISC Microprocessors
High Power 5V to 1.3V-3.5V Regulators
The LTC1530 is specified for commercial and industrial
temperature ranges and is available in the S0-8 package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corp.
AMD-K6 is a registered trademark of Advanced Micro Devices, Inc.
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TYPICAL APPLICATIO
Efficiency vs Load Current
VIN
5V
100
90
MBR0530T1 MBR0530T1
+
+
10µF
80
CIN1200µF
×4
0.22µF
IMAX PVCC
150pF
0.022µF
10k
20Ω
IFB
COMP
LTC1530-3.3
G2
GND
L1
2µH
Q1
G1
+
Q2
COUT
330µF
×7
VOUT
3.3V
14A
70
60
50
40
30
20
1530 F01a
VOUT
EFFICIENCY (%)
0.1µF
2.7k
CIN: SANYO 10MV1200GX
COUT: AVX TPSE337M006R0100
L1: COILTRONICS CTX02-13198
OR PANASONIC ETQP6F2R5HA
Q1, Q2: SILICONIX SUD50N03-10
10
TA = 25°C
0
0
0.3
2
8
4
10
6
LOAD CURRENT (A)
12
14
1530 F01b
Figure 1. Single 5V to 3.3V Supply
1530fa
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LTC1530
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage
PVCC ........................................................................ 14V
Input Voltage
IFB (Note 2) ............................................... PVCC + 0.3V
IMAX ........................................................ – 0.3V to 14V
IFB Input Current (Notes 2,3) ............................ – 100mA
Operating Ambient Temperature Range
LTC1530C ............................................... 0°C to 70°C
LTC1530I ............................................ – 40°C to 85°C
Maximum Junction Temperature
LTC1530C, LTC1530I ...................................... 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
PVCC 1
8
G1
GND 2
*VSENSE /
VOUT 3
7
G2
6
IFB
COMP 4
5
IMAX
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 130°C/ W
*VOUT FOR FIXED VOLTAGE VERSIONS
LTC1530CS8
LTC1530CS8-1.9
LTC1530CS8-2.5
LTC1530CS8-2.8
LTC1530CS8-3.3
LTC1530IS8
LTC1530IS8-1.9
LTC1530IS8-2.5
LTC1530IS8-2.8
LTC1530IS8-3.3
S8 PART MARKING
1530
153019
153025
153028
153033
1530I
530I19
530I25
530I28
530I33
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. PVCC = 12V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VSENSE
Internal Feedback Voltage
LTC1530CS8 (Note 4)
VOUT
Output Voltage
MIN
TYP
MAX
UNITS
●
1.223
1.216
1.235
1.235
1.247
1.254
V
V
●
1.881
1.871
1.9
1.9
1.919
1.929
V
V
●
2.475
2.462
2.5
2.5
2.525
2.538
V
V
●
2.772
2.758
2.8
2.8
2.828
2.842
V
V
●
3.267
3.250
3.3
3.3
3.333
3.350
V
V
●
1.6
2
2.6
LTC1530CS8-1.9 (Note 4)
LTC1530CS8-2.5 (Note 4)
LTC1530CS8-2.8 (Note 4)
LTC1530CS8-3.3 (Note 4)
gmERR
Error Amplifier Transconductance
(Note 5)
millimho
The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PVCC = 12V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
PVCC
Supply Voltage
(Note 6)
VUVLO
Undervoltage Lockout Voltage
(Note 7)
VSENSE
Internal Feedback Voltage
LTC1530IS8 (Note 4)
MIN
TYP
MAX
UNITS
13.2
V
3.5
3.75
V
1.235
1.235
1.247
1.260
V
V
●
●
1.223
1.210
1530fa
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LTC1530
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. PVCC = 12V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT
Output Voltage
LTC1530IS8-1.9 (Note 4)
●
1.881
1.862
1.9
1.9
1.919
1.938
V
V
●
2.475
2.450
2.5
2.5
2.525
2.550
V
V
●
2.772
2.744
2.8
2.8
2.828
2.856
V
V
●
3.267
3.234
3.3
3.3
3.333
3.366
V
V
LTC1530IS8-2.5 (Note 4)
LTC1530IS8-2.8 (Note 4)
LTC1530IS8-3.3 (Note 4)
∆VOUT
IPVCC
fOSC
Output Load Regulation
IOUT = 0 to 14A
–5
Output Line Regulation
VIN = 4.75V to 5.25V, IOUT = 0
±1
mV
Operating Supply Current
Figure 3, VFB = 0V (Note 8)
15
mA
Quiescent Current
Figure 3, COMP = 0.5V, VFB = 5V
●
Shutdown Supply Current
Figure 3, COMP = 0 (Note 9)
●
Internal Oscillator Frequency
Figure 4
●
Oscillator Valley Voltage
VCOMP at 0% Duty Cycle
1.0
250
mV
1.4
mA
45
80
µA
300
350
kHz
2.5
V
Oscillator Peak Voltage
VCOMP at Max Duty Cycle
3.5
V
GERR
Error Amplifier Open-Loop DC Gain
(Note 5)
●
40
54
dB
gmERR
Error Amplifier Transconductance
(Note 5)
●
1.6
2
2.8
millimho
IMAX
IMAX Sink Current
VIMAX = 5V
VIMAX = 5V
●
170
120
200
200
230
300
µA
µA
IMAX Sink Current Tempco
VIMAX = 5V
3300
ppm/°C
VSHDN
Shutdown Threshold Voltage
Figure 4, Measured at COMP Pin (Note 9)
180
mV
SRSS
Internal Soft-Start Slew Rate
Figure 4, COMP Pulls High, VFB = 0V
(Notes 9, 10)
0.4
V/ms
t SS
Internal Soft-Start Wake-Up Time
Figure 4, COMP Pulls High to G1↑ (Note 10)
3.5
ms
t r, t f
Driver Rise and Fall Time
Figure 4
●
t NOL
Driver Nonoverlap Time
Figure 4
●
30
100
ns
DCMAX
Maximum G1 Duty Cycle
Figure 4
●
81
86
%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If IFB is taken below GND, it is clamped by an internal diode. This
pin handles input currents ≤ 100mA below GND without latch-up. In the
positive direction, it is not clamped to PVCC.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: The LTC1530 is tested in an op amp feedback loop which
regulates VSENSE or VOUT based on VCOMP = 2V for the error amplifier.
Note 5: The Open-loop DC gain and transconductance from the VFB pin to
the COMP pin are GERR and gmERR respectively. For fixed output voltage
versions, the actual open-loop DC gain and transconductance are GERR
and gmERR multiplied by the ratio 1.235/VOUT.
●
100
90
140
ns
Note 6: The total voltage from the PVCC pin to the GND pin must be ≥ 8V
for the current limit protection circuit to be active.
Note 7: G1 and G2 begin to switch once PVCC is ≥ the undervoltage
lockout threshold voltage.
Note 8: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This current varies
with the LTC1530 operating frequency, supply voltage and the external
FETs used.
Note 9: The LTC1530 enters shutdown if COMP is pulled low.
Note 10: Slew rate is measured at the COMP pin on the transition from
shutdown to active mode.
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LTC1530
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TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
Efficiency vs Load Current
90
2.508
80
2.506
1.250
2.504
1.245
2.502
1.240
EFFICIENCY (%)
70
60
50
40
20
TA = 25°C
REFER TO FIGURE 10
10
1.260
TA = 25°C
REFER TO FIGURE 2
1.255
VSENSE (V)
OUTPUT VOLTAGE (V)
2.510
30
2.500
2.498
0
0.3
2
8
4
10
6
LOAD CURRENT (A)
12
1.235
1.230
2.496
1.225
2.494
1.220
2.492
1.215
2.490
0
0
14
1
2
3
4
OUTPUT CURRENT (A)
5
1.210
–55 –35 –15
6
1530 G02
1530 G01
LTC1530-2.8 VOUT vs Temperature
1.930
2.55
2.85
1.925
2.54
2.84
2.53
2.83
2.52
2.82
1.915
1.910
VOUT (V)
1.905
1.900
1.895
1.890
2.81
2.51
VOUT (V)
1.920
2.50
2.49
2.80
2.79
2.78
2.48
1.885
2.77
2.47
2.76
1.875
2.46
2.75
1.870
–55 –35 –15
2.45
–55 –35 –15
1.880
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G04
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G06
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G08
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G06
ERROR AMPLIFIER TRANSCONDUCTANCE (millimho)
Undervoltage Lockout Threshold
Voltage vs Temperature
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
VOUT (V)
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
3.23
–55 –35 –15
2.74
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G05
LTC1530-3.3 VOUT vs Temperature
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G03
LTC1530-2.5 VOUT vs Temperature
LTC1530-1.9 VOUT vs Temperature
VOUT (V)
LTC1530 VSENSE vs Temperature
100
Error Amplifier Transconductance
vs Temperature
2.8
2.6
2.4
2.2
2.0
1.8
1.6
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G09
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LTC1530
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TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Temperature
60
Maximum G1 Duty Cycle
vs Ambient Temperature
92
350
55
50
45
MAXIMUM G1 DUTY CYCLE (%)
340
OSCILLATOR FREQUENCY (kHz)
ERROR AMPLIFIER OPEN-LOOP DC GAIN (dB)
Error Amplifier Open-Loop Gain
vs Temperature
330
320
310
300
290
280
270
250
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G10
200
180
160
50
40
30
20
PVCC = 12V
70
65
60
55
50
45
40
35
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0
1
3
2
4
5
6
GATE CAPACITANCE (nF)
7
8
30
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G14
Shutdown Threshold Voltage
vs Temperature
1530 G15
Output Overcurrent Protection
250
Transient Response
3.0
PVCC = 12V
MEASURED AT
COMP PIN
2.5
OUTPUT VOLTAGE (V)
SHUTDOWN THRESHOLD VOLTAGE (mV)
7700pF
80
75
1530 G13
200
82
80
PVCC = 12V
TA = 25°C
60 GATE CAPACITANCE = C = C
G1
G2
10
140
120
–55 –35 –15
3300pF
5500pF
PVCC Shutdown Supply Current
vs Temperature
PVCC SHUTDOWN CURRENT (µA)
PVCC SUPPLY CURRENT (mA)
IMAX SINK CURRENT (µA)
220
2200pF
1530 G12
70
PVCC = 12V
G1, G2 ARE NOT SWITCHING
240
84
PVCC Supply Current
vs Gate Capacitance
300
260
86
G1, G2
CAPACITANCE
= 1000pF
1530 G11
IMAX Sink Current vs Temperature
280
88
PVCC = 12V
fOSC = 300kHz
THERMAL SHUTDOWN OCCURS
BEYOND THESE POINTS
78
–55 –35 –15 5 25 45 65 85 105 125
AMBIENT TEMPERATURE (°C)
260
40
–55 –35 –15
90
150
100
50
0
–55 –35 –15
50mV/DIV
PVCC = 12V
TA = 25°C
REFER TO
FIGURE 2
2.0
1.5
2A/DIV
1.0
SHORT-CIRCUIT
CURRENT
0.5
50µs/DIV
1530 G18
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
1530 G16
0
1
2
3 4 5 6 7 8
OUTPUT CURRENT (A)
9
10
1530 G17
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LTC1530
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PVCC (Pin 1): Power Supply for G1, G2 and Logic. PVCC
must connect to a potential of at least VIN + VGS(ON)Q1. If
VIN = 5V, generate PVCC using a simple charge pump
connected to the switching node between Q1 and Q2 (see
Figure 1) or connect PVCC to a 12V supply. Bypass PVCC
properly or erratic operation will result. A low ESR 10µF
capacitor or larger bypass capacitor along with a 0.1µF
surface mount ceramic capacitor in parallel is recommended from PVCC directly to GND to minimize switching
ripple. Switching ripple should be ≤100mV at the PVCC
pin.
GND (Pin 2): Power and Logic Ground. GND is connected
to the internal gate drive circuitry and the feedback circuitry. To obtain good output voltage regulation, use
proper ground techniques between the LTC1530 GND and
bottom-side FET source and the negative terminal of the
output capacitor. See the Applications Information section
for more details on PCB layout techniques.
VSENSE/VOUT (Pin 3): Feedback Voltage Pin. For the adjustable LTC1530, use an external resistor divider to set the
required output voltage. Connect the tap point of the
resistor divider network to VSENSE and the top of the
divider network to the output voltage. For fixed output
voltage versions of the LTC1530, the resistor divider is
internal and the top of the resistor divider network is
brought out to VOUT. In general, the resistor divider
network for each fixed output voltage version sinks approximately 30µA. Connect VOUT to the output voltage
either at the output capacitors or at the actual point of load.
VSENSE/VOUT is sensitive to switching noise injected into
the pin. Isolate high current switching traces from this pin
and its PCB trace.
COMP (Pin 4): External Compensation. The COMP pin is
connected to the error amplifier output and the input of the
PWM comparator. An RC + C network is typically used at
COMP to compensate the feedback loop for optimum
transient response. To shut down the LTC1530, pull this
pin below 0.1V with an open-collector or open-drain
transistor. Supply current is typically reduced to 45µA in
shutdown. An internal 4µA pullup ensures start-up.
IMAX (Pin 5): Current Limit Threshold. Current limit is set
by the voltage drop across an external resistor connected
between the drain of Q1 and IMAX. This voltage is compared with the voltage across the RDS(ON) of the high side
MOSFET. The LTC1530 contains a 200µA internal pulldown at IMAX to set current limit. This 200µA current
source has a positive temperature coefficient to provide
first order correction for the temperature coefficient of the
external N-channel MOSFET’s RDS(ON).
IFB (Pin 6): Current Limit Sense Pin. Connect IFB to the
switching node between Q1’s source and Q2’s drain. If IFB
drops below IMAX with G1 on, the LTC1530 enters current
limit. Under this condition, the internal soft-start capacitor
is discharged and COMP is pulled low slowly. Duty cycle
is reduced and output power is limited. The current limit
circuitry is only activated if PVCC ≥ 8V. This action eases
start-up considerations as PVCC is ramping up because
the MOSFET’s RDS(ON) can be significantly higher than
what is measured under normal operating conditions. The
current limit circuit is disabled by floating IMAX and shorting IFB to PVCC.
G2 (Pin 7): Gate Drive for the Low Side N-Channel MOSFET,
Q2. This output swings from PVCC to GND. It is always low
if G1 is high or if the output is disabled. To prevent
undershoot during a soft-start cycle, G2 is held low until
G1 first transitions high.
G1 (Pin 8): Gate Drive for the Topside N-Channel MOSFET,
Q1. This output swings from PVCC to GND. It is always low
if G2 is high or if the output is disabled.
1530fa
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LTC1530
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BLOCK DIAGRA
DISDR
LOGIC AND
THERMAL SHUTDOWN
INTERNAL
OSCILLATOR
1
PVCC
POWER DOWN
8 G1
–
ICOMP
PWM
7 G2
+
COMP 4
ISS
MSS
FIXED VOUT
R1
R2
1.9V
2.5V
2.8V
3.3V
23.4k
44.4k
54.9k
68.4k
43.2k
43.2k
43.2k
40.8k
CSS
gm = 2millimho
ERR
+
MIN
–
MAX
+
–
+
–
FB
VREF
VREF – 3%
VREF + 3%
–
6 IFB
+
5 IMAX
VSENSE
3
VOUT
R1
FB
R2
CC
3
FOR FIXED
VOLTAGE
VERSIONS
IMAX
+
HCL
MONO
MHCL
VREF
VREF – 3%
VREF + 3%
VREF /2
VREF /2
LVC
–
VREF
1530 BD
TEST CIRCUITS
VIN
5V
+
750Ω
IMAX
C1
100pF
RC
8.2k
CC
0.01µF
0.1µF
PVCC
G1
GND
+
PVCC
12V
10µF
100Ω
IFB
COMP
LTC1530-2.5
G2
CIN***
1200µF
×2
+
0.1µF
10µF
PVCC
Q1
LO*
Si4410DY 2.4µH
Q2
Si4410DY
VOUT
PVCC
12V
+
CO**
330µF
×8
VOUT
2.5V
6A
1530 F02
COMP
IFB
G1
NC
COMP
IMAX
LTC1530
G2
NC
VSENSE/VOUT
VFB
GND
*SUMIDA CDRH127-2R4
**AVX TPSE337M006R0100
***SANYO 10MV1200GX
Figure 2
NC
1530 F03
Figure 3
1530fa
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LTC1530
TEST CIRCUITS
PVCC
12V
0.1µF
90%
10µF
50%
PVCC
G1
IFB
COMP
VOUT
10%
G1 RISE/FALL
G2
90%
50%
10%
COMP
3300pF
LTC1530
COMP
tf
tr
+
tNOL
50%
G2 RISE/FALL
tNOL
50%
G1
3300pF
GND
t SS
1530 F04b
1530 F04a
Figure 4
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APPLICATIO S I FOR ATIO
OVERVIEW
The LTC1530 is a voltage feedback, synchronous switching regulator controller (see Block Diagram) designed for
use in high power, low voltage step-down (buck) converters. It includes an on-chip soft-start capacitor, a PWM
generator, a precision reference trimmed to ±1%, two high
power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching
regulator circuit running at 300kHz.
The LTC1530 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. If the current comparator, CC,
detects an overcurrent condition, the duty cycle is reduced
by discharging the internal soft-start capacitor through a
voltage-controlled current source. Under severe overloads or output short-circuit conditions, the soft-start
capacitor is pulled to ground and a start-up cycle is
initiated. If the short circuit or overload persists, the chip
repeats soft-start cycles and prevents damage to external
components.
THEORY OF OPERATION
Primary Feedback Loop
The LTC1530 compares the output voltage with the internal reference at the error amplifier inputs. The error
amplifier outputs an error signal to the PWM comparator.
This signal is compared to the fixed frequency oscillator
sawtooth waveform to generate the PWM signal. The
PWM signal drives the external MOSFETs at the G1 and G2
pins. The resulting chopped waveform is filtered by LO and
COUT which closes the loop. Loop frequency compensation is typically accomplished with an external RC + C
network at the COMP pin, which is the output node of the
transconductance error amplifier.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the error
amplifier cannot respond quickly enough. MIN compares
the feedback signal to a voltage 3% below the internal
reference. If the signal is below the comparator threshold,
the MIN comparator overrides the error amplifier and
forces the loop to maximum duty cycle, typically 86%.
Similarly, the MAX comparator forces the output to 0%
duty cycle if the feedback signal is greater than 3% above
the internal reference. To prevent these two comparators
from triggering due to noise, the MIN and MAX comparators’ response times are deliberately delayed by two to
three microseconds. These comparators help prevent
extreme output perturbations with fast output load current
transients, while allowing the main feedback loop to be
optimally compensated for stability.
Thermal Shutdown
The LTC1530 has a thermal protection circuit that disables
both internal gate drivers if activated. G1 and G2 are held
low and the LTC1530 supply current drops to about 1mA.
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LTC1530
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APPLICATIO S I FOR ATIO
Typically, thermal shutdown is activated if the LTC1530’s
junction temperature exceeds 150°C. G1 and G2 resume
switching when the junction temperature drops below
100°C.
Soft-Start and Current Limit
Unlike other PWM parts, the LTC1530 includes an on-chip
soft-start capacitor that is used during start-up and current limit operation. On power-up, an internal 4µA pull-up
at COMP brings the LTC1530 out of shutdown mode. An
internal current source then charges the internal CSS
capacitor. The COMP pin is clamped to one VGS above the
voltage on CSS during start-up. This prevents the error
amplifier from forcing the loop to maximum duty cycle.
The LTC1530 operates at low duty cycle as the COMP pin
voltage increases above about 2.4V. The slew rate of the
soft-start capacitor is typically 0.4V/ms. As the voltage on
CSS continues to increase, MSS eventually turns off and the
error amplifier regulates the output. The MIN comparator
is disabled if soft-start is active to prevent an override of
the soft-start function.
The LTC1530 includes another feedback loop to control
operation in current limit. Before each falling edge of G1,
the current comparator, CC, samples and holds the voltage drop across external MOSFET Q1 with the LTC1530’s
IFB pin. CC compares the voltage at IFB to the voltage at the
IMAX pin. As peak current rises, the voltage across the
RDS(ON) of Q1 increases. If the voltage at IFB drops below
IMAX, indicating that Q1’s drain current has exceeded the
maximum desired level, CC pulls current out of CSS. Duty
cycle decreases and the output current is controlled. The
CC comparator pulls current out of CSS in proportion to the
voltage difference between IFB and IMAX. Under minor
overload conditions, the voltage at CSS falls gradually,
creating a time delay before current limit activates. Very
short, mild overloads may not affect the output voltage at
all. Significant overload conditions allow the voltage on
CSS to reach a steady state and the output remains at a
reduced voltage until the overload is removed. Serious
overloads generate a large overdrive and allow CC to pull
the CSS voltage down quickly, thus preventing damage to
the external components.
By using the RDS(ON) of Q1 to measure output current, the
current limit circuit eliminates the sense resistor that
would otherwise be required. This minimizes the number
of components in the high current power path. The current
limit circuitry is not designed to be highly accurate. It is
primarily meant to prevent damage to the power supply
circuitry during fault conditions. The exact current level
where current limiting takes effect will vary from unit to
unit as the RDS(ON) of Q1 varies.
Figure 5a illustrates the basic connections for the current
limit circuitry. For a given current limit level, the external
resistor from IMAX to VIN is determined by:
RIMAX =
(ILMAX)RDS(ON)Q1
IIMAX
where,
I
ILMAX = ILOAD + RIPPLE
2
ILOAD = Maximum load current
IRIPPLE = Inductor ripple current
=
(VIN − VOUT )(VOUT )
(fOSC)(LO)(VIN)
fOSC = LTC1530 oscillator frequency = 300kHz
LO = Inductor value
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX = 200µA sink current
VIN
+
LTC1530
IMAX
CIN
RIMAX
+
G1
200µA
CC
IFB
–
Q1
LO
20Ω
+
G2
Q2
VOUT
COUT
1530 F05
Figure 5a. Current Limit Setting (Use Kelvin-Sense
Connections Directly at the Drain and Source of Q1)
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For a given application, the input and output requirements
are known and determine the main inductor and output
capacitor values. These values establish the transient load
recovery time. In general, a low value inductor combined
with high value output capacitance has a short transient
load recovery time at the expense of higher inductor ripple
and start-up current (IRIPPLE and IST). However, if a small
inductor and large value output capacitors are chosen, the
value of RIMAX obtained from Figure 5b may be too small
to allow proper regulator start-up.
During start-up, if IST is higher than the current limit
threshold set by the RIMAX resistor, the LTC1530 current
limit comparator turns on. This comparator then limits
input charging current by reducing duty cycle. During this
time, if VOUT doesn’t increase above one-half of the rated
value, the LTC1530 hard current limit circuit turns on. This
circuit forces the LTC1530 to repeat a soft-start cycle and
the power supply fails to start. If VOUT increases above
one-half of the rated value, the power supply output may
start-up properly depending on whether the limited input
current charges the output capacitor and prevents hard
current limit action.
5500
MINIMUM REQUIRED RIMAX (Ω)
RIMAX ≥ 500Ω
ILMAX = ILOAD + IRIPPLE /2
4500
0.04Ω
Q1 RDS(ON) = 0.05Ω
3500
0.03Ω
2500
0.02Ω
1500
0.01Ω
500
0
2
4
6
8 10 12 14 16 18 20
ILMAX (A)
1530 F05b
Figure 5b. Minimum Required RIMAX vs ILMAX
25
TA = 25°C
VIN = 5V
ILOAD = 0A
20
START-UP IST (A)
Figure 5b plots the minimum required RIMAX resistor (kΩ)
versus the maximum operating load current (ILMAX =
ILOAD + IRIPPLE/2) as a function of Q1’s RDS(ON). Note that
during an intial power-up sequence (VOUT = 0V), the
inductor’s start-up current IST is much higher than the
steady-state condition, ILMAX. The difference between IST
and ILMAX is affected by the input power supply slew rate,
the input and output voltages, the LTC1530 soft-start slew
rate, the maximum duty cycle and the inductor and output
capacitor values.
15
L = 1.2µH
10
L = 4.7µH
5
L = 2.4µH
0
0
2
4
6
8
10
OUTPUT CAPACITANCE (mF)
12
1530 F06a
Figure 6a. Start-Up IST vs Output Capacitance
30
TA = 25°C
VIN = 5V
ILOAD = 10A
25
Figures 6a and 6b plot the start-up IST vs output capacitance and inductance for unloaded and loaded conditions
with the current limit circuit disabled. Figures 6a and 6b
are provided as examples. Actual IST under start-up conditions must be measured for any application circuit so
that RIMAX can be properly chosen.
START-UP IST (A)
L = 2.4µH
Therefore, select RIMAX with the start-up current (IST) in
mind. Choosing RIMAX to set the current comparator
threshold above IST ensures proper power supply start-up
as well as recovery from an output fault condition.
20
L = 1.2µH
15
L = 4.7µH
10
5
0
0
2
10
4
6
8
OUTPUT CAPACITANCE (mF)
12
1530 F06b
Figure 6b. Start-Up IST vs Output Capacitance
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In order for the current limit circuit to operate properly and
to obtain a reasonably accurate current limit threshold, the
IMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. A 0.1µF decoupling capacitor can also be
connected across RIMAX to filter switching noise. In addition, LTC recommends that the voltage drop across the
RIMAX resistor be set to ≥100mV. Otherwise, noise spikes
or ringing at Q1’s source can cause the actual current limit
to be greater than the desired current limit set point.
MOSFET Gate Drive
The PVCC supply must be greater than the input supply
voltage, VIN, by at least one power MOSFET VGS(ON) for
efficient operation. This higher voltage can be supplied
with a separate supply, or it can be generated using a
simple charge pump as shown in Figure 7. The 86%
maximum duty cycle ensures sufficient off-time to refresh
the charge pump during each cycle.
As PVCC is powered up from 0V, the LTC1530 undervoltage lockout circuit prevents G1 and G2 from pulling high
until PVCC reaches about 3.5V. To prevent Q1’s high
RDS(ON) from triggering the current limit comparator while
PVCC is slewing, the current limit circuit is disabled until
PVCC is≥ 8V. In addition, on start-up or recovery from
thermal shutdown, the driver logic is designed to hold G2
low until G1 first goes high.
OPTIONAL FOR
VIN > 6.5V
13V
1N5243B
MBR0530T1 MBR0530T1 VIN
+
+
CIN
10µF
PVCC
0.22µF
G1
Q1
LO
+
G2
Q2
LTC1530
Figure 7. Doubling Charge Pump
VOUT
CO
1530 F07
Power MOSFETs
Two N-channel power MOSFETs are required for synchronous LTC1530 circuits. They should be selected based
primarily on threshold voltage and on-resistance considerations. Thermal dissipation is often a secondary concern in high efficiency designs. The required MOSFET
threshold should be determined based on the available
power supply voltages and/or the complexity of the gate
drive charge pump scheme. In 5V input designs where a
12V supply is used to power PVCC, standard MOSFETs
with RDS(ON) specified at VGS = 5V or 6V can be used with
good results. The current drawn from the 12V supply
varies with the MOSFETs used and the LTC1530’s operating frequency, but is generally less than 50mA.
LTC1530 applications that use a 5V VIN voltage and a
doubling charge pump to generate PVCC do not provide
enough gate drive voltage to fully enhance standard
power MOSFETs. Under this condition, the effective
MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. In addition,
power supply start-up problems can occur with standard
power MOSFETs. These start-up problems can occur for
two reasons. First, if the MOSFET is not fully enhanced,
the higher effective RDS(ON) causes the LTC1530 to activate current limit at a much lower level than the desired
trip point. Second, standard MOSFETs have higher GATE
threshold voltages than logic level MOSFETs, thereby
increasing the PVCC voltage required to turn them on. A
MOSFET whose RDS(ON) is rated at VGS = 4.5V does not
necessarily have a logic level MOSFET GATE threshold
voltage. Logic level FETs are the recommended choice for
5V-only systems. Logic level FETs can be fully enhanced
with a doubler charge pump and will operate at maximum
efficiency. Note that doubler charge pump designs running from supplies higher than 6.5V should include a
Zener diode clamp at PVCC to prevent transients from
exceeding the absolute maximum rating of the pin.
After the MOSFET threshold voltage is selected, choose
the RDS(ON) based on the input voltage, the output voltage,
allowable power dissipation and maximum output current. In a typical LTC1530 buck converter circuit, operating in continuous mode, the average inductor current is
equal to the output load current. This current flows through
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either Q1 or Q2 with the power dissipation split up according to the duty cycle:
V
DC(Q1) = OUT
VIN
(
VIN − VOUT
V
DC(Q2) = 1 − OUT =
VIN
VIN
)
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
PMAX( Q1)
RDS( ON)Q1 =
[DC(Q1)](IMAX2 )
( VIN )[PMAX( Q1) ]
=
( VOUT)(IMAX2 )
In most LTC1530 applications, RDS(ON) is used as the
current sensing element. MOSFET RDS(ON) has a positive
temperature coefficient. Therefore, the LTC1530 IMAX sink
current is designed with a positive 3300ppm/°C temperature coefficient. The positive tempco of IMAX provides first
order correction for current limit vs temperature. Therefore, current limit does not have to be set to an increased
level at room temperature to guarantee a desired output
current at elevated temperatures.
PMAX( Q2)
RDS( ON)Q2 =
[DC(Q2)](IMAX2 )
( VIN )[PMAX( Q2) ]
=
(VIN − VOUT)(IMAX2 )
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A high efficiency
buck converter designed for the Pentium II with 5V input
and a 2.8V, 11.2A output might allow no more than 4%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a PMAX
value of:
(2.8)(11.2A/0.9)(0.04) = 1.39W per FET
and a required RDS(ON) of:
RDS(ON)Q1 =
RDS(ON)Q2 =
(
5V 1.39W
)
2.8V 11.2A2
(
= 0.020Ω
5V 1.39W
(
)
)
5V − 2.8V 11.2A2
Note that while the required RDS(ON) values suggest large
MOSFETs, the power dissipation numbers are only 1.39W
per device or less — large TO-220 packages and heat
sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY or International Rectifier
IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in DPAK) are small footprint surface mount devices with RDS(ON) values below 0.03Ω at 5V
of VGS that work well in LTC1530 circuits. With higher
output voltages, the RDS(ON) of Q1 may need to be significantly lower than that for Q2. These conditions can often
be met by paralleling two MOSFETs for Q1 and using a
single device for Q2. Using a higher PMAX value in the
RDS(ON) calculations generally decreases the MOSFET
cost and the circuit efficiency and increases the MOSFET
heat sink requirements.
= 0.025Ω
Table 1 highlights a variety of power MOSFETs that are
suitable for use in LTC1530 applications.
Inductor Selection
The inductor is often the largest component in an LTC1530
design and must be chosen carefully. Choose the inductor
value and type based on output slew rate requirements
and expected peak current. The required output slew rate
primarily controls the inductor value. The maximum rate
of rise of inductor current is set by the inductor’s value, the
input-to-output voltage differential and the LTC1530’s
maximum duty cycle. In a typical 5V input, 2.8V output
application, the maximum rise time will be:
V − V 1.85
DCMAX IN OUT =
L
L
A
µs
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Table 1. Recommended MOSFETs for LTC1530 Applications
PART NO.
PACKAGE
RDS(ON)
AT 25°C
(Ω)
Siliconix
SUD50N03-10
TO-252
0.019
15A at 25°C
10A at 100°C
3200
1.8
175
Siliconix
Si4410DY
SO-8
0.020
10A at 25°C
8A at 75°C
2700
—
150
MTD20N03HDL
DPAK
0.035
20A at 25°C
16A at 100°C
880
1.67
150
FDS6680
SO-8
0.01
11.5A at 25°C
2070
25
150
MTB75N03HDL*
D2PAK
0.0075
75A at 25°C
59A at 100°C
4025
1.0
150
IR
IRL3103S
D2PAK
0.014
56A at 25°C
40A at 100°C
1600
1.8
175
IR
IRLZ44
TO-220
0.028
50A at 25°C
36A at 100°C
3300
1.0
175
Fuji
2SK1388
TO-220
0.037
35A at 25°C
1750
2.08
150
MANUFACTURER
ON Semiconductor
Fairchild
ON Semiconductor
RATED CURRENT
(A)
TYPICAL INPUT
CAPACITANCE
Ciss (pF)
θJC
(°C/W)
TJMAX
(°C)
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
*Users must consider the power dissipation and thermal effects in the LTC1530 if driving external MOSFETs with high values of input capacitance.
Refer to the PVCC Supply Current vs GATE Capacitance in the Typical Performance Characteristics section.
where L is the inductor value in µH. With proper frequency
compensation, the combination of the inductor and output
capacitor values determine the transient recovery time. In
general, a smaller value inductor improves transient
response at the expense of ripple and inductor core
saturation rating. A 2µH inductor has a 0.9A/µs rise time
in this application, resulting in a 5.5µs delay in responding
to a 5A load current step. During this 5.5µs, the difference
between the inductor current and the output current is
made up by the output capacitor. This action causes a
temporary voltage droop at the output. To minimize this
effect, the inductor value should usually be in the 1µH to
5µH range for most 5V input LTC1530 circuits. Different
combinations of input and output voltages and expected
loads may require different values.
Once the required inductor value is selected, choose the
inductor core type based on peak current and efficiency
requirements. Peak current in the inductor is equal to the
maximum output load current plus half of the peak-topeak inductor ripple current. Inductor ripple current is set
by the inductor’s value, the input voltage, the output
voltage and the operating frequency. If the efficiency is
high, ripple current is approximately equal to:
IRIPPLE =
(VIN − VOUT)(VOUT)
(fOSC)(LO)(VIN)
where
fOSC = LTC1530 oscillator frequency
LO = Inductor value
Solving this equation for a typical 5V to 2.8V application
with a 2µH inductor, ripple current is:
(2.2V)(0.56) = 2AP-P
(300kHz)(2µH)
Peak inductor current at 11.2A load:
11.2A +
2A
= 12.2A
2
The ripple current should generally fall between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
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circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductors with gradual saturation characteristics (example:
powdered iron) are often the best choice.
Input and Output Capacitors
A typical LTC1530 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC1530
draws square waves of current from the input supply at the
switching frequency. The peak current value is equal to the
output load current plus 1/2 the peak-to-peak ripple current. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours (3 months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s specification is recommended to extend the useful life of the
circuit. Lower operating temperature has the largest effect
on capacitor longevity.
The output capacitor in a buck converter under steady
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC1530 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. An 11A load step with a 0.05Ω ESR output
capacitor results in a 550mV output voltage shift; this is
19.6% of the output voltage for a 2.8V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capacitor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1530 applications. OS-CON
electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. AVX TPS series surface mount
devices are popular surge tested tantalum capacitors that
work well in LTC1530 applications.
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical
LTC1530 application might exhibit 5A input ripple current. Sanyo OS-CON capacitors, part number 10SA220M
(220µF/10V), feature 2.3A allowable ripple current at
85°C; three in parallel at the input (to withstand the input
ripple current) meet the above requirements. Similarly,
AVX TPSE337M006R0100 (330µF/6V) capacitors have a
rated maximum ESR of 0.1Ω; seven in parallel lower the
net output capacitor ESR to 0.014Ω. For low cost
applications, the Sanyo MV-GX capacitor series can be
used with acceptable performance.
Feedback Loop Compensation
The LTC1530 voltage feedback loop is compensated at the
COMP pin, which is the output node of the gm error
amplifier. The feedback loop is generally compensated
with an RC + C network from COMP to GND as shown in
Figure 8a.
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier compensation network. The inductor and the output capacitor
create a double pole at the frequency:
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fLC =
VOUT
1
(
2π LO COUT
)
3
LTC1530
COMP
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
1
(2π)(ESR)(COUT )
1
(2π)(RC)(CC)
and fP =
C1
BG
CC
1530 F08a
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
fZ =
RC
1
(2π)(RC)(C1)
Figure 8a. Compensation Pin Hook-Up
LOOP GAIN
fESR =
–
ERR
+
4
fSW = LTC1530 SWITCHING FREQUENCY
fCO = CLOSED-LOOP CROSSOVER FREQUENCY
fZ
–20dB/DECADE
respectively. Figure 8b shows the Bode plot of the overall
transfer function.
The compensation values used in this design are based on
the following criteria, fSW = 12fCO, fZ = fLC, fP = 5fCO. At the
closed-loop frequency fCO, the attenuation due to the LC
filter and the input resistor divider is compensated by the
gain of the PWM modulator and the gain of the error
amplifier (gmERR)(RC).
Although a mathematical approach to frequency compensation can be used, the added complication of input and/
or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage, load current
variations and frequency of operation all suggest a more
practical empirical method. This can be done by injecting
a transient current at the load and using an RC network box
to iterate toward the final compensation values or by
obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.
Table 2 shows the suggested compensation components
for 5V input applications based on the inductor and output
capacitor values. The values were calculated using multiple paralleled 330µF AVX TPS series surface mount
tantalum capacitors for the output capacitor. The optimum component values might deviate from the suggested
values slightly because of board layout and operating
condition differences.
fP
fLC
fESR
FREQUENCY
fCO
1530 F08b
Figure 8b. Bode Plot of the LTC1530 Overall
Transfer Function
Table 2. Suggested Compensation Network for a 5V Input
Application Using Multiple Paralleled 330µF AVX TPS Output
Capacitors for 2.5V Output
LO (µH)
CO (µF)
RC (kΩ)
CC (µF)
C1 (pF)
1
990
1.3
0.022
1000
1
1980
2.7
0.022
470
1
4950
6.8
0.01
220
2.7
990
3.6
0.022
330
2.7
1980
7.5
0.01
220
2.7
4950
18
0.01
68
5.6
990
7.5
0.01
220
5.6
1980
15
0.01
100
5.6
4950
36
0.0047
47
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple paralleled 1500µF Sanyo MV-GX capacitors for the output capacitor, Table 3 shows the suggested
compensation components for 5V input applications based
on the inductor and output capacitor values.
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Table 3. Suggested Compensation Network for a 5V Input
Application Using Multiple Paralleled 1500µF SANYO MV-GX
Output Capacitors for 2.5V Output
LO (µH)
CO (µF)
RC (kΩ)
CC (µF)
C1 (pF)
1
4500
3
0.022
470
1
6000
4
0.022
330
1
9000
6
0.022
220
2.7
4500
8.2
0.022
150
2.7
6000
11
0.01
100
2.7
9000
16
0.01
100
5.6
4500
16
0.01
100
5.6
6000
22
0.01
68
5.6
9000
33
0.01
47
Note: For different values of VOUT, multiply the RC value by VOUT/2.5 and
multiply the CC and C1 values by 2.5/VOUT. This maintains the same
crossover frequency for the closed-loop transfer function.
Thermal Considerations
Limit the LTC1530’s junction temperature to less than
125°C. The LTC1530’s SO-8 package is rated at 130°C/W
and care must be taken to ensure that the worst-case input
voltage and gate drive load current requirements do not
cause excessive die temperatures. Short-circuit or fault
conditions may activate the internal thermal shutdown
circuit.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board (PCB), the
following checklist should be used to ensure proper
operation of the LTC1530. These items are illustrated
graphically in the layout diagram of Figure 9. The thicker
lines show the high current power paths. Note that at 10A
current levels or above, current density in the PCB itself is
a serious concern. Traces carrying high current should be
as wide as possible. For example, a PCB fabricated with
2oz copper requires a minimum trace width of 0.15" to
carry 10A, and only if trace length is kept short.
1. In general, begin the layout with the location of the
power devices. Orient the power circuitry so that a
clean power flow path is achieved. Maximize conductor widths but minimize conductor lengths. Keep high
current connections on one side of the PCB if possible.
If not, minimize the use of vias and keep the current
density in the vias to
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