LTC1588

LTC1588/LTC1589/LTC1592 12-/14-/16-Bit SoftSpan DACs with Programmable Output Range FEATURES s DESCRIPTIO s s s s s Six Programmable Output Ranges Unipolar Mode: 0V to 5V, 0V to 10V Bipolar Mode: ± 5V, ±10V, ± 2.5V, – 2.5V to 7.5V 1LSB Max DNL and INL Over the Industrial Temperature Range Glitch Impulse < 2nV-s 16-Lead SSOP Package Power-On Reset to 0V Asynchronous Clear to 0V for All Ranges The LTC®1588/LTC1589/LTC1592 are serial input 12-/14/16-bit multiplying current output DACs that operates from a single 5V supply. These SoftSpanTM DACs can be software-programmed for either unipolar or bipolar mode through a 3-wire SPI interface. In either mode, the voltage output range can also be software-programmed. Two output ranges in unipolar mode and four output ranges in bipolar mode are available. INL and DNL are accurate to 1LSB over the industrial temperature range in both unipolar and bipolar modes. True 16-bit 4-quadrant multiplication is achieved with on-chip four quadrant multiplication resistors. The LTC1588/LTC1589/LTC1592 are available in a 16-lead SSOP package. These devices include an internal deglitcher circuit that reduces the glitch impulse to less than 2nV-s (typ). The asynchronous clear pin resets the LTC1588/LTC1589/ LTC1592 to 0V in unipolar or bipolar mode. , LTC and LT are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. APPLICATIO S s s s s s Process Control and Industrial Automation Precision Instrumentation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment TYPICAL APPLICATIO VREF 5V 5 Programmable Output Range 16-Bit SoftSpan DAC LTC1592 Integral Nonlinearity 7 INTEGRAL NONLINEARITY (LSB) + 1/2 LT®1469 6 – C2 150pF 2 R1 R1 5V 9 0.1µF 14 13 12 11 10 CLR CS/LD SCK SDI SDO VCC 1 RCOM R2 16 15 3 4 C1 15pF 15V 8 0.1µF R2 REF ROFS RFB 16-BIT DAC WITH SPAN ADJUST IOUT2 6 AGND LTC1592 GND 7 8 3 1588992 TA01 + – IOUT1 5 2 1/2 LT1469 4 –15V 1 VOUT 0.1µF U 1.0 VREF = 5V 0.8 ALL OUTPUT RANGES 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 TA02 U U 1588992fa 1 LTC1588/LTC1589/LTC1592 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RCOM R1 ROFS RFB IOUT1 IOUT2 AGND GND 1 2 3 4 5 6 7 8 G PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 125°C/ W 16 R2 15 REF 14 CLR 13 CS/LD 12 SCK 11 SDI 10 SDO 9 VCC VCC to AGND, GND ......................................– 0.3V to 7V AGND to GND .............................. – 0.3V to (VCC + 0.3V) GND to AGND .............................. – 0.3V to (VCC + 0.3V) RCOM to AGND, GND ................................ – 0.3V to 12V REF to AGND, GND ................................................ ±15V ROFS, RFB, R1, R2 to AGND, GND .......................... ±15V Digital Inputs to AGND, GND ....... – 0.3V to (VCC + 0.3V) IOUT1, IOUT2 to AGND, GND .......... – 0.3V to (VCC + 0.3V) Maximum Junction Temperature .......................... 150°C Operating Temperature Range LTC1588C/LTC1589C/LTC1592C ........... 0°C to 70°C LTC1588I/LTC1589I/LTC1592I ........... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1588CG LTC1588IG LTC1589CG LTC1589IG LTC1592ACG LTC1592AIG LTC1592BCG LTC1592BIG Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. SYMBOL PARAMETER Accuracy Resolution INL DNL GE BZE Integral Nonlinearity Differential Nonlinearity Gain Error (Notes 2, 3) Guaranteed Monotonic (Note 3) All Output Ranges (Note 3) TA = 25°C TMIN to TMAX TMIN to TMAX TA = 25°C TMIN to TMAX TA = 25°C TMIN to TMAX q q q CONDITIONS TEMPERATURE LTC1588 LTC1589 LTC1592B LTC1592A MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 12 ±1 ±1 ±1 –0.20 ± 3 –0.22 ± 3 ±1 ±1 3 ±5 ± 15 ±0.01±0.15 14 ±1 ±1 ±1 –1.0 ± 4 –1.3 ± 6 ±2.5 ±4.0 3 ±5 ± 15 ±0.05 ±0.5 16 ±2 ±2 ±1 –3 ±16 –4 ± 24 ±10 ±16 3 ±5 ± 15 ±2 1 16 ±0.3 ± 1 ±0.4 ± 1 ±0.2 ± 1 –2 ±16 –3 ±16 ±5 ±8 3 ±5 ± 15 ±0.2 ± 2 UNITS Bits LSB LSB LSB LSB LSB LSB LSB ppm/°C nA nA LSB/V q q q Bipolar Zero Error All Bipolar Ranges (Note 3) Gain Temperature ∆Gain/∆Temperature Coefficient (Note 4) ILKG PSRR IOUT1 Leakage Current Power Supply Rejection (Note 5) VCC = 5V ± 10% TA = 25°C TMIN to TMAX q q 1588992fa 2 U W U U WW W LTC1588/LTC1589/LTC1592 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Reference Input RREF R1, R2 ROFS RFB DAC Input Resistance (Unipolar) R1, R2 Resistance Offset Resistance (Bipolar) Feedback Resistance (Unipolar) Feedback Resistance (Bipolar) (Note 6) The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. CONDITIONS q q q q q q q q q MIN 5 10 10 20 5 10 10 20 5 TYP 7 14 14 28 7 14 14 28 7 160 100 2 2 1 – 108 11 MAX 10 20 20 40 10 20 20 40 10 UNITS kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ pF pF µs nV-s mVP-P dB nV/√Hz V (Notes 6, 11) ± 5V, ±10V, ±2.5V Ranges –2.5V to 7.5V Range 5V Range 10V Range ± 5V and –2.5V to 7.5V Ranges ± 10V Range ± 2.5V Range DAC Load All 1s DAC Load All 0s 5V Range, 0V to 5V Step with LT1468 (Note 7) (Note 10) VREF = ±10V, 10kHz Sine Wave (Note 8) Multiplying (Note 9) At IOUT1 Analog Outputs (Note 4) COUT Output Capacitance (IOUT1) AC Performance (Note 4) Settling Time Midscale Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density Digital Inputs VIH VIL IIN CIN VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Digital Output High Voltage Digital Output Low Voltage Serial Input Valid to SCK Setup Time Serial Input Valid to SCK Hold Time SCK Pulse Width High SCK Pulse Width Low CS/LD Pulse High Width LSB SCK High to CS/LD High CS/LD Low to SCK High SCK to SDO Propagation Delay SCK Low to CS/LD Low Clear Pulse Low Width CS/LD High to SCK Positive Edge SCK Frequency Non-Daisy Chain (Note 12) Daisy Chain (Note 13) CLOAD = 50pF VIN = 0V (Note 4) IOH = 200µA IOL = 1.6mA q q q q 2.4 0.8 ±1 8 4 0.4 60 0 35 35 360 35 0 20 35 100 35 14.2 4.1 180 V µA pF V V ns ns ns ns ns ns ns ns ns ns ns MHz MHz Digital Outputs q q Timing Characteristics q q q q q q q q q q q q 1588992fa 3 LTC1588/LTC1589/LTC1592 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Power Supply VCC ICC Supply Voltage Supply Current, VCC CONDITIONS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. MIN q TYP 5 MAX 5.5 10 UNITS V µA 4.5 Digital Inputs = 0V or VCC q Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: ± 1LSB = ± 0.0015% of full scale = ±15.3ppm of full scale (LTC1592). ± 1LSB = ±0.006% of full scale = ±61.2ppm of full scale (LTC1589). ± 1LSB = 0.024% of full scale = ± 244.8ppm of full scale (LTC1588). Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: IOUT1 with DAC register loaded to all 0s. Note 6: Typical temperature coefficient is 100ppm/°C. Note 7: To 0.0015% for a full-scale change, measured from the falling edge of LD for the LTC1592 only. Note 8: REF = 6VRMS at 1kHz. DAC register loaded with all 1s. Output amplifier = LT1468. Note 9: Calculation from en = √4kTRB where: k = Boltzmann constant (1.38E-23 J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz). Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191 to 8192 for the LTC1589, 2047 to 2048 for the LTC1588. Note 11: R1 and R2 are measured between R1 and RCOM, R2 and RCOM. Note 12: If a continuous clock is used with data changing on the rising edge of SCK, setup and hold time (t1, t2) will limit the maximum clock frequency. If data changes on the falling edge of SCK then the setup time will limit the maximum clock frequency to 8MHz (continuous 50% duty cycle clock). Note 13: SDO propagation delay and SDI setup time (t8, t1) limit the maximum clock frequency for daisy chaining. TYPICAL PERFOR A CE CHARACTERISTICS (LTC1588/LTC1589/LTC1592) Midscale Glitch Impulse 40 30 USING AN LT1468 CFEEDBACK = 30pF VREF = 10V SUPPLY CURRENT (mA) OUTPUT VOLTAGE (mV) LOGIC THRESHOLD (V) 20 10 0 –10 –20 – 30 – 40 1nV-s TYPICAL 0 0.2 0.4 0.6 TIME (µs) 4 UW 0.8 1588992 G03 Supply Current vs Input Voltage 5 Logic Threshold vs Supply Voltage 3.0 4 VCC = 5V ALL DIGITAL INPUTS TIED TOGETHER 2.5 2.0 1.5 1.0 0.5 0 3 2 1 0 1.0 0 1 3 2 INPUT VOLTAGE (V) 4 5 1588992 G09 0 1 5 2 3 4 SUPPLY VOLTAGE (V) 6 7 1588992 G10 1588992fa LTC1588/LTC1589/LTC1592 TYPICAL PERFOR A CE CHARACTERISTICS (LTC1588) Integral Nonlinearity 1.0 1.0 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 800 2400 3200 1600 DIGITAL INPUT CODE 4095 DIFFERENTIAL NONLINEARITY (LSB) 0.8 INTEGRAL NONLINEARITY (LSB) (LTC1589) Integral Nonlinearity 1.0 1.0 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 8224 12336 4112 DIGITAL INPUT CODE 16383 1588992 G13 DIFFERENTIAL NONLINEARITY (LSB) 0.8 INTEGRAL NONLINEARITY (LSB) (LTC1592) Integral Nonlinearity (INL) 1.0 DIFFERENTIAL NONLINEARITY (LSB) 0.8 INTEGRAL NONLINEARITY (LSB) 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 G01 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 G02 INTEGRAL NONLINEARITY (LSB) UW Differential Nonlinearity 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 800 2400 3200 1600 DIGITAL INPUT CODE 4095 1588992 G11 1588992 G12 Differential Nonlinearity 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 8224 12336 4112 DIGITAL INPUT CODE 16383 1588992 G14 Differential Nonlinearity (DNL) 1.0 0.8 1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 Integral Nonlinearity vs Reference Voltage in Unipolar Mode –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 1588992 G05 1588992fa 5 LTC1588/LTC1589/LTC1592 TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity vs Reference Voltage in Bipolar Mode 1.0 DIFFERENTIAL NONLINEARITY (LSB) 0.8 INTEGRAL NONLINEARITY (LSB) 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 Differential Nonlinearity vs Reference Voltage in Bipolar Mode 1.0 DIFFERENTIAL NONLINEARITY (LSB) 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 PI FU CTIO S RCOM (Pin 1): Center Tap Point of the Two Bipolar Resistors R1 and R2. Normally tied to the inverting input of an external amplifier. When these resistors are not used, connect this pin to ground. The absolute maximum voltage range on this pin is – 0.3V to 12V. R1 (Pin 2): Bipolar Resistor R1. The main reference input VREF, typically 5V. Accepts up to ±15V. Normally tied to ROFS (Pin 3) and the reference input voltage VREF (5V). When not used connect this pin to ground. ROFS (Pin 3): Bipolar Offset Network. This pin provides the offset of the output voltage range for bipolar modes. Accepts up to ±15V. Normally tied to R1 and the reference input voltage VREF (5V). Alternatively, this pin may be driven from a different voltage than VREF. RFB (Pin 4): Feedback Network. Normally tied to the output of the current to voltage converter op amp. Range limited to ±15V. 1588992fa 6 UW (LTC1592) Differential Nonlinearity vs Reference Voltage in Unipolar Mode 1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 1588992 G06 1588992 G07 Full-Scale Settling Waveform LD PULSE 5V/DIV GATED SETTLING WAVEFORM 500µV/DIV 500ns/DIV USING LT1468 OP AMP CFEEDBACK = 20pF 0V TO 10V STEP 1592 G04 1588992 G08 U U U LTC1588/LTC1589/LTC1592 PI FU CTIO S IOUT1 (Pin 5): True DAC Current Output. Tied to the inverting input of the current-to-voltage op amp. IOUT2 (Pin 6): Complement of DAC Current Output. Normally tied to AGND pin. AGND (Pin 7): Analog Ground. Tie to the system’s analog ground plane. GND (Pin 8): Ground. Tie to the system’s analog ground plane. VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V. Requires a 0.1µF bypass capacitor to ground. SDO (Pin 10): Serial Data Output. Data at this pin is shifted out on the rising edge of SCK. SDI (Pin 11): Serial Data Input. SCK (Pin 12): Serial Interface Clock. Data on the SDI pin is shifted into the input shift register on rising edge of SCK. CS/LD (Pin 13): Chip Select Input. When CS/LD is low, SCK is enabled for shifting data into the input shift register. When CS/LD is pulled high, SCK is disabled and the control logic executes the control word (the first 4 bits of the input data stream as shown in Table 1). CLR (Pin 14): When CLR is taken to a logic low, it sets the DAC output to 0V and all internal registers to zero code. REF (Pin 15): DAC Reference Input. Typically 5V, accepts up to ± 15V. R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC reference input REF (Pin 15) and the output of the inverting amplifier tied to RCOM (Pin 1). FU CTIO TABLE Table 1 Internal Register Status COMMAND BUF2 BUF1 SREG DAC DAC DATA WORD OPERATION BUFFER OUTPUT INPUT Dn IN INPUT EACH COMMAND IS EXECUTED C0 RANGE SHIFT REGISTER BUFFER (DAC OUTPUT) ON THE RISING EDGE OF CS/LD No Change No Change Dn Dn 0 Copy Data Word Dn in SReg to Buf1 Dn No Change Dn X 1 Copy the Data in Buf1 to Buf2 Dn No Change Dn Dn 0 Copy Data Word Dn in SReg to Buf1 and Buf2 1 Reserved (Do Not Use) 0 Reserved (Do Not Use) 1 Reserved (Do Not Use) 0 Reserved (Do Not Use) 1 Reserved (Do Not Use) Dn 5V Dn Dn 0 Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2 Dn 10V Dn Dn 1 Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2 Dn ± 5V Dn Dn 0 Set Range to ± 5V. Copy Dn in SReg to Buf1 and Buf2 Dn ± 10V Dn Dn 1 Set Range to ± 10V. Copy Dn in SReg to Buf1 and Buf2 Dn ± 2.5V Dn Dn 0 Set Range to ± 2.5V. Copy Dn in SReg to Buf1 and Buf2 Dn –2.5V to 7.5V Dn Dn 1 Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2 0 Reserved (Do Not Use) No Change No Change No Change X 1 No Operation C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code. U U U U U 1588992fa 7 LTC1588/LTC1589/LTC1592 BLOCK DIAGRA SDI SCK 24-BIT SHIFT REGISTER SDO CS/LD TI I G DIAGRA SCK t9 SDI t5 CS/LD t7 SDO 1588992 TD 8 W W BUF1 SREG 12-/14-/16-BIT DATA WORD Dn BUFFER 12/14/16 BITS BUFFER 12/14/16 BITS 12-/14-/16-BIT DAC SPAN ADJUST BUF2 4 BIT COMMAND WORD DECODER 1588992 BD 8-BIT SHIFT REGISTER UW t1 t2 1 t3 2 t4 23 t6 24 t11 t8 1588992fa LTC1588/LTC1589/LTC1592 OPERATIO INPUT WORD (LTC1588) COMMAND C3 C2 C1 C0 X DON’T CARE X X X D11 D10 D9 MSB DATA (12 BITS + 4 DON’T-CARE BITS) D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB X X X X 1588992 TD4 INPUT WORD (LTC1589) COMMAND C3 C2 C1 C0 X DON’T CARE X X X DATA (14 BITS + 2 DON’T-CARE BITS) D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB DATA (16 BITS) X D15 D14 D13 D12 D11 D10 D9 MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 1588992 TD2 INPUT WORD (LTC1592) COMMAND C3 C2 C1 C0 X DON’T CARE X X Serial Interface When the CS/LD is brought to a logic low, the data on the SDI input is loaded into the shift register on the rising edge of the clock. A 4-bit command word (C3 C2 C1 C0), followed by four “don’t care” bits and 16 data bits (MSB-first) is the minimum loading sequence required for the LTC1588/LTC1589/LTC1592. When the CS/LD is brought to a logic high, the clock is disabled internally and the command word is executed. If no daisy-chaining is required, the input stream can be 24-bit wide as shown in Figure 1a. The first four bits are the command word, followed by four “don’t care” bits, then a 16-bit data word. The last four bits (LSBs) of this 16-bit data word are don’t cares for the LTC1588. For the LTC1589, the last 2 bits of the 16-bit data word are don’t cares. If daisy-chaining is required or the input needs to be written in two 16-bit wide segments, then the input stream must be 32-bit wide and the first 8 bits loaded are “don’t care” bits. The remaining bits work the same as a 24-bit stream which is described in the previous paragraph. The output of the internal 32-bit shift register is available on the SDO pin 32 clock cycles later. Multiple LTC1588/LTC1589/LTC1592s may be daisychained together by connecting the SDO pin to the SDI pin of the next IC. The clock and CS/LD signals should remain common to all ICs in the daisy-chain. The serial data is U X X 1588992 TD3 clocked to all ICs, then the CS/LD signal is pulled high to update all of them simultaneously. Power-On Reset and Clear When the power supply is first turned on, the LTC1588/ LTC1589/LTC1592 will power up in 5V unipolar mode (C3 C2 C1 C0 = 1000). All the internal registers are set to zeros and the DAC is set to zero code. The LTC1588/LTC1589/LTC1592 must first be programmed in either unipolar or bipolar mode. There are six operating modes available and can be software-programmed by the command word. When a CLR signal is brought to low, it clears all internal registers to zero. The DAC output voltage goes to zero volts. If an update DAC command (C3 C2 C1 C0 = 0001) is issued immediately after the CLR signal, the DAC output remains at zero volts. If a CLR signal is given within a 100ns interval immediately after CS/LD goes high, the user should reload the output range. Output Range Programming There are two output ranges available in unipolar mode and four output ranges available in bipolar mode. See Function Table for details. All output ranges are with respect to a 5V reference input. When changing the LTC1588/ LTC1589/LTC1592 to a new mode, the command word and data are given at the same time (24 or 32 bit). When 1588992fa 9 SCK 1 2 7 13 14 17 D7 1588992 F01a 3 4 10 21 D3 D2 D1 D0 23 D14 DATA WORD Dn D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 22 16 20 C0 DON’T CARE (RESERVED) X X X X D15 5 6 8 9 19 15 C1 SDI CONTROL WORD C3 C2 LTC1588/LTC1589/LTC1592 Figure 1a. LTC1592 24-Bit Load Sequence (Minimum Input Word) LTC1589 SDI Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions LTC1588 SDI Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions 32-BIT DATA STREAM (CAN BE DAISY-CHAINED) CS/LD 6 7 13 14 17 D15 D14 D13 D12 D11 D10 D9 X DON’T CARE C0 X X X X D15 D14 D13 D12 D11 D10 D9 X X X X CONTROL WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 20 22 15 19 X 23 24 D8 25 D7 DATA WORD Dn D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0 SCK 1 2 3 4 5 SDI X X X X X DON’T CARE SDO X X X X X PREVIOUS 32-BIT INPUT WORD t1 t2 SCK 17 t3 SDI D15 t8 SDO PREVIOUS D15 PREVIOUS D14 t4 D14 18 CURRENT 32-BIT INPUT WORD 1588992 F01b Figure 1b. LTC1592 32-Bit Load Sequence (Required for Daisy-Chain Operation) LTC1589 SDI/SDO Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions LTC1588 SDI/SDO Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions U OPERATIO 10 24-BIT DATA STREAM (CANNOT BE DAISY-CHAINED) CS/LD 1588992fa LTC1588/LTC1589/LTC1592 OPERATIO CS/LD goes high, the mode changes and the DAC output goes to a value corresponding to the data code. Examples using the LTC1592: 1. Using a 24-bit loading sequence, load the unipolar range of 0V to 10V with the DAC output at zero volt: a) CS/LD b) Clock SDI = 1001 XXXX 0000 0000 0000 0000 c) CS/LD ; then VOUT = 0V 2. Using a 24-bit loading sequence, load the bipolar range of ±5V and the DAC output at zero volt: a) CS/LD b) Clock SDI = 1010 XXXX 1000 0000 0000 0000 c) CS/LD ; then VOUT = 0V on the ±5V range APPLICATIO S I FOR ATIO Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1592, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the LTC1592’s accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 2 and 3 can also be used to determine the effects of op amp parameters on the LTC1589 and the LTC1588. However, the results obtained from Tables 2 and 3 are in 16-bit LSBs. Divide these results by 4 (LTC1589) and 16 (LTC1588) to obtain the correct LSB sizing. U W UU U 3. Using a 32-bit load sequence, load the bipolar range of ±10V with the DAC output voltage at 5V initially. Then change the DAC output to –5V: a) CS/LD b) Clock SDI = XXXX XXXX 1011 XXXX 1100 0000 0000 0000 c) CS/LD ; then VOUT = 5V on the ±10V range Next, the bipolar range of ±10V is retained and the DAC output voltage is changed to VOUT = – 5V: a) CS/LD b) Clock SDI = XXXX XXXX 0010 XXXX 0100 0000 0000 0000 c) CS/LD ; then VOUT = – 5V on the ±10V range Table 4 contains a partial list of LTC precision op amps recommended for use with the LTC1592. The easy-to-use design equations simplify the selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 4 and insert the specified op amp parameters in Table 3. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the LTC1592. Arithmetic summation gives an (unlikely) worstcase effect. A root-sum-square (RMS) summation produces a more realistic estimate. Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC1592, a 250µV op amp offset will cause about 0.65LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range (20V range in bipolar). For the LTC1592 programmed in a unipolar mode, the same 250µV op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error with a 10V full-scale range. 1588992fa 11 LTC1588/LTC1589/LTC1592 APPLICATIO S I FOR ATIO While not directly addressed by the simple equations in Tables 2 and 3, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 3 and calculate the temperature induced effects. For applications where fast settling time is important, Application Note 74, entitled “Component and Measurement Table 2. Variables for Each Output Range That Adjust the Equations in Table 3 OUTPUT RANGE 5V 10V ± 5V ±10V ±2.5V –2.5V to 7.5V A1 1.1 2.2 2 4 1 1.9 A2 2 3 2 4 1 3 1.2 1.2 1.6 1 1 1 1 0.5 A3 A4 A5 1 1.5 1.5 2.5 1 1.5 Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges INL (LSB) 5V VOS1 (mV) VOS1 • 2.4 • V REF 5V IB1 (nA) IB1 • 0.0003 • V REF 16.5k AVOL1 (V/V) A1 • A VOL1 VOS2 (mV) IB2 (mV) AVOL2 (V/V) 0 0 0 OP AMP () () () DNL (LSB) 5V VOS1 • 0.6 • V REF 5V IB1 • 0.00008 • V REF 1.5k A2 • A VOL1 0 0 0 () () () UNIPOLAR OFFSET (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.13 • V REF 0 0 0 0 Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1588/LTC1589/LTC1592, with Relevant Specifications AMPLIFIER SPECIFICATIONS VOS µV 25 50 60 70 75 125 IB nA 2 0.35 0.25 20 10 10 AOL V/mV 800 1000 1500 4000 5000 2000 VOLTAGE NOISE nV/√Hz 10 14 14 2.7 5 5 CURRENT NOISE pA/√Hz 0.12 0.008 0.008 0.3 0.6 0.6 SLEW RATE V/µs 0.25 0.2 0.16 4.5 22 22 GAIN BANDWIDTH PRODUCT MHz 0.8 0.7 0.75 12.5 90 90 tSETTLING with LTC1592 µs 120 120 115 19 2.5 2.5 POWER DISSIPATION mW 46 11 10.5/Op Amp 69/Op Amp 117 123/Op Amp 1588992fa AMPLIFIER LT1001 LT1097 LT1112 (Dual) LT1124 (Dual) LT1468 LT1469 (Dual) 12 U Advances Ensure 16-Bit DAC Settling Time,” offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC1592 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC1592 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference W UU () () BIPOLAR ZERO ERROR (LSB) 5V A3 • VOS1 • 19.8 • V REF 5V IB1 • 0.01 • V REF 0 A4 • VOS2 • 13.1 • B2 () () REF (V5V ) ) 5V A4 • (I • 0.05 • ( V )) A4 • ( 66k ) A REF VOL2 ( UNIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.1 • VREF 131k AVOL2 () () () () () () BIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.1 • VREF 131k AVOL2 () () () () () () LTC1588/LTC1589/LTC1592 APPLICATIO S I FOR ATIO with low output voltage initial tolerance, like the LT1236 (±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Table 5. Partial List of LTC Precision References Recommended for Use with the LTC1588/LTC1589/LTC1592 with Relevant Specifications REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 LT1790A-2.5 INITIAL TOLERANCE ±0.05% ±0.05% ±0.075% ±0.05% TEMPERATURE DRIFT 5ppm/°C 5ppm/°C 10ppm/°C 10ppm/°C 0.1Hz to 10Hz NOISE 12µVP-P 3µVP-P 20µVP-P 12µVP-P U Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. IOUT2 must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than 1Ω, a force/sense amplified configuration should be used to drive this pin (see Figure 2). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC1588/LTC1589/LTC1592. An Isolated 16-Bit Subsystem Using the LTC1592 The circuit in Figure 4 is a complete example of an optically isolated analog output subsystem that supports most of the legacy ranges that are still common in industrial environments. This circuit uses only two optoisolators, the load pulse (CS/LD) being derived from a series of transitions on the data line (SDI) after the clock (SCK) is halted high. If a single chip microcontroller with an automated SPI interface is to be used, the SPI port can transfer the 24 bits as three bytes. Subsequently, the data output port pin can be reassigned to general purpose port operation and exercised to produce a number of transitions to generate the load pulse. Alternatively, the entire sequence can be programmed bit by bit with a general purpose port. Figure 5 shows the timing. The DC/DC converter, Figure 3 based on the LT®3439 ultralow noise transformer driver provides a compact means of powering this circuit, and allows the output to deliver output current that is only limited by the LT1468 capabilities. The output capability of the DC/DC converter itself is 80mA at ±12V and is available as demo board DC511A. This circuit as shown requires approximately 130mA of the 5V supply (no load). The total surface area required is less than 2 square inches. 1588992fa W UU 13 LTC1588/LTC1589/LTC1592 APPLICATIO S I FOR ATIO IOUT2 6 ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE 2 6 1 ZETEX BAT54S 2 VREF 5V 3 LT1468 3 IOUT2 1 6 LT1001 3 ZETEX* BAT54S 5 + 1/2 LT1469 7 2 3 6 – C3** 150pF *SCHOTTKY BARRIER DIODE 2 R1 R1 5V 9 0.1µF 14 13 12 11 10 CLR CS/LD SCK SDI SDO VCC 1 RCOM R2 16 15 3 4 RFB C2 15pF 15V 8 0.1µF R2 REF ROFS 12-/14-/16-BIT DAC WITH SPAN ADJUST IOUT2 6 AGND GND LTC1588/LTC1589/LTC1592 1588992 F02 7 8 **FOR MULTIPLYING APPLICATIONS C3 = 15pF Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits for Driving IOUT2 from AGND with a Force/Sense Amplifier LT1121-5 5V 2.2µF 3 BYP 1 LT1761 5 IN OUT C3 GND ADJ R4 22µF 2 4 442k 25V CER R5 49.9k C4 22µF 25V CER R6 49.9k C7 0.01µF 12V E1 VIN 5V ±5% E5 SHDN E7 SYNC VIN C1 4.7µF 6.3V R1 1M 11 5 R9 10k 6 C2 820pF 7 R2 16.9k SHDN SYNC LT3439 CT RT 10 1 COLB RSL 16 14 4 R3 15k 13 VIN COLA 3 D1 MMBD914 T1 CTX02-16030 D2 MMBD914 • • R10 10k • • D3 MMBD914 D4 MMBD914 E6 GND GND PGND PGND 1 4 R7 GND ADJ 442k 2 LT1964 5 IN OUT BYP 3 C22 2.2nF 1kV Figure 3. Isolated Power Supplies for the Circuit of Figure 4 1588992fa 14 + 3 – IOUT1 5 2 – + U 200Ω 200Ω 1000pF 2 1/2 LT1469 4 –15V 1 VOUT 0.1µF – + W UU + C5 33µF 25V TANT C6 33µF 25V TANT AGND + C8 0.01µF 1588992 F03 –12V LTC1588/LTC1589/LTC1592 PACKAGE DESCRIPTIO 7.8 – 8.2 0.42 ± 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U G Package 16-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 1.25 ± 0.12 5.90 – 6.50* (.232 – .256) 16 15 14 13 12 11 10 9 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.65 BSC 12345678 2.0 (.079) 0° – 8° 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G16 SSOP 0802 1588992fa 15 LTC1588/LTC1589/LTC1592 APPLICATIO S I FOR ATIO 74HC161 3 GND 4 5 6 2 7 10 9 1 5V A B C D OPTIONAL CIRCUIT FOR 2-WIRE INTERFACE. FOR A 3-WIRE INTERFACE (SPI), ADD A 3RD OPTOISOLATOR TO DRIVE CS/LD WITH THE WAVEFORMS OF FIGURE 1 12V 7 2 14 ISOLATED QA 13 CS/LD QB 12 QC 11 QD HCPL2300 VCC SCK TO µCONTROLLER VCC SDI 2 R2 7.5k 3 2 R1 7.5k 3 8 5V 7 6 5 CLK ENP ENT LD 15 CLR RCO HCPL2300 8 5V 7 6 5 ISOLATED SCK ISOLATED SDI 0.1µF 14 13 12 11 10 9 CLR CS/LD SCK SDI SDO 12-/14-/16-BIT DAC WITH SPAN ADJUST IOUT2 AGND LTC1588/LTC1589/LTC1592 GND 6 7 8 Figure 4. Optically Isolated 16-Bit SoftSpan System SCK SDI C3 C2 C1 C0 X D2 D1 D0 CS/LD 1588992 F05 Figure 5. Timing Diagram for the Circuit of Figure 4 RELATED PARTS PART NUMBER LTC1591/LTC1597 LTC1595/LTC1596 LTC1599 LTC1821 LTC2600/LTC2610 LTC2620 DESCRIPTION Parallel 14-/16-Bit Current Output DACs Serial 16-Bit Current Output DACs 2-Byte, 16-Bit Current Output DAC Parallel 16-Bit Voltage Outupt DAC Octal 16-/14-/12-Bit DACs COMMENTS On-Chip 4-Quadrant Resistors Low Glitch, ±1LSB Maximum INL, DNL On-Chip 4-Quadrant Resistors Precision 16-Bit Settling in 2µs for 10V Step Single Supply, µPower in Narrow SSOP16 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q LT/TP 0503 1K REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001 + 3 – U 5V REF 10µF 4 0.1µF 6 10µF 4 –12V 0.1µF 150pF 2 R1 5V R1 VCC IOUT1 5 2 1 RCOM R2 16 15 3 4 RFB 15pF 12V 7 LT1468 4 –12V 1588992 F04 W UU 12V 8 – LT1468 + LT1027-5 2 10µF 3 + R2 REF ROFS 10µF 0.1µF AGND 6 10µF VOUT 0.1µF AGND 1588992fa