LTC1588IG#PBF

LTC1588/LTC1589/LTC1592 12-/14-/16-Bit SoftSpan DACs with Programmable Output Range U FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1588/LTC1589/LTC1592 are serial input 12-/14/16-bit multiplying current output DACs that operates from a single 5V supply. These SoftSpanTM DACs can be software-programmed for either unipolar or bipolar mode through a 3-wire SPI interface. In either mode, the voltage output range can also be software-programmed. Two output ranges in unipolar mode and four output ranges in bipolar mode are available. Six Programmable Output Ranges Unipolar Mode: 0V to 5V, 0V to 10V Bipolar Mode: ±5V, ±10V, ±2.5V, – 2.5V to 7.5V 1LSB Max DNL and INL Over the Industrial Temperature Range Glitch Impulse < 2nV-s 16-Lead SSOP Package Power-On Reset to 0V Asynchronous Clear to 0V for All Ranges INL and DNL are accurate to 1LSB over the industrial temperature range in both unipolar and bipolar modes. True 16-bit 4-quadrant multiplication is achieved with on-chip four quadrant multiplication resistors. The LTC1588/LTC1589/LTC1592 are available in a 16-lead SSOP package. U APPLICATIO S ■ ■ ■ ■ ■ Process Control and Industrial Automation Precision Instrumentation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment These devices include an internal deglitcher circuit that reduces the glitch impulse to less than 2nV-s (typ). The asynchronous clear pin resets the LTC1588/LTC1589/ LTC1592 to 0V in unipolar or bipolar mode. , LTC and LT are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Programmable Output Range 16-Bit SoftSpan DAC VREF 5V LTC1592 Integral Nonlinearity + 1/2 LT®1469 6 1.0 7 VREF = 5V 0.8 ALL OUTPUT RANGES – INTEGRAL NONLINEARITY (LSB) 5 C2 150pF 2 1 R1 9 3 13 12 11 10 C1 15pF R2 VCC 0.1µF 14 4 R2 REF ROFS RFB RCOM R1 5V 16 15 IOUT1 CLR IOUT2 6 SCK SDO 2 16-BIT DAC WITH SPAN ADJUST CS/LD SDI 5 AGND LTC1592 GND 7 8 – 15V 8 0.1µF 1/2 LT1469 3 + 1 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 VOUT –1.0 0 4 –15V 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 TA02 0.1µF 1588992 TA01 1588992fa 1 LTC1588/LTC1589/LTC1592 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS (Note 1) VCC to AGND, GND ......................................– 0.3V to 7V AGND to GND .............................. – 0.3V to (VCC + 0.3V) GND to AGND .............................. – 0.3V to (VCC + 0.3V) RCOM to AGND, GND ................................ – 0.3V to 12V REF to AGND, GND ................................................ ±15V ROFS, RFB, R1, R2 to AGND, GND .......................... ±15V Digital Inputs to AGND, GND ....... – 0.3V to (VCC + 0.3V) IOUT1, IOUT2 to AGND, GND .......... – 0.3V to (VCC + 0.3V) Maximum Junction Temperature .......................... 150°C Operating Temperature Range LTC1588C/LTC1589C/LTC1592C ........... 0°C to 70°C LTC1588I/LTC1589I/LTC1592I ........... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RCOM 1 16 R2 R1 2 15 REF ROFS 3 14 CLR RFB 4 13 CS/LD IOUT1 5 12 SCK IOUT2 6 11 SDI AGND 7 10 SDO GND 8 9 LTC1588CG LTC1588IG LTC1589CG LTC1589IG LTC1592ACG LTC1592AIG LTC1592BCG LTC1592BIG VCC G PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 125°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. SYMBOL PARAMETER CONDITIONS LTC1588 LTC1589 LTC1592B LTC1592A MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX TEMPERATURE UNITS Accuracy Resolution INL ● 16 Bits ±1 ±1 ±1 ±1 ±2 ±2 ±0.3 ±1 ±0.4 ±1 LSB LSB Guaranteed Monotonic (Note 3) TMIN to TMAX ● ±1 ±1 ±1 ±0.2 ±1 LSB All Output Ranges (Note 3) TA = 25°C TMIN to TMAX ● –0.20 ±3 –0.22 ±3 –1.0 ±4 –1.3 ±6 –3 ±16 –4 ±24 –2 ±16 –3 ±16 LSB LSB Bipolar Zero Error All Bipolar Ranges (Note 3) TA = 25°C TMIN to TMAX ● ±1 ±1 ±2.5 ±4.0 ±10 ±16 ±5 ±8 LSB LSB ● 3 3 3 3 ppm/°C ● ±5 ±15 ±5 ±15 ±5 ±15 ±5 ±15 nA nA ±0.05 ±0.5 ±2 ±0.2 ±2 LSB/V DNL Differential Nonlinearity GE Gain Error Gain Temperature ∆Gain/∆Temperature Coefficient (Note 4) PSRR 16 ● (Notes 2, 3) ILKG 14 TA = 25°C TMIN to TMAX Integral Nonlinearity BZE 12 IOUT1 Leakage Current (Note 5) Power Supply Rejection VCC = 5V ±10% TA = 25°C TMIN to TMAX ● ±0.01±0.15 1 1588992fa 2 LTC1588/LTC1589/LTC1592 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input RREF DAC Input Resistance (Unipolar) (Note 6) ● 5 7 10 kΩ R1, R2 R1, R2 Resistance (Notes 6, 11) ● 10 14 20 kΩ ROFS Offset Resistance (Bipolar) ±5V, ±10V, ±2.5V Ranges –2.5V to 7.5V Range ● ● 10 20 14 28 20 40 kΩ kΩ RFB Feedback Resistance (Unipolar) 5V Range 10V Range ● ● 5 10 7 14 10 20 kΩ kΩ Feedback Resistance (Bipolar) ±5V and –2.5V to 7.5V Ranges ±10V Range ±2.5V Range ● ● ● 10 20 5 14 28 7 20 40 10 kΩ kΩ kΩ Analog Outputs (Note 4) COUT Output Capacitance (IOUT1) DAC Load All 1s DAC Load All 0s 160 100 pF pF µs AC Performance (Note 4) THD Settling Time 5V Range, 0V to 5V Step with LT1468 (Note 7) 2 Midscale Glitch Impulse (Note 10) 2 nV-s Multiplying Feedthrough Error VREF = ±10V, 10kHz Sine Wave 1 mVP-P Total Harmonic Distortion (Note 8) Multiplying Output Noise Voltage Density (Note 9) At IOUT1 – 108 dB 11 nV/√Hz Digital Inputs VIH Digital Input High Voltage ● 2.4 V VIL Digital Input Low Voltage ● 0.8 V IIN Digital Input Current ● ±1 µA CIN Digital Input Capacitance VIN = 0V (Note 4) ● 8 pF Digital Outputs VOH Digital Output High Voltage IOH = 200µA ● VOL Digital Output Low Voltage IOL = 1.6mA ● 4 V 0.4 V Timing Characteristics t1 Serial Input Valid to SCK Setup Time ● t2 Serial Input Valid to SCK Hold Time ● 0 ns t3 SCK Pulse Width High ● 35 ns t4 SCK Pulse Width Low ● 35 ns t5 CS/LD Pulse High Width ● 360 ns t6 LSB SCK High to CS/LD High ● 35 ns t7 CS/LD Low to SCK High ● 0 ns t8 SCK to SDO Propagation Delay ● 20 t9 SCK Low to CS/LD Low ● 35 ns t 10 Clear Pulse Low Width ● 100 ns t 11 CS/LD High to SCK Positive Edge ● 35 SCK Frequency CLOAD = 50pF Non-Daisy Chain (Note 12) Daisy Chain (Note 13) ● 60 ns 180 ns ns 14.2 4.1 MHz MHz 1588992fa 3 LTC1588/LTC1589/LTC1592 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.5 5 5.5 V 10 µA Power Supply VCC Supply Voltage ICC Supply Current, VCC ● Digital Inputs = 0V or VCC Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale (LTC1592). ±1LSB = ±0.006% of full scale = ±61.2ppm of full scale (LTC1589). ±1LSB = 0.024% of full scale = ±244.8ppm of full scale (LTC1588). Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: IOUT1 with DAC register loaded to all 0s. Note 6: Typical temperature coefficient is 100ppm/°C. Note 7: To 0.0015% for a full-scale change, measured from the falling edge of LD for the LTC1592 only. Note 8: REF = 6VRMS at 1kHz. DAC register loaded with all 1s. Output amplifier = LT1468. ● Note 9: Calculation from en = √4kTRB where: k = Boltzmann constant (1.38E-23 J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz). Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191 to 8192 for the LTC1589, 2047 to 2048 for the LTC1588. Note 11: R1 and R2 are measured between R1 and RCOM, R2 and RCOM. Note 12: If a continuous clock is used with data changing on the rising edge of SCK, setup and hold time (t1, t2) will limit the maximum clock frequency. If data changes on the falling edge of SCK then the setup time will limit the maximum clock frequency to 8MHz (continuous 50% duty cycle clock). Note 13: SDO propagation delay and SDI setup time (t8, t1) limit the maximum clock frequency for daisy chaining. U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC1588/LTC1589/LTC1592) Supply Current vs Input Voltage Midscale Glitch Impulse USING AN LT1468 CFEEDBACK = 30pF VREF = 10V 10 0 1nV-s TYPICAL –10 VCC = 5V ALL DIGITAL INPUTS TIED TOGETHER 4 20 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (mV) 30 –20 Logic Threshold vs Supply Voltage 3.0 5 2.5 LOGIC THRESHOLD (V) 40 3 2 1 2.0 1.5 1.0 0.5 – 30 – 40 0 0 0.2 0.4 0.6 TIME (µs) 0.8 1.0 1588992 G03 0 0 1 3 2 INPUT VOLTAGE (V) 4 5 1588992 G09 0 1 5 2 3 4 SUPPLY VOLTAGE (V) 6 7 1588992 G10 1588992fa 4 LTC1588/LTC1589/LTC1592 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC1588) Differential Nonlinearity 1.0 1.0 0.8 0.8 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 800 2400 3200 1600 DIGITAL INPUT CODE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 4095 800 0 2400 3200 1600 DIGITAL INPUT CODE 1588992 G11 4095 1588992 G12 (LTC1589) Differential Nonlinearity 1.0 0.8 0.8 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity 1.0 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 8224 12336 4112 DIGITAL INPUT CODE 16383 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 8224 12336 4112 DIGITAL INPUT CODE 0 1588992 G13 1588992 G14 (LTC1592) Integral Nonlinearity vs Reference Voltage in Unipolar Mode Differential Nonlinearity (DNL) 1.0 1.0 0.8 0.8 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 INTEGRAL NONLINEARITY (LSB) 1.0 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity (INL) 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 G01 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –1.0 16383 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1588992 G02 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 1588992 G05 1588992fa 5 LTC1588/LTC1589/LTC1592 U W TYPICAL PERFOR A CE CHARACTERISTICS Differential Nonlinearity vs Reference Voltage in Unipolar Mode 1.0 1.0 0.8 0.8 DIFFERENTIAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity vs Reference Voltage in Bipolar Mode 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) (LTC1592) 8 10 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 1588992 G06 8 10 1588992 G07 Differential Nonlinearity vs Reference Voltage in Bipolar Mode Full-Scale Settling Waveform DIFFERENTIAL NONLINEARITY (LSB) 1.0 0.8 0.6 LD PULSE 5V/DIV 0.4 0.2 GATED SETTLING WAVEFORM 500µV/DIV 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –10 – 8 – 6 – 4 – 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10 500ns/DIV USING LT1468 OP AMP CFEEDBACK = 20pF 0V TO 10V STEP 1592 G04 1588992 G08 U U U PI FU CTIO S RCOM (Pin 1): Center Tap Point of the Two Bipolar Resistors R1 and R2. Normally tied to the inverting input of an external amplifier. When these resistors are not used, connect this pin to ground. The absolute maximum voltage range on this pin is – 0.3V to 12V. ROFS (Pin 3): Bipolar Offset Network. This pin provides the offset of the output voltage range for bipolar modes. Accepts up to ±15V. Normally tied to R1 and the reference input voltage VREF (5V). Alternatively, this pin may be driven from a different voltage than VREF. R1 (Pin 2): Bipolar Resistor R1. The main reference input VREF, typically 5V. Accepts up to ±15V. Normally tied to ROFS (Pin 3) and the reference input voltage VREF (5V). When not used connect this pin to ground. RFB (Pin 4): Feedback Network. Normally tied to the output of the current to voltage converter op amp. Range limited to ±15V. 1588992fa 6 LTC1588/LTC1589/LTC1592 U U U PI FU CTIO S IOUT1 (Pin 5): True DAC Current Output. Tied to the inverting input of the current-to-voltage op amp. SCK (Pin 12): Serial Interface Clock. Data on the SDI pin is shifted into the input shift register on rising edge of SCK. IOUT2 (Pin 6): Complement of DAC Current Output. Normally tied to AGND pin. CS/LD (Pin 13): Chip Select Input. When CS/LD is low, SCK is enabled for shifting data into the input shift register. When CS/LD is pulled high, SCK is disabled and the control logic executes the control word (the first 4 bits of the input data stream as shown in Table 1). AGND (Pin 7): Analog Ground. Tie to the system’s analog ground plane. GND (Pin 8): Ground. Tie to the system’s analog ground plane. VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V. Requires a 0.1µF bypass capacitor to ground. SDO (Pin 10): Serial Data Output. Data at this pin is shifted out on the rising edge of SCK. SDI (Pin 11): Serial Data Input. CLR (Pin 14): When CLR is taken to a logic low, it sets the DAC output to 0V and all internal registers to zero code. REF (Pin 15): DAC Reference Input. Typically 5V, accepts up to ±15V. R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC reference input REF (Pin 15) and the output of the inverting amplifier tied to RCOM (Pin 1). U U FU CTIO TABLE Table 1 Internal Register Status COMMAND C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BUF2 BUF1 SREG DAC DAC DATA WORD OPERATION BUFFER OUTPUT INPUT Dn IN INPUT EACH COMMAND IS EXECUTED C0 RANGE SHIFT REGISTER BUFFER (DAC OUTPUT) ON THE RISING EDGE OF CS/LD No Change No Change Dn Dn 0 Copy Data Word Dn in SReg to Buf1 Dn No Change Dn X 1 Copy the Data in Buf1 to Buf2 Dn No Change Dn Dn 0 Copy Data Word Dn in SReg to Buf1 and Buf2 1 Reserved (Do Not Use) 0 Reserved (Do Not Use) 1 Reserved (Do Not Use) 0 Reserved (Do Not Use) 1 Reserved (Do Not Use) Dn 5V Dn Dn 0 Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2 Dn 10V Dn Dn 1 Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2 Dn ±5V Dn Dn 0 Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2 Dn ±10V Dn Dn 1 Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2 Dn ±2.5V Dn Dn 0 Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2 Dn –2.5V to 7.5V Dn Dn 1 Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2 0 Reserved (Do Not Use) No Change No Change No Change X 1 No Operation Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code. 1588992fa 7 LTC1588/LTC1589/LTC1592 W BLOCK DIAGRA SDI BUF1 BUF2 SREG 12-/14-/16-BIT DATA WORD Dn SCK BUFFER 12/14/16 BITS BUFFER 12/14/16 BITS 12-/14-/16-BIT DAC 24-BIT SHIFT REGISTER SPAN ADJUST 4 BIT COMMAND WORD DECODER 1588992 BD 8-BIT SHIFT REGISTER SDO CS/LD WU W TI I G DIAGRA t1 t2 t3 1 SCK 2 t9 t6 t4 23 24 t11 SDI t5 t7 CS/LD t8 SDO 1588992 TD 1588992fa 8 LTC1588/LTC1589/LTC1592 U OPERATIO INPUT WORD (LTC1588) COMMAND C3 C2 C1 C0 DON’T CARE X X X DATA (12 BITS + 4 DON’T-CARE BITS) X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X X X 1588992 TD4 LSB INPUT WORD (LTC1589) COMMAND C3 C2 C1 C0 DON’T CARE X X X DATA (14 BITS + 2 DON’T-CARE BITS) X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB X X 1588992 TD3 INPUT WORD (LTC1592) COMMAND C3 C2 C1 C0 DON’T CARE X X X DATA (16 BITS) X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 MSB D3 D2 D1 D0 LSB 1588992 TD2 Serial Interface When the CS/LD is brought to a logic low, the data on the SDI input is loaded into the shift register on the rising edge of the clock. A 4-bit command word (C3 C2 C1 C0), followed by four “don’t care” bits and 16 data bits (MSB-first) is the minimum loading sequence required for the LTC1588/LTC1589/LTC1592. When the CS/LD is brought to a logic high, the clock is disabled internally and the command word is executed. If no daisy-chaining is required, the input stream can be 24-bit wide as shown in Figure 1a. The first four bits are the command word, followed by four “don’t care” bits, then a 16-bit data word. The last four bits (LSBs) of this 16-bit data word are don’t cares for the LTC1588. For the LTC1589, the last 2 bits of the 16-bit data word are don’t cares. If daisy-chaining is required or the input needs to be written in two 16-bit wide segments, then the input stream must be 32-bit wide and the first 8 bits loaded are “don’t care” bits. The remaining bits work the same as a 24-bit stream which is described in the previous paragraph. The output of the internal 32-bit shift register is available on the SDO pin 32 clock cycles later. Multiple LTC1588/LTC1589/LTC1592s may be daisychained together by connecting the SDO pin to the SDI pin of the next IC. The clock and CS/LD signals should remain common to all ICs in the daisy-chain. The serial data is clocked to all ICs, then the CS/LD signal is pulled high to update all of them simultaneously. Power-On Reset and Clear When the power supply is first turned on, the LTC1588/ LTC1589/LTC1592 will power up in 5V unipolar mode (C3 C2 C1 C0 = 1000). All the internal registers are set to zeros and the DAC is set to zero code. The LTC1588/LTC1589/LTC1592 must first be programmed in either unipolar or bipolar mode. There are six operating modes available and can be software-programmed by the command word. When a CLR signal is brought to low, it clears all internal registers to zero. The DAC output voltage goes to zero volts. If an update DAC command (C3 C2 C1 C0 = 0001) is issued immediately after the CLR signal, the DAC output remains at zero volts. If a CLR signal is given within a 100ns interval immediately after CS/LD goes high, the user should reload the output range. Output Range Programming There are two output ranges available in unipolar mode and four output ranges available in bipolar mode. See Function Table for details. All output ranges are with respect to a 5V reference input. When changing the LTC1588/ LTC1589/LTC1592 to a new mode, the command word and data are given at the same time (24 or 32 bit). When 1588992fa 9 10 X X SDI SDO SCK CS/LD 1 X X 2 X X 3 X 4 X X X DON’T CARE 5 C3 SDI C2 2 C1 3 X X 6 X 5 X 7 DON’T CARE (RESERVED) X 6 X 8 D15 9 D14 10 D13 11 D12 12 D11 13 D10 14 D9 D8 16 D7 17 DATA WORD Dn 15 D6 18 D5 19 D4 20 D3 X X 8 C3 C3 C2 10 C1 11 C2 C1 CONTROL WORD 9 C0 C0 X X 13 X 15 X X DON’T CARE X 14 X X 16 17 D15 D15 PREVIOUS 32-BIT INPUT WORD 12 D14 D14 18 D12 D12 20 D15 t1 D11 D11 21 22 t8 t3 t2 D9 D9 D8 24 D7 25 t4 D14 D8 18 D7 DATA WORD Dn 23 PREVIOUS D14 17 D10 D10 SDO PREVIOUS D15 SDI SCK D13 D13 19 32-BIT DATA STREAM (CAN BE DAISY-CHAINED) D6 D5 D4 29 D3 D2 D2 30 1588992 F01a D3 24 D0 28 D4 23 D1 27 D5 22 D2 26 D6 21 Figure 1b. LTC1592 32-Bit Load Sequence (Required for Daisy-Chain Operation) LTC1589 SDI/SDO Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions LTC1588 SDI/SDO Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions X X 7 C0 4 Figure 1a. LTC1592 24-Bit Load Sequence (Minimum Input Word) LTC1589 SDI Data Word = 14-Bit Input Code + 2 Don’t Care Bits at LSB Positions LTC1588 SDI Data Word = 12-Bit Input Code + 4 Don’t Care Bits at LSB Positions CONTROL WORD 1 SCK CS/LD 24-BIT DATA STREAM (CANNOT BE DAISY-CHAINED) D1 D1 31 D0 D0 32 1588992 F01b CURRENT 32-BIT INPUT WORD LTC1588/LTC1589/LTC1592 U OPERATIO 1588992fa LTC1588/LTC1589/LTC1592 U OPERATIO CS/LD goes high, the mode changes and the DAC output goes to a value corresponding to the data code. Examples using the LTC1592: 1. Using a 24-bit loading sequence, load the unipolar range of 0V to 10V with the DAC output at zero volt: 3. Using a 32-bit load sequence, load the bipolar range of ±10V with the DAC output voltage at 5V initially. Then change the DAC output to –5V: a) CS/LD a) CS/LD b) Clock SDI = XXXX XXXX 1011 XXXX 1100 0000 0000 0000 b) Clock SDI = 1001 XXXX 0000 0000 0000 0000 c) CS/LD ; then VOUT = 5V on the ±10V range c) CS/LD ; then VOUT = 0V Next, the bipolar range of ±10V is retained and the DAC output voltage is changed to VOUT = – 5V: 2. Using a 24-bit loading sequence, load the bipolar range of ±5V and the DAC output at zero volt: a) CS/LD b) Clock SDI = 1010 XXXX 1000 0000 0000 0000 c) CS/LD ; then VOUT = 0V on the ±5V range a) CS/LD b) Clock SDI = XXXX XXXX 0010 XXXX 0100 0000 0000 0000 c) CS/LD ; then VOUT = – 5V on the ±10V range U W U U APPLICATIO S I FOR ATIO Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1592, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the LTC1592’s accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 2 and 3 can also be used to determine the effects of op amp parameters on the LTC1589 and the LTC1588. However, the results obtained from Tables 2 and 3 are in 16-bit LSBs. Divide these results by 4 (LTC1589) and 16 (LTC1588) to obtain the correct LSB sizing. Table 4 contains a partial list of LTC precision op amps recommended for use with the LTC1592. The easy-to-use design equations simplify the selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 4 and insert the specified op amp parameters in Table 3. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the LTC1592. Arithmetic summation gives an (unlikely) worstcase effect. A root-sum-square (RMS) summation produces a more realistic estimate. Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC1592, a 250µV op amp offset will cause about 0.65LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range (20V range in bipolar). For the LTC1592 programmed in a unipolar mode, the same 250µV op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error with a 10V full-scale range. 1588992fa 11 LTC1588/LTC1589/LTC1592 U W U U APPLICATIO S I FOR ATIO While not directly addressed by the simple equations in Tables 2 and 3, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 3 and calculate the temperature induced effects. Advances Ensure 16-Bit DAC Settling Time,” offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations For applications where fast settling time is important, Application Note 74, entitled “Component and Measurement Table 2. Variables for Each Output Range That Adjust the Equations in Table 3 OUTPUT RANGE A1 A2 5V 1.1 2 A3 A4 A5 1 10V 2.2 3 1.5 ±5V 2 2 1.2 1 1.5 ±10V 4 4 1.2 1 2.5 ±2.5V 1 1 1.6 1 1 –2.5V to 7.5V 1.9 3 1 0.5 1.5 Much in the same way selecting an operational amplifier for use with the LTC1592 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC1592 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges OP AMP INL (LSB) 5V VOS1 (mV) VOS1 • 2.4 • V REF 5V IB1 (nA) IB1 • 0.0003 • V REF 16.5k AVOL1 (V/V) A1 • A VOL1 ( ) ( ) ( ) DNL (LSB) 5V VOS1 • 0.6 • V REF 5V IB1 • 0.00008 • V REF 1.5k A2 • A VOL1 ( ) ( ) ( ) BIPOLAR ZERO ERROR (LSB) UNIPOLAR OFFSET (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.13 • V REF 5V A3 • VOS1 • 19.8 • V REF 5V IB1 • 0.01 • V REF 0 0 ( ) ( ) VOS2 (mV) 0 0 0 IB2 (mV) 0 0 0 AVOL2 (V/V) 0 0 0 ( ) ( ) ( (V5V ) ) 5V A4 • (I • 0.05 • ( V )) A4 • ( 66k ) A A4 • VOS2 • 13.1 • B2 REF REF VOL2 UNIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.1 • VREF 131k AVOL2 ( ) ( ) ( ) ( ) ( ) ( ) BIPOLAR GAIN ERROR (LSB) 5V VOS1 • 13.2 • V REF 5V IB1 • 0.0018 • V REF 131k A5 • AVOL1 5V VOS2 • 26.2 • VREF 5V IB2 • 0.1 • VREF 131k AVOL2 ( ) ( ) ( ) ( ) ( ) ( ) Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1588/LTC1589/LTC1592, with Relevant Specifications AMPLIFIER SPECIFICATIONS IB nA AOL V/mV VOLTAGE NOISE nV/√Hz CURRENT NOISE pA/√Hz SLEW RATE V/µs GAIN BANDWIDTH PRODUCT MHz tSETTLING with LTC1592 µs POWER DISSIPATION mW AMPLIFIER VOS µV LT1001 25 2 800 10 0.12 0.25 0.8 120 46 LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp LT1468 75 10 5000 5 0.6 22 90 2.5 117 LT1469 (Dual) 125 10 2000 5 0.6 22 90 2.5 123/Op Amp 1588992fa 12 LTC1588/LTC1589/LTC1592 U W U U APPLICATIO S I FOR ATIO with low output voltage initial tolerance, like the LT1236 (±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Table 5. Partial List of LTC Precision References Recommended for Use with the LTC1588/LTC1589/LTC1592 with Relevant Specifications INITIAL TOLERANCE TEMPERATURE DRIFT 0.1Hz to 10Hz NOISE LT1019A-5, LT1019A-10 ±0.05% 5ppm/°C 12µVP-P LT1236A-5, LT1236A-10 ±0.05% 5ppm/°C 3µVP-P LT1460A-5, LT1460A-10 ±0.075% 10ppm/°C 20µVP-P LT1790A-2.5 ±0.05% 10ppm/°C 12µVP-P REFERENCE Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. IOUT2 must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than 1Ω, a force/sense amplified configuration should be used to drive this pin (see Figure 2). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC1588/LTC1589/LTC1592. An Isolated 16-Bit Subsystem Using the LTC1592 The circuit in Figure 4 is a complete example of an optically isolated analog output subsystem that supports most of the legacy ranges that are still common in industrial environments. This circuit uses only two optoisolators, the load pulse (CS/LD) being derived from a series of transitions on the data line (SDI) after the clock (SCK) is halted high. If a single chip microcontroller with an automated SPI interface is to be used, the SPI port can transfer the 24 bits as three bytes. Subsequently, the data output port pin can be reassigned to general purpose port operation and exercised to produce a number of transitions to generate the load pulse. Alternatively, the entire sequence can be programmed bit by bit with a general purpose port. Figure 5 shows the timing. The DC/DC converter, Figure 3 based on the LT®3439 ultralow noise transformer driver provides a compact means of powering this circuit, and allows the output to deliver output current that is only limited by the LT1468 capabilities. The output capability of the DC/DC converter itself is 80mA at ±12V and is available as demo board DC511A. This circuit as shown requires approximately 130mA of the 5V supply (no load). The total surface area required is less than 2 square inches. 1588992fa 13 LTC1588/LTC1589/LTC1592 U W U U APPLICATIO S I FOR ATIO ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE 6 – 1000pF LT1468 1 3 + ZETEX BAT54S 2 6 IOUT2 3 2 LT1001 + 6 200Ω 200Ω 2 – IOUT2 1 VREF 5V 3 ZETEX* BAT54S 5 + 2 6 3 7 1/2 LT1469 *SCHOTTKY BARRIER DIODE – C3** 150pF 2 1 16 15 R1 RCOM R2 REF ROFS 9 13 12 11 10 C2 15pF VCC 0.1µF 14 4 RFB R2 R1 5V 3 5 2 – IOUT2 6 3 + IOUT1 12-/14-/16-BIT DAC WITH SPAN ADJUST CLR CS/LD SCK AGND SDI GND 15V 8 0.1µF 1/2 LT1469 7 4 –15V 8 1 VOUT 0.1µF LTC1588/LTC1589/LTC1592 SDO 1588992 F02 **FOR MULTIPLYING APPLICATIONS C3 = 15pF Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits for Driving IOUT2 from AGND with a Force/Sense Amplifier 5V 2.2µF LT1121-5 E1 VIN 5V ±5% D1 MMBD914 VIN C1 4.7µF 6.3V R1 1M 13 E5 SHDN 11 E7 SYNC 5 C2 820pF VIN COLA 3 LT3439 7 R2 16.9k • • • • D2 MMBD914 SYNC R9 10k 6 E6 GND SHDN T1 CTX02-16030 CT COLB RT RSL GND PGND PGND 10 1 16 D3 MMBD914 14 D4 MMBD914 4 R3 15k R10 10k 3 BYP 1 LT1761 5 IN OUT C3 GND ADJ R4 22µF 2 4 442k 25V CER R5 49.9k C4 22µF 25V CER R6 49.9k 1 4 R7 GND ADJ 442k 2 LT1964 5 IN OUT BYP 3 C7 0.01µF 12V + C5 33µF 25V TANT + C6 33µF 25V TANT 1588992 F03 AGND –12V C8 0.01µF C22 2.2nF 1kV Figure 3. Isolated Power Supplies for the Circuit of Figure 4 1588992fa 14 LTC1588/LTC1589/LTC1592 U PACKAGE DESCRIPTIO G Package 16-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 5.90 – 6.50* (.232 – .256) 1.25 ±0.12 7.8 – 8.2 16 15 14 13 12 11 10 9 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42 ±0.03 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 5.00 – 5.60** (.197 – .221) 2.0 (.079) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G16 SSOP 0802 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 1588992fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1588/LTC1589/LTC1592 U W U U APPLICATIO S I FOR ATIO OPTIONAL CIRCUIT FOR 2-WIRE INTERFACE. FOR A 3-WIRE INTERFACE (SPI), ADD A 3RD OPTOISOLATOR TO DRIVE CS/LD WITH THE WAVEFORMS OF FIGURE 1 5V REF 12V 10µF 8 12V 7 74HC161 HCPL2300 2 VCC SCK 5 HCPL2300 2 VCC SDI 8 5V 7 6 R1 7.5k 3 TO µCONTROLLER 3 GND 4 5 6 2 7 10 9 1 A B C D 2 4 0.1µF 3 + 2 10µF 6 LT1468 CLK ENP ENT LD 15 CLR RCO + – LT1027-5 10µF 4 –12V 0.1µF 150pF 5V 5V 8 5V 7 9 ISOLATED SDI 2 1 16 15 R1 RCOM R2 REF ROFS R1 ISOLATED SCK 6 R2 7.5k 3 14 ISOLATED QA 13 CS/LD QB 12 QC 11 QD 3 VCC IOUT1 14 13 12 11 10 5 2 12-/14-/16-BIT DAC WITH SPAN ADJUST CLR 3 CS/LD IOUT2 SCK AGND SDI LTC1588/LTC1589/LTC1592 SDO 10µF 15pF R2 0.1µF 5 4 RFB GND – + 6 12V 7 LT1468 0.1µF AGND 6 VOUT 10µF 4 –12V 7 8 1588992 F04 0.1µF AGND Figure 4. Optically Isolated 16-Bit SoftSpan System SCK C3 SDI C2 C1 C0 X D2 D1 D0 CS/LD 1588992 F05 Figure 5. Timing Diagram for the Circuit of Figure 4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1591/LTC1597 Parallel 14-/16-Bit Current Output DACs On-Chip 4-Quadrant Resistors LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL LTC1599 2-Byte, 16-Bit Current Output DAC On-Chip 4-Quadrant Resistors LTC1821 Parallel 16-Bit Voltage Outupt DAC Precision 16-Bit Settling in 2µs for 10V Step LTC2600/LTC2610 LTC2620 Octal 16-/14-/12-Bit DACs Single Supply, µPower in Narrow SSOP16 1588992fa 16 Linear Technology Corporation LT/TP 0503 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2001