LTC1594L/LTC1598L
4- and 8-Channel,
3V Micropower Sampling
12-Bit Serial I/O A/D Converters
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FEATURES
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DESCRIPTIO
The LTC®1594L/LTC1598L are 3V micropower, 12-bit
sampling A/D converters that feature 4- and 8-channel
multiplexers, respectively. They typically draw only 160µA
of supply current when converting and automatically
power down to a typical supply current of 1nA between
conversions. The LTC1594L is available in a 16-pin SO
package and the LTC1598L is packaged in a 24-pin
SSOP. Both operate on a 3V supply. The 12-bit, switchedcapacitor, successive approximation ADCs include a
sample-and-hold.
12-Bit Resolution on 3V Supply
Low Supply Current: 160µA Typ
Auto Shutdown to 1nA
Guaranteed ±3/4LSB Max DNL
Guaranteed 2.7V Operation
(5V Versions Available: LTC1594/LTC1598)
Multiplexer: 4-Channel MUX (LTC1594L)
8-Channel MUX (LTC1598L)
Separate MUX Output and ADC Input Pins
MUX and ADC May Be Controlled Separately
Sampling Rate: 10.5ksps
I/O Compatible with QSPI, SPI and MICROWIRETM, etc.
Small Package: 16-Pin Narrow SO (LTC1594L)
24-Pin SSOP (LTC1598L)
On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
or four wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers.
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APPLICATIO S
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The circuit can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1.5V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
Pen Screen Digitizing
Battery-Operated Systems
Remote Data Acquisition
Isolated Data Acquisition
Battery Monitoring
Temperature Measurement
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATION
12µW, 8-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 3V Supply
OPTIONAL
ADC FILTER
Supply Current vs Sample Rate
18
MUXOUT
ANALOG
INPUTS
0V TO 3V
RANGE
20
CH0
21
CH1
22
CH2
23
CH3
24
CH4
1
CH5
2
CH6
3
CH7
8
COM
3V
1µF
17
ADCIN
16
15, 19
VREF VCC
CSADC
CSMUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
–
CLK
DIN
DOUT
LTC1598L
GND
4, 9
NC
NC
1000
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
1µF
10
6
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
5, 14
7
11
MPU
SUPPLY CURRENT (µA)
1k
100
10
12
13
1
0.1
1594L/98L TA01
1
10
SAMPLE FREQUENCY (kHz)
100
1594L/98L TA02
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LTC1594L/LTC1598L
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) to GND ................................... 12V
Voltage
Analog Reference .................... – 0.3V to (VCC + 0.3V)
Analog Inputs .......................... – 0.3V to (VCC + 0.3V)
Digital Inputs .........................................– 0.3V to 12V
Digital Output .......................... – 0.3V to (VCC + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1594LCS/LTC1598LCG ..................... 0°C to 70°C
LTC1594LIS/LTC1598LIG ................. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
CH0 1
16 VCC
CH1 2
15 MUXOUT
CH2 3
14 DIN
CH3 4
13 CSMUX
LTC1594LCS
LTC1594LIS
CH5
1
24 CH4
CH6
2
23 CH3
CH7
3
22 CH2
GND
4
21 CH1
CLK
5
20 CH0
19 VCC
CSMUX
6
ADCIN 5
12 CLK
DIN
7
18 MUXOUT
VREF 6
11 VCC
COM
8
17 ADCIN
COM 7
10 DOUT
GND
9
16 VREF
GND 8
9
CSADC
S PACKAGE
16-LEAD PLASTIC SO
ORDER PART
NUMBER
TOP VIEW
CSADC 10
15 VCC
DOUT 11
14 CLK
NC 12
TJMAX = 125°C, θJA = 120°C/ W
LTC1598LCG
LTC1598LIG
13 NC
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 110°C/ W
Consult factory for Military grade parts.
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RECOM ENDED OPERATING CONDITIONS
The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
VCC
fCLK
tCYC
thDI
tsuCS
tsuDI
tWHCLK
tWLCLK
tWHCS
tWLCS
PARAMETER
Supply Voltage (Note 3)
Clock Frequency
Total Cycle Time
Hold Time, DIN After CLK↑
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
Setup Time, DIN Stable Before CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
CONDITIONS
VCC = 2.7V
fCLK = 200kHz
VCC = 2.7V
VCC = 2.7V
VCC = 2.7V
VCC = 2.7V
VCC = 2.7V
fCLK = 200kHz
fCLK = 200kHz
MIN
2.7
(Note 4)
95
450
2
600
1.5
1.5
25
70
TYP
MAX
3.6
200
UNITS
V
kHz
µs
ns
µs
ns
µs
µs
µs
µs
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LTC1594L/LTC1598L
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CONVERTER AND MULTIPLEXER CHARACTERISTICS
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
REF Input Range
Analog Input Range
MUX Channel Input Leakage Current
MUXOUT Leakage Current
ADCIN Input Leakage Current
CONDITIONS
●
(Note 6)
●
●
●
(Notes 7, 8)
(Notes 7, 8)
Off Channel
Off Channel
(Note 9)
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DYNAMIC ACCURACY
SYMBOL
S/(N + D)
THD
SFDR
●
●
●
●
LTC1594LCS/LTC1598LCG
LTC1594LIS/LTC1598LIG
MIN
TYP
MAX
MIN
TYP
MAX
12
12
±3
±3
± 3/4
±1
±3
±3
±8
±8
1.5V to VCC + 0.05V
– 0.05V to VCC + 0.05V
±200
±200
±200
±200
±1
±1
UNITS
Bits
LSB
LSB
LSB
LSB
V
V
nA
nA
µA
TA = 25°C, fSMPL = 10.5kHz. (Note 5)
PARAMETER
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
Peak Harmonic or Spurious Noise
CONDITIONS
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
MIN
TYP
68
– 78
80
– 80
MAX
UNITS
dB
dB
dB
dB
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
VIH
VIL
IIH
IIL
VOH
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
VOL
IOZ
ISOURCE
ISINK
RREF
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Input Resistance
IREF
Reference Current
ICC
Supply Current
CONDITIONS
VCC = 3.6V
VCC = 2.7V
VIN = VCC
VIN = 0V
VCC = 2.7V, IO = 10µA
VCC = 2.7V, IO = 360µA
VCC = 2.7V, IO = 400µA
CS = High
VOUT = 0V
VOUT = VCC
CS = VIH
CS = VIL
CS = VCC
tCYC ≥ 760µs, fCLK ≤ 25kHz
tCYC ≥ 60µs, fCLK ≤ 200kHz
CS = VCC, CLK = VCC, DIN = VCC
tCYC ≥ 760µs, fCLK ≤ 25kHz
tCYC ≥ 60µs, fCLK ≤ 200kHz
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MIN
2.0
TYP
0.8
2.5
– 2.5
●
●
●
●
●
2.4
2.1
2.64
2.30
0.4
±3
●
●
●
●
●
●
MAX
– 10
15
2700
60
0.001
50
50
0.001
160
160
2.5
70
±5
400
UNITS
V
V
µA
µA
V
V
V
µA
mA
mA
MΩ
kΩ
µA
µA
µA
µA
µA
µA
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LTC1594L/LTC1598L
AC CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.(Note 5)
SYMBOL
tSMPL
fSMPL(MAX)
PARAMETER
Analog Input Sample Time
Maximum Sampling Frequency
CONDITIONS
See Figure 1 in Applications Information
See Figure 1 in Applications Information
tCONV
tdDO
tdis
ten
thDO
tf
tr
tON
tOFF
tOPEN
CIN
Conversion Time
Delay Time, CLK↓ to DOUT Data Valid
Delay Time, CS↑ to DOUT Hi-Z
Delay Time, CLK↓ to DOUT Enabled
Time Output Data Remains Valid After CLK↓
DOUT Fall Time
DOUT Rise Time
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Input Capacitance
See Figure 1 in Applications Information
See Test Circuits
See Test Circuits
See Test Circuits
CLOAD = 100pF
See Test Circuits
See Test Circuits
See Figure 1 in Applications Information
See Figure 2 in Applications Information
●
MIN
1.5
10.5
●
●
●
●
●
●
●
●
125
Analog Inputs On-Channel
Off-Channel
Digital Input
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 3V. Consult factory for 5V
specified devices (LTC1594/LTC1598).
Note 4: Increased leakage currents at elevated temperatures cause the S/H
to droop, therefore it is recommended that fCLK ≥ 200kHz at 85°C,
fCLK ≥ 75kHz at 70°C and fCLK ≥ 1kHz at 25°C.
Note 5: VCC = 2.7V, VREF = 2.5V and CLK = 200kHz unless otherwise
specified. CSADC and CSMUX pins are tied together during the test.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
TYP
12
600
220
180
520
60
80
540
190
350
20
5
5
MAX
1500
600
500
180
180
1200
500
UNITS
CLK Cycles
kHz
CLK Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above VCC. This spec allows 50mV forward
bias of either diode for 2.7V ≤ VCC ≤ 3.6V. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 3V
input voltage range, it will therefore require a minimum supply voltage of
2.950V over initial tolerance, temperature variations and loading.
Note 8: Recommended operating condition.
Note 9: Channel leakage current is measured after the channel selection.
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sample Rate
53
260
220
100
10
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
fSMPL = 10.5kHz
52
REFERENCE CURRENT (µA)
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
Reference Current vs Temperature
Supply Current vs Temperature
1000
180
140
100
51
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
fSMPL = 10.5kHz
50
49
48
47
46
45
44
1
0.1
1
10
SAMPLE FREQUENCY (kHz)
100
1594L/98L G01
60
– 55 – 35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1594L/98L G02
43
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1594L/98L G03
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LTC1594L/LTC1598L
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TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset
vs Reference Voltage
0.50
0.20
2.0
1.5
1.0
0.5
VCC = 2.7V
0.15 VREF = 2.5V
fCLK = 200kHz
0.10 fSMPL = fSMPL(MAX)
0.05
0
– 0.05
– 0.10
0.25
0.20
0.15
0.10
0.05
1.5
2.0
2.5
REFERENCE VOLTAGE (V)
3.0
0
0
10
50
40
30
TEMPERATURE (°C)
20
Effective Bits and S/(N + D)
vs Input Frequency
DIFFERENTIAL NONLINEARITY ERROR (LSB)
–7
–6
–5
–4
–3
1
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
0.5
0
– 0.5
–2
–1
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE (V)
–1
0
56
8
50
7
6
5
4
3
TA = 25°C
VCC = 2.7V
fCLK = 200kHz
fSMPL = 10.5kHz
2
1
1
10
INPUT FREQUENCY (kHz)
80
70
60
50
40
30
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fSMPL = fSMPL(MAX)
0
100
1594L/98L G10
100
1594L/98L G09
Frequency Response
0
80
TA = 25°C
70 VCC = 2.7V
VREF = 2.5V
60 fIN = 1kHz
fSMPL = fSMPL(MAX)
10
20
ATTENUATION (%)
SIGNAL-TO-NOISE PLUS DISTORTION (dB)
90
10
INPUT FREQUENCY (kHz)
62
9
S/(N + D) vs Input Level
100
1
68
10
1594L/98L G08
Spurious Free Dynamic Range
vs Input Frequency
10
74
11
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1594L/98L G07
12
S/(N + D) (dB)
TA = 25°C
VCC = 2.7V
fCLK = 200kHz
fSMPL = 10.5kHz
20
1594L/98L G06
Differential Nonlinearity vs Code
–10
–8
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE (V)
70
1594L/98L G05
Change in Gain
vs Reference Voltage
–9
60
EFFECTIVE NUMBER OF BITS (ENOBs)
1.0
1594L/98L G04
CHANGE IN GAIN (LSB)
0.35
0.30
– 0.20
0.5
SPURIOUS-FREE DYNAMIC RANGE (dB)
0.40
– 0.15
0
TA = 25°C
VCC = 2.7V
fCLK = 200kHz
fSMPL = 10.5kHz
0.45
CHANGE IN LINEARITY (LSB)
TA = 25°C
VCC = 2.7V
fCLK = 200kHz
fSMPL = 10.5kHz
CHANGE IN OFFSET (LSB)
CHANGE IN OFFSET (LSB = 1/4096 × VREF)
3.0
2.5
Change in Linearity
vs Reference Voltage
Change in Offset vs Temperature
50
40
30
20
30
40
50
60
(MUX + ADC)
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fSMPL = fSMPL(MAX)
70
80
10
90
0
– 45 – 40 – 35 – 30 – 25 – 20 – 15 – 10 – 5
INPUT LEVEL (dB)
100
0
1594L/98/ G11
1k
100k
1M
10k
INPUT FREQUENCY (Hz)
10M
1594L/98L G12
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LTC1594L/LTC1598L
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TYPICAL PERFORMANCE CHARACTERISTICS
0
TA = 25°C
VCC = 2.7V
VREF = 2.5V
f1 = 2.05kHz
f2 = 3.05kHz
fSMPL = 7.5kHz
– 20
MAGNITUDE (dB)
MAGNITUDE (dB)
– 40
0
0
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fIN = 3.05kHz
fCLK = 120kHz
fSMPL = 7.5kHz
– 20
Power Supply Feedthrough
vs Ripple Frequency
Intermodulation Distortion
– 60
– 80
– 100
– 40
TA = 25°C
VCC = 2.7V (VRIPPLE = 1mV)
VREF = 2.5V
fCLK = 200kHz
– 10
– 20
FEEDTHROUGH (dB)
4096 Point FFT Plot
– 60
– 80
– 30
– 40
– 50
– 60
– 70
– 80
– 100
– 90
– 120
0
0.5
1.0
–100
– 120
1.5 2.0 2.5 3.0
FREQUENCY (kHz)
3.5
0
4.0
0.5
1.0
1.5 2.0 2.5 3.0
FREQUENCY (kHz)
1594L/98L G13
1k
4.0
10M
1594L/98L G15
Sample-and-Hold Acquisition Time
vs Source Resistance
10000
200
S & H ACQUISITION TIME (ns)
TA = 25°C
VCC = 2.7V
VREF = 2.5V
190
180
170
160
150
VIN
+INPUT
140
–INPUT
130
RSOURCE–
TA = 25°C
VCC = 2.7V
VREF = 2.5V
1000
RSOURCE+
VIN
+INPUT
–INPUT
100
120
10
100
SOURCE RESISTANCE (Ω)
1
1000
10
100
1000
SOURCE RESISTANCE (Ω)
Input Channel Leakage Current
vs Temperature
Minimum Clock Frequency for
0.1LSB Error vs Temperature
1000
120
VCC = 2.7V
VREF = 2.5V
100
VCC = 2.7V
VREF = 2.5V
LEAKAGE CURRENT (nA)
100
80
60
40
10
1
ON CHANNEL
OFF CHANNEL
0.1
20
2
0
10000
1594L/98L G17
1594L/98L G16
CLOCK FREQUENCY (kHz)
100k
1M
10k
RIPPLE FREQUENCY (Hz)
1594L/98L G14
Maximum Clock Frequency
vs Source Resistance
CLOCK FREQUENCY (kHz)
3.5
0
10
20
30
50
40
TEMPERATURE (°C)
60
70
1594L/98L G18
0.01
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1594L/98L G19
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LTC1594L/LTC1598L
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PIN FUNCTIONS
LTC1594L
CH0 (Pin 1): Analog Multiplexer Input.
CH1 (Pin 2): Analog Multiplexer Input.
CH2 (Pin 3): Analog Multiplexer Input.
CH3 (Pin 4): Analog Multiplexer Input.
ADCIN (Pin 5): ADC Input. This input is the positive analog
input to the ADC. Connect this pin to MUXOUT for normal
operation.
VREF (Pin 6): Reference Input. The reference input defines
the span of the ADC.
COM (Pin 7): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 8): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 9): ADC Chip Select Input. A logic high on this
input powers down the ADC and three-states DOUT. A logic
low on this input enables the ADC to sample the selected
channel and start the conversion. For normal operation,
drive this pin in parallel with CSMUX.
DOUT (Pin 10): Digital Data Output. The A/D conversion
result is shifted out of this output.
VCC (Pin 11): Power Supply Voltage. This pin provides
power to the ADC. It must be bypassed directly to the
analog ground plane.
CLK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer to both MUX and ADC.
CSMUX (Pin 13): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
DIN (Pin 14): Digital Data Input. The multiplexer address
is shifted into this input.
MUXOUT (Pin 15): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
VCC (Pin 16): Power Supply Voltage. This pin should be
tied to Pin 11.
LTC1598L
CH5 (Pin 1): Analog Multiplexer Input.
CH6 (Pin 2): Analog Multiplexer Input.
CH7 (Pin 3): Analog Multiplexer Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CLK (Pin 5): Shift Clock. This clock synchronizes the serial
data transfer to both MUX and ADC. It also determines the
conversion speed of the ADC.
CSMUX (Pin 6): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.
DIN (Pin 7): Digital Data Input. The multiplexer address is
shifted into this input.
COM (Pin 8): Negative Analog Input. This input is the
negative analog input to the ADC and must be free of noise
with respect to GND.
GND (Pin 9): Analog Ground. GND should be tied directly
to an analog ground plane.
CSADC (Pin 10): ADC Chip Select Input. A logic high on
this input deselects and powers down the ADC and threestates DOUT. A logic low on this input enables the ADC to
sample the selected channel and start the conversion. For
normal operation drive this pin in parallel with CSMUX.
DOUT (Pin 11): Digital Data Output. The A/D conversion
result is shifted out of this output.
NC (Pin 12): No Connection.
NC (Pin 13): No Connection.
CLK (Pin 14): Shift Clock. This input should be tied to Pin 5.
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LTC1594L/LTC1598L
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PIN FUNCTIONS
VCC (Pin 15): Power Supply Voltage. This pin provides
power to the A/D Converter. It must be bypassed directly
to the analog ground plane.
VCC (Pin 19): Power Supply Voltage. This pin should be
tied to Pin 15.
VREF (Pin 16): Reference Input. The reference input
defines the span of the ADC.
CH1 (Pin 21): Analog Multiplexer Input.
ADCIN (Pin 17): ADC Input. This input is the positive
analog input to the ADC. Connect this pin to MUXOUT for
normal operation.
CH0 (Pin 20): Analog Multiplexer Input.
CH2 (Pin 22): Analog Multiplexer Input.
CH3 (Pin 23): Analog Multiplexer Input.
CH4 (Pin 24): Analog Multiplexer Input.
MUXOUT (Pin 18): MUX Output. This pin is the output of
the multiplexer. Tie to ADCIN for normal operation.
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BLOCK DIAGRA S
LTC1594L
15
LTC1594L
1
CH0
2
CH1
3
CH2
4
CH3
7
COM
MUXOUT
LTC1598L
5
6
ADCIN
VREF VCC
18
16
LTC1598L
CSADC
CSMUX
4-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
CLK
DIN
–
DOUT
9
20 CH0
13
21 CH1
12
22 CH2
14
23 CH3
10
24 CH4
1594L BD
16
ADCIN
VREF VCC
15, 19
CSMUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
CLK
DIN
–
2 CH6
8
17
CSADC
1 CH5
GND
MUXOUT
DOUT
NC
3 CH7
NC
8 COM
10
6
5, 14
7
11
12
13
GND
4, 9
1598L BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
1.4V
VOH
DOUT
VOL
3k
DOUT
TEST POINT
tr
tf
1594L/98L TC02
100pF
1594L/98L TC01
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TEST CIRCUITS
Voltage Waveforms for ten
Voltage Waveforms for DOUT Delay Times, tdDO
LTC1594L/LTC1598L
CLK
CSADC
VIL
tdDO
VOH
DOUT
1
CLK
2
VOL
1594L/98L TC03
B11
DOUT
VOL
t en
Load Circuit for tdis and ten
1594L/98L TC06
Voltage Waveforms for tdis
TEST POINT
CSADC = CSMUX = CS
3k
VCC tdis WAVEFORM 2, ten
DOUT
100pF
VIH
tdis WAVEFORM 1
DOUT
WAVEFORM 1
(SEE NOTE 1)
90%
tdis
1594L/98L TC04
DOUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1594L/98L TC05
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OVERVIEW
The LTC1594L/LTC1598L are 3V micropower, 12-bit
sampling A/D converters that feature 4- and 8-channel
multiplexers respectively. They typically draw only 160µA
of supply current when sampling at 10.5kHz. Supply
current drops linearly as the sample rate is reduced (see
Supply Current vs Sample Rate). The ADCs automatically
power down when not performing conversions, drawing
only leakage current. The LTC1594L is available in a
16-pin narrow SO package and the LTC1598L is packaged in a 24-pin SSOP. Both devices operate on a single
supply from 2.7V to 3.6V.
The LTC1594L/LTC1598L contain a 12-bit, switchedcapacitor ADC, sample-and-hold, serial port and an
external reference input pin. In addition, the LTC1594L
has a 4-channel multiplexer and the LTC1598L provides
an 8-channel multiplexer (see Block Diagram). They can
measure signals floating on a DC common mode voltage
and can operate with reduced spans to 1.5V. Reducing
the spans allow them to achieve 366µV resolution.
The LTC1594L/LTC1598L provide separate MUX output
and ADC input pins to form an ideal MUXOUT/ADCIN
loop which economizes signal conditioning. The MUX
and ADC of the devices can also be controlled individually
through separate chip selects to enhance flexibility.
SERIAL INTERFACE
For this discussion, we will assume that CSMUX and
CSADC are tied together and will refer to them as simply
CS, unless otherwise specified.
The LTC1594L/LTC1598L communicate with the microprocessor and other external circuitry via a synchronous,
half duplex, 4-wire interface (see Operating Sequences in
Figures 1 and 2).
tCYC
CSMUX = CSADC = CS
tsuCS
CLK
EN
D1
DIN
DON’T CARE
D0
D2
DOUT
NULL
BIT
Hi-Z
tSMPL
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0*
Hi-Z
tCONV
CH0 TO
CH7
tON
ADCIN =
MUXOUT
COM = GND
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY
1594F/98F F01
Figure 1. LTC1594L/LTC1598L Operating Sequence Example: CH2, GND
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tCYC
CSMUX = CSADC = CS
tsuCS
CLK
EN
D1
DIN
D0N‘T CARE
D0
D2
DOUT
NULL
BIT
Hi-Z
Hi-Z
DUMMY CONVERSION
tCONV
CH0 TO
CH7
tOFF
ADCIN =
MUXOUT
1594L/98L F02
COM = GND
Figure 2. LTC1594L/LTC1598L Operating Sequence Example: All Channels Off
Data Transfer
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
The LTC1594L/LTC1598L first receive input data and
then transmit back the A/D conversion results (half
duplex). Because of the half duplex operation, DIN and
DOUT may be tied together allowing transmission over
just 3 wires: CS, CLK and DATA (DIN/DOUT).
Data transfer is initiated by a rising chip select (CS)
signal. After CS rises, the input data on the DIN pin is
latched into a 4-bit register on the rising edge of the clock.
More than four input bits can be sent to the DIN pin
without problems, but only the last four bits clocked in
before CS falls will be stored into the 4-bit register. This
4-bit input data word will select the channel in the
muliplexer (see Input Data Word and Tables 1 and 2). To
ensure correct operation, the CS must be pulled low
before the next rising edge of the clock.
Once the CS is pulled low, all channels are simultaneously switched off after a delay of tOFF to ensure a
break-before-make interval, tOPEN. After a delay of tON
(tOFF + tOPEN), the selected channel is switched on,
allowing the ADC in the chip to acquire input signal and
start the conversion (see Figures 1 and 2). After 1 null bit,
the result of the conversion is output on the DOUT line.
The selected channel remains on, until the next falling
edge of CS. At the end of the data exchange, CS should
be brought high. This resets the LTC1594L/LTC1598L
and initiates the next data exchange.
CS
DIN1
DIN2
DOUT1
SHIFT MUX
ADDRESS IN
DOUT2
SHIFT A/D CONVERSION
RESULT OUT
1594L/98L AI01
tSMPL + 1 NULL BIT
Break-Before-Make
The LTC1594L/LTC1598L provide a break-before-make
interval from switching off all the channels simultaneously to switching on the next selected channel once
CS is pulled low. In other words, once CS is pulled low,
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after a delay of tOFF, all the channels are switched off to
ensure a break-before-make interval. After this interval,
the selected channel is switched on allowing signal
transmission. The selected channel remains on until the
next falling edge of CS and the process repeats itself with
the “EN” bit being logic high. If the “EN” bit is logic low,
all the channels are switched off simultaneously after a
delay of tOFF from CS being pulled low and all the
channels remain off until the next falling edge of CS.
Input Data Word
When CS is high, the LTC1594L/LTC1598L clock data
into the DIN inputs on the rising edge of the clock and
store the data into a 4-bit register. The input data words
are defined as follows:
EN
D2
D1
D0
Table 2. Logic Table for the LTC1598L Channel Selection
CHANNEL STATUS
EN
D2
D1
DO
All Off
0
X
X
X
CH0
1
0
0
0
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
CH4
1
1
0
0
CH5
1
1
0
1
CH6
1
1
1
0
CH7
1
1
1
1
Transfer Curve
The LTC1594L/LTC1598L are permanently configured
for unipolar only. The input span and code assignment
for this conversion type is illustrated below.
Transfer Curve
CHANNEL SELECTION
1594L/98L AI02
“EN” Bit
111111111111
•
•
•
000000000001
VIN
000000000000
Multiplexer (MUX) Address
VREF
VREF
4096
VREF–1LSB
1LSB =
VREF–2LSB
1LSB
0V
The first bit in the 4-bit register is an “EN” bit. If the “EN”
bit is a logic high, as illustrated in Figure 1, it enables the
selected channel after a delay of tON when the CS is pulled
low. If the “EN” bit is logic low, as illustrated in Figure 2,
it disables all channels after a delay of tOFF when the CS
is pulled low.
111111111110
1594L/98L • AI03
The 3 bits of input word following the “EN” bit select the
channel in the MUX for the requested conversion. For a
given channel selection, the converter will measure the
voltage of the selected channel with respect to the voltage
on the COM pin. Tables 1 and 2 show the various bit
combinations for the LTC1594L/LTC1598L channel
selection.
Output Code
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.500V)
11111111111111
11111111111110
•
•
•
00000000000001
00000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
2.49939V
2.49878V
•
•
•
0.00061V
0V
1594L/98L • AI04
Table 1. Logic Table for the LTC1594L Channel Selection
CHANNEL STATUS
EN
D2
D1
DO
All Off
0
X
X
X
CH0
1
0
0
0
CH1
1
0
0
1
CH2
1
0
1
0
CH3
1
0
1
1
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(see Figure 3). Therefore the processor port line must be
switched to an input with CS being low to avoid a conflict.
Operation with DIN and DOUT Tied Together
The LTC1594L/LTC1598L can be operated with DIN and
DOUT tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire.
The processor pin connected to this data line should be
configurable as either an input or an output. The
LTC1594L/LTC1598L will take control of the data line
after CS falling and before the 6th falling CLK while the
processor takes control of the data line when CS is high
Separate Chip Selects for MUX and ADC
The LTC1594L/LTC1598L provide separate chip selects,
CSMUX and CSADC, to control MUX and ADC separately.
This feature not only provides the flexibility to select a
particular channel once for multiple conversions (see
Figure 4) but also maximizes the sample rate up to
20ksps (see Figure 5).
tsuCS
CS
1
2
EN
D2
3
4
5
6
CLK
DATA (DIN/DOUT)
D1
D0
B11
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1594L/LTC1598L
• • •
B10
LTC1594L/LTC1598L CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE DATA
LINE AFTER CS FALLING AND
BEFORE THE 6TH FALLING CLK
LTC1594L/LTC1598L TAKES CONTROL OF DATA
LINE AFTER CS FALLING AND BEFORE THE
6TH FALLING CLK
1594L/98L F03
Figure 3. LTC1594L/LTC1598L Operation with DIN and DOUT Tied Together
CSMUX
CSADC
tsuCS
tsuCS
CLK
EN
D1
DIN
DON’T CARE
DOUT
DON’T CARE
D0
D2
D0
NULL
BIT
Hi-Z
tSMPL
B11 B10 B9
B8
B7
B6
tCONV
B5
B4
B3
B2
B1
B0
Hi-Z
tSMPL
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Hi-Z
tCONV
CH0 TO
CH7
tON
ADCIN =
MUXOUT
1594L/98L F04
COM = GND
Figure 4. Selecting a Channel Once for Multiple Conversions
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CSADC
CSMUX
tsuCS
tsuCS
CLK
EN
D1
EN
DIN
B4
B3
B2
B1
D2
NULL
BIT
B0
B11 B10 B9
B8
tSMPL
D1
DON’T CARE
D0
D2
DOUT
EN
D1
DON’T CARE
B7
B6
B5
B4
B3
B2
B1
D0
D2
NULL
BIT
B0
B11 B10 B9
tSMPL
tCONV
B8
B7
B6
B5
B4
B3
B2
B1
D0
B0
tCONV
CH0 TO
CH7
tON
tON
ADCIN =
MUXOUT
1594L/98L F05
COM = GND
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
The MUXOUT and ADCIN pins of the LTC1594L/LTC1598L
form a very flexible external loop that allows Programmable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
In the Typical Applications section, there are a few
examples illustrating how to use the MUXOUT/ADCIN loop
to form a PGA and to antialias filter several analog inputs.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160µA and automatic
shutdown between conversions, the LTC1594L/
LTC1598L achieve extremely low power consumption
over a wide range of sample rates (see Figure 6). The auto
shutdown allows the supply current to drop with reduced
sample rate. Several things must be taken into account to
achieve such a low power consumption.
1000
SUPPLY CURRENT (µA)
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fCLK = 200kHz
100
10
1
0.1
1
10
SAMPLE FREQUENCY (kHz)
100
1594L/98L G01
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
leaving the CLK running to clock the input data word into
MUX. If the CS, DIN and CLK are not running rail-to-rail, the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, DIN and CLK pins
rail-to-rail.
DOUT Loading
Shutdown
The LTC1594L/LTC1598L are equipped with automatic
shutdown features. They draw power when the CS pin is
low. The bias circuits and comparator of the ADC powers
down and the reference input becomes high impedance at
the end of each conversion leaving the CLK running to
clock out the LSB first data or zeroes (see Figures 1 and 2).
When the CS pin is high, the ADC powers down completely
14
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add more than 50µA to the supply current at a 200kHz
clock frequency. An extra 50µA or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any
logic. The (C)(V)(f) currents must be evaluated and the
troublesome ones minimized.
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BOARD LAYOUT CONSIDERATIONS
SAMPLE-AND-HOLD
Grounding and Bypassing
Both the LTC1594L/LTC1598L provide a built-in sampleand-hold (S&H) function to acquire signals through the
selected channel, assuming the ADCIN and MUXOUT
pins are tied together. The S & H of these parts acquire
input signals through the selected channel relative to
COM input during the tSMPL time (see Figure 7).
The LTC1594L/LTC1598L are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1594L/LTC1598L
can also operate with smaller 1µF or less surface mount
or ceramic bypass capacitors. All analog inputs should
be referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Single-Ended Inputs
The sample-and-hold of the LTC1594L/LTC1598L allows
conversion of rapidly varying signals. The input voltage
is sampled during the tSMPL time as shown in Figure 7.
The sampling interval begins after tON time once the CS
is pulled low and continues until the second falling CLK
edge after the CS is low (see Figure 7). On this falling CLK
SAMPLE
tON
HOLD
“ANALOG” INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
CSADC = CSMUX = CS
tCONV
CLK
DIN
EN
D2
D1
DON‘T CARE
D0
DOUT
B11
1ST BIT TEST “COM” INPUT MUST
SETTLE DURING THIS TIME
MUXOUT = ADCIN
CH0 TO CH7
COM
1594L/98L F07
Figure 7. LTC1594L/LTC1598L ADCIN and COM Input Settling Windows
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edge, the S & H goes into hold mode and the conversion
begins. The voltage on the “COM” input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the “COM” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “COM” input this error
would be:
VERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK
Where f(“COM”) is the frequency of the “COM” input
voltage, VPEAK is its peak amplitude and fCLK is the
frequency of the CLK. In most cases, VERROR will not be
significant. For a 60Hz signal on the “COM” input to
generate a 0.5LSB error (305µV) with the converter
running at CLK = 200kHz, its peak value would have to be
5.266mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594L/
LTC1598L have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“Analog” Input Settling
The input capacitor of the LTC1594L/LTC1598L is switched
onto the selected channel input during the tSMPL time (see
Figure 7) and samples the input signal within that time. The
sample phase is at least 1 1/2 CLK cycles before conversion starts. The voltage on the “analog” input must settle
completely within tSMPL. Minimizing RSOURCE+ and C1 will
improve the input settling time. If a large “analog” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
“COM” Input Settling
At the end of the tSMPL, the input capacitor switches to the
“COM” input and conversion starts (see Figures 1 and 7).
During the conversion, the “analog” input voltage is
effectively “held” by the sample-and-hold and will not
affect the conversion result. However, it is critical that the
“COM” input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing RSOURCE– and C2 will improve settling time.
If a large “COM” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodate slower op amps. Most op amps, including
the LT ®1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 7.5µs (“analog” input) which occur at the
maximum clock rate of 200kHz.
Source Resistance
The analog inputs of the LTC1594L/LTC1598L look like a
20pF capacitor (CIN) in series with a 1k resistor (RON) and
a 90Ω channel resistance as shown in Figure 8. CIN gets
switched between the selected “analog” and “COM”
inputs once during each conversion cycle. Large external
source resistors and capacitances will slow the settling
of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
MUX
“ANALOG” R
ON
RSOURCE + INPUT
90Ω
VIN +
MUXOUT
ADCIN
C1
RSOURCE –
LTC1594L
RON LTC1598L
1k
“COM”
INPUT
CIN
20pF
VIN –
C2
1594L/98L F08
Figure 8. Analog Input Equivalent Circuit
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Input Leakage Current
Offset with Reduced VREF
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 200nA (at 85°C) flowing
through a source resistance of 600Ω will cause a voltage
drop of 120µV or 0.2LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve Input Channel Leakage Current
vs Temperature).
The offset of the LTC1594L/LTC1598L has a larger effect
on the output code when the ADCs are operated with
reduced reference voltage. The offset (which is typically
a fixed voltage) becomes a larger fraction of an LSB as the
size of the LSB is reduced. The typical curve of Change in
Offset vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 122µV which is 0.2LSB with a 2.5V
reference becomes 0.5LSB with a 1V reference and
2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system
or by offsetting the “COM” input of the LTC1594L/
LTC1598L.
REFERENCE INPUTS
The reference input of the LTC1594L/LTC1598L is effectively a 50k resistor from the time CS goes low to the end
of the conversion. The reference input becomes a high
impedance node at any other time (see Figure 9). Since
the voltage on the reference input defines the voltage
span of the A/D converter, the reference input should be
driven by a reference with low ROUT (ex. LT1004, LT1019
and LT1021) or a voltage source with low ROUT.
REF+
1
LTC1594L
LTC1598L
ROUT
VREF
GND
4
1594L/98L F09
Figure 9. Reference Input Equivalent Circuit
Reduced Reference Operation
The effective resolution of the LTC1594L/LTC1598L can
be increased by reducing the input span of the converters. The LTC1594L/LTC1598L exhibit good linearity and
gain over a wide range of reference voltages (see typical
curves Change in Linearity vs Reference Voltage and
Change in Gain vs Reference Voltage). However, care
must be taken when operating at low values of VREF
because of the reduced LSB step size and the resulting
higher accuracy requirement placed on the converters.
The following factors must be considered when operating at low VREF values:
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Noise with Reduced VREF
The total input referred noise of the LTC1594L/LTC1598L
can be reduced to approximately 400µV peak-to-peak
using a ground plane, good bypassing, good layout
techniques and minimizing noise on the reference inputs.
This noise is insignificant with a 5V reference but will
become a larger fraction of an LSB as the size of the LSB
is reduced.
For operation with a 2.5V reference, the 400µV noise is
only 0.66LSB peak-to-peak. In this case, the LTC1594L/
LTC1598L noise will contribute virtually no uncertainty to
the output code. However, for reduced references the
noise may become a significant fraction of an LSB and
cause undesirable jitter in the output code. For example,
with a 1.25V reference this same 400µV noise is 1.32LSB
peak-to-peak. This will reduce the range of input voltages
over which a stable output code can be achieved by 1LSB.
If the reference is further reduced to 1V, the 400µV noise
becomes equal to 1.65LSBs and a stable code may be
difficult to achieve. In this case, averaging multiple
readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF or VIN) will
add to the internal noise. The lower the reference voltage
to be used the more critical it becomes to have a clean,
noise free setup.
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Conversion Speed with Reduced VREF
Effective Number of Bits
With reduced reference voltages, the LSB step size is
reduced and the LTC1594L/LTC1598L internal comparator overdrive is reduced. Therefore, it may be necessary
to reduce the maximum CLK frequency when low values
of VREF are used.
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
0
TA = 25°C
VCC = 2.7V
VREF = 2.5V
fIN = 3.05kHz
fCLK = 120kHz
fSMPL = 7.5kHz
MAGNITUDE (dB)
– 20
– 40
12
74
11
68
10
62
9
56
8
50
S/(N + D) (dB)
The LTC1594L/LTC1598L have exceptional sampling
capability. Fast Fourier Transform (FFT) test techniques
are used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 10 shows a typical LTC1594L/LTC1598L
plot.
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 10.5kHz with a 5V supply, the LTC1594L/
LTC1598L maintain above 10.7 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
EFFECTIVE NUMBER OF BITS (ENOBs)
DYNAMIC PERFORMANCE
ENOB = [S/(N + D) – 1.76]/6.02
7
6
5
4
3
TA = 25°C
VCC = 2.7V
fCLK = 200kHz
fSMPL = 10.5kHz
2
1
0
– 60
1
10
INPUT FREQUENCY (kHz)
– 80
100
1594L/98L G09
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
– 100
– 120
0
0.5
1.0
1.5 2.0 2.5 3.0
FREQUENCY (kHz)
3.5
4.0
1594L/98L G13
Figure 10. LTC1594L/LTC1598L Nonaveraged,
4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other frequency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spectral content with a 10.5kHz sampling rate.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling
frequency. THD is defined as:
THD = 20log
V22 + V32 + V42 + ... + VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through the Nth harmonics. The typical THD
15948lfb
18
LTC1594L/LTC1598L
U
W
U
U
APPLICATIONS INFORMATION
specification in the Dynamic Accuracy table includes the
2nd through 5th harmonics. With a 1kHz input signal, the
LTC1594L/LTC1598L have typical THD of 78dB with
VCC = 2.7V.
(
)
amplitude fa ± fb
IMD fa ± fb = 20log
amplitude at fa
(
)
Intermodulation Distortion
Peak Harmonic or Spurious Noise
If the ADC input signal consists of more than one
spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD)
in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal
input at a different frequency.
The peak harmonic or spurious noise is the largest
spectral component excluding the input signal and DC.
This value is expressed in dBs relative to the RMS value
of a full-scale input signal.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa +
fb) and (fa – fb) while 3rd order IMD terms include (2fa +
fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitudes, the value (in dB) of the
2nd order IMD products can be expressed by the following formula:
The full-power bandwidth is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Full-Power and Full-Linear Bandwidth
The full-linear bandwidth is the input frequency at which
the effective bits rating of the ADC falls to 11 bits. Beyond
this frequency, distortion of the sampled input signal
increases. The LTC1594L/LTC1598L have been designed
to optimize input bandwidth, allowing the ADCs to
undersample input signals with frequencies above the
converters’ Nyquist Frequency.
U
TYPICAL APPLICATIONS N
Microprocessor Interfaces
Motorola SPI (MC68HC05)
The LTC1594L/LTC1598L can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats including
MICROWIRE, SPI and QSPI. If an MPU without a dedicated serial port is used, then three of the MPU’s parallel
port lines can be programmed to form the serial link to the
LTC1594L/LTC1598L. Included here is one serial interface
example.
The MC68HC05 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data
register starts the SPI process. With three
8-bit transfers the A/D result is read into the MPU. The
second 8-bit transfer clocks B11 through B7 of the A/D
conversion result into the processor. The third 8-bit transfer clocks the remaining bits B6 through B0 into the MPU.
ANDing the second byte with 1FHEX clears the three most
significant bits and ANDing the third byte with FEHEX clears
the least significant bit. Shifting the data to the right by one
bit results in a right justified word.
15948lfb
19
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
MC68HC05 CODE
LDA #$52
Configuration data for serial peripheral
control register (Interrupts disabled, output
enabled, master, Norm = 0, Ph = 0, Clk/16)
Load configuration data into location $0A (SPCR)
Configuration data for I/O ports
(all bits are set as outputs)
Load configuration data into Port A DDR ($04)
Load configuration data into Port B DDR ($05)
Load configuration data into Port C DDR ($06)
Put DIN word for LTC1598L into Accumulator
(CH0 with respect to GND)
Load DIN word into memory location $50
Bit 0 Port C ($02) goes high (CS goes high)
Load DIN word at $50 into Accumulator
Load DIN word into SPI data register ($0C) and
start clocking data
Test status of SPIF bit in SPI status register ($0B)
STA $0A
LDA #$FF
STA
STA
STA
LDA
$04
$05
$06
#$08
STA $50
START BSET 0,$02
LDA $50
STA $0C
LOOP1 TST $0B
BPL LOOP1
BCLR 0,$02
LDA $0C
STA $0C
LOOP2 TST $0B
BPL LOOP2
LDA $0C
STA $0C
AND #$IF
STA $00
LOOP3 TST $0B
BPL LOOP3
LDA $0C
AND #$FE
STA $01
JMP START
Loop if not done with transfer to previous instruction
Bit 0 Port C ($02) goes low (CS goes low)
Load contents of SPI data register into Accumulator
Start next SPI cycle
Test status of SPIF
Loop if not done
Load contents of SPI data register into Accumulator
Start next SPI cycle
Clear 3 MSBs of first DOUT word
Load Port A ($00) with MSBs
Test status of SPIF
Loop if not done
Load contents of SPI data register into Accumulator
Clear LSB of second DOUT word
Load Port B ($01) with LSBs
Go back to start and repeat program
Data Exchange Between LTC1598L and MC68HC05
CSMUX
= CSADC
= CS
CLK
EN
DIN
D2
D1
DO
DON‘T CARE
DOUT
B11 B10
MPU
TRANSMIT
WORD
0
MPU
RECEIVED
WORD
?
0
0
0
EN
D2
D1
D0
X
X
X
?
?
X
B8
B7
X
X
X
B6
X
B5
B4
B3
B2
B1
B0
B1
X
X
X
X
X
X
X
B1
B0
B1
BYTE 2
BYTE 1
?
X
B9
?
?
?
?
?
?
0
B11 B10
BYTE 3
B9
B8
B7
B6
BYTE 2
BYTE 1
B2
B5
B4
B2
B3
1594L/98L TA03
BYTE 3
Hardware and Software Interface to Motorola MC68HC05
DOUT FROM LTC1598L STORED IN MC68HC05 RAM
MSB
#00
0
0
0
B11
B10
B9
B8
B7
CSMUX
BYTE 1
CSADC
ANALOG
INPUTS
LSB
#01
B6
B5
B4
B3
B2
B1
B0
0
BYTE 2
LTC1598L CLK
C0
MC68HC05
SCK
DIN
MOSI
DOUT
MISO
1594L/98L TA04
15948lfb
20
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
MULTICHANNEL A/D USES A SINGLE
ANTIALIASING FILTER
than 1LSB of error due to offsets and bias currents. The
filter’s noise and distortion are less than –72dB for a
100Hz, 2VP-P offset sine input.
This circuit demonstrates how the LTC1598L’s independent analog multiplexer can simplify design of a 12-bit
data acquisition system. All eight channels are MUXed into
a single 1kHz, 4th order Sallen-Key antialiasing filter,
which is designed for single supply operation. Since the
LTC1598L’s data converter accepts inputs from ground to
the positive supply, rail-to-rail op amps were chosen for
the filter to maximize dynamic range. The LT1368 dual railto-rail op amp is designed to operate with 0.1µF load
capacitors (C1 and C2). These capacitors provide frequency compensation for the amplifiers and help reduce
the amplifier’s output impedance and improve supply
rejection at high frequencies. The filter contributes less
The combined MUX and A/D errors result in an integral
nonlinearity error of ± 3LSB (maximum) and a differential
nonlinearity error of ±3/4LSB (maximum). The typical
signal-to-noise plus distortion ratio is 68dB, with approximately –78dB of total harmonic distortion. The LTC1598L
is programmed through a 4-wire serial interface that is
compatible with MICROWIRE, SPI and QSPI. Maximum
serial clock speed is 200kHz, which corresponds to a
10.5kHz sampling rate.
The complete circuit consumes approximately 600µA
from a single 3V supply.
Simple Data Acquisition System Takes Advantage of the LTC1598L’s
MUXOUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion
3.3V
R1
7.5k
R2
7.5k
3
C1
0.03µF
C2
0.015µF
+
R4
7.5k
1
1/2 LT1368
2
R3
7.5k
C8
0.01µF
8
C4
0.03µF
–
C3
0.1µF
5
C5
0.015µF
+
1/2 LT1368
6
–
4
7
C6
0.1µF
3.3V
18
LTC1598L
MUXOUT
C7
1µF
15, 19
17
16
ADCIN
VREF VCC
20 CH0
21 CH1
CSADC
22 CH2
23 CH3
24 CH4
1 CH5
2 CH6
CSMUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
–
CLK
DIN
DOUT
3 CH7
NC
8 COM
GND
4, 9
NC
10
6
5, 14
7
11
SERIAL DATA LINK
MICROWIRE AND SPI
COMPATIBLE
12
13
1594L/98L TA05
15948lfb
21
LTC1594L/LTC1598L
U
TYPICAL APPLICATIONS N
Using MUXOUT/ADCIN Loop as PGA
This figure shows the LTC1598L’s MUXOUT/ADCIN pins
and an LT1368 being used to create a single channel PGA
with eight noninverting gains. Combined with the LTC1391,
the system can expand to eight channels and eight gains
for each channel. Using the LTC1594L, the PGA is reduced
to four gains. The output of the LT1368 drives the ADCIN
and the resistor ladder. The resistors above the selected
MUX channel form the feedback for the LT1368. The gain
for this amplifier is RS1/RS2 + 1. RS1 is the summation of
the resistors above the selected MUX channel and RS2 is
the summation of the resistors below the selected MUX
channel. If CH0 is selected, the gain is 1 since RS1 is 0.
Table 1 shows the gain for each MUX channel. The LT1368
dual rail-to-rail op amp is designed to operate with 0.1µF
load capacitors. These capacitors provide frequency compensation for the amplifiers, help reduce the amplifiers’
output impedance and improve supply rejection at high
frequencies. Because the LT1368’s IB is low, the RON of the
selected channel will not affect the gain given by the
formula above.
Using the MUXOUT/ADCIN Pins of the LTC1598L to Form a PGA.
The LTC1391 MUX Allows Eight Input Channels to be Digitized
3V
1µF
LTC1391
1
2
3
4
5
6
7
8
CH0
CH1
CH2
V+
16
15
D
14
V–
13
CH3
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
3V
12
3(5)
+
8
1/2 LT1368
2(6)
–
1µF
1(7)
3V
0.1µF
4
17
ADCIN
11
10
9
64R
20
CH0
32R
21
CH1
16R
22
CH2
8R
23
CH3
4R
24
CH4
2R
1
CH5
R
2
CH6
R
3
CH7
16
15, 19
VREF VCC
CSADC
CSMUX
8-CHANNEL
MUX
+
12-BIT
SAMPLING
ADC
–
CLK
DOUT
DIN
LTC1598L
18
8
MUXOUT
COM
NC
GND
NC
1µF
10
6
5, 14
11
µP/µC
7
12
13
4, 9
= DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L
1594L/98L TA06
15948lfb
22
LTC1594L/LTC1598L
U
PACKAGE DESCRIPTION
G Package
24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.65
(.0256)
BSC
0.55 – 0.95
(.022 – .037)
0.05
(.002)
MIN
0.22 – 0.38
(.009 – .015)
TYP
G24 SSOP 0204
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
.386 – .394
(9.804 – 10.008)
NOTE 3
.045 ±.005
.050 BSC
16
N
15
14
13
12
11
10
9
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
.030 ±.005
TYP
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
2
3
4
5
6
.053 – .069
(1.346 – 1.752)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
8
.004 – .010
(0.101 – 0.254)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
7
.050
(1.270)
BSC
S16 0502
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
15948lfb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1594L/LTC1598L
U
TYPICAL APPLICATION
Using the LTC1598L and LTC1391 as an 8-Channel Differential 12-Bit ADC System
3V
18
MUXOUT
20
CH0
21
CH1
22
CH2
23
CH3
24
CH4
1
CH5
2
CH6
16
3
CH7
15
D
14
–
V
13
8
3V
1µF
LTC1391
CH0
1
2
3
4
5
6
7
CH7
8
CH0
CH1
CH2
V+
CH3
DOUT
CH4
DIN
CH5
CS
CH6
CLK
CH7
GND
17
ADCIN
16
15, 19
VREF VCC
CSADC
CSMUX
8-CHANNEL
MUX
COM
+
12-BIT
SAMPLING
ADC
–
CLK
DIN
DOUT
LTC1598L
GND
NC
NC
1µF
10
6
5, 14
7
11
12
13
4, 9
12
11
10
9
DIN
CLK
CS
DOUT
= DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L
1594L/98L TA07
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Multiplexed 3V, 12-Bit ADC
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Multiplexed 5V, 12-Bit ADC
8-Channel 12-Bit Serial I/O
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Low Power, Small Size, Low Cost
15948lfb
24
Linear Technology Corporation
LT/TP 0404 1K REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
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