LTC1604
High Speed, 16-Bit, 333ksps
Sampling A/D Converter
with Shutdown
DESCRIPTION
FEATURES
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A Complete, 333ksps 16-Bit ADC
90dB S/(N+D) and –100dB THD (Typ)
Power Dissipation: 220mW (Typ)
No Pipeline Delay
No Missing Codes over Temperature
Nap (7mW) and Sleep (10μW) Shutdown Modes
Operates with Internal 15ppm/°C Reference
or External Reference
True Differential Inputs Reject Common Mode Noise
5MHz Full Power Bandwidth
±2.5V Bipolar Input Range
36-Pin SSOP Package
The LTC®1604 is a 333ksps, 16-bit sampling A/D converter that draws only 220mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
The LTC1604’s full-scale input range is ±2.5V. Outstanding AC performance includes 90dB S/(N+D) and –100dB
THD at a sample rate of 333ksps.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
APPLICATIONS
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Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has μP compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
L, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
10μF
2.2μF
10Ω
+
3
36
AVDD
VREF
5V 10μF
5V
+
35
AVDD
9
10μF
+
LTC1604 4096 Point FFT
0
10
DVDD
–20
SHDN 33
+
7.5k
4.375V
1.75X
2.5V
REF
47μF
CS 32
μP
CONTROL
LINES
CONVST 31
RD 30
BUSY 27
OVDD 29
+
1 AIN+
DIFFERENTIAL
ANALOG INPUT
±2.5V
+
2 AIN
–
–
OGND 28
16-BIT
SAMPLING
ADC
AGND
5
AGND
6
OUTPUT
BUFFERS
B15 TO B0
AGND
7
–40
–60
–80
–100
–120
16-BIT
PARALLEL
BUS
–140
11 TO 26
AGND VSS
8
D15 TO D0
5V OR
3V
10μF
AMPLITUDE (dB)
4 REFCOMP
CONTROL
LOGIC
AND
TIMING
fSAMPLE = 333kHz
fIN = 100kHz
SINAD = 89dB
THD = –96dB
DGND
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
1604 TA01
34
1604 TA02
+
10μF
–5V
1604fa
1
LTC1604
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
ORDER
PART NUMBER
TOP VIEW
Supply Voltage (VDD) ..................................................6V
Negative Supply Voltage (VSS) ..................................–6V
Total Supply Voltage (VDD to VSS) ............................12V
Analog Input Voltage
(Note 3) ..........................(VSS – 0.3V) to (VDD + 0.3V)
VREF Voltage (Note 4)................... –0.3V to (VDD + 0.3V)
REFCOMP Voltage (Note 4).......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4)..................... –0.3V to 10V
Digital Output Voltage .................. –0.3V to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1604C ................................................ 0°C to 70°C
LTC1604I..............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
AIN+
1
36 AVDD
AIN–
2
35 AVDD
VREF
3
34 VSS
REFCOMP
4
33 SHDN
AGND
5
32 CS
AGND
6
31 CONV
AGND
7
30 RD
AGND
8
29 OVDD
DVDD
9
28 OGND
DGND 10
27 BUSY
D15 (MSB) 11
26 D0
D14 12
25 D1
D13 13
24 D2
D12 14
23 D3
D11 15
22 D4
D10 16
21 D5
D9 17
20 D6
D8 18
19 D7
LTC1604CG
LTC1604IG
LTC1604ACG
LTC1604AIG
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Military grade parts.
CONVERTER CHARACTERISTICS
PARAMETER
With Internal Reference (Notes 5, 6)
CONDITIONS
l
Resolution (No Missing Codes)
Integral Linearity Error
(Note 7)
Transition Noise
(Note 8)
MIN
LTC1604
TYP
15
16
l
MAX
MIN
16
±1
±4
Offset Error
(Note 9)
Offset Tempco
(Note 9)
Full-Scale Error
Internal Reference
External Reference
Full-Scale Tempco
IOUT(Reference) = 0, Internal Reference
±0.05
16
±0.5
0.7
l
LTC1604A
TYP
MAX
Bits
±2
0.7
±0.125
±0.05
0.5
±0.125
±0.125
±15
LSB
LSB
±0.125
0.5
±0.25
±0.25
UNITS
%
ppm/°C
±0.25
±0.25
±15
%
%
ppm/°C
ANALOG INPUT
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 2)
4.75 ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ –4.75V,
VSS ≤ (AIN–, AIN+) ≤ AVDD
IIN
Analog Input Leakage Current
CS = High
CIN
Analog Input Capacitance
Between Conversions
During Conversions
tACQ
tAP
tjitter
Sample-and-Hold Acquisition Delay Time Jitter
CMRR
MIN
TYP
MAX
±2.5
l
UNITS
V
±1
μA
43
5
pF
pF
Sample-and-Hold Acquisition Time
380
ns
Sample-and-Hold Acquisition Delay Time
–1.5
ns
Analog Input Common Mode Rejection Ratio
–2.5V < (AIN– = AIN+) < 2.5V
5
psRMS
68
dB
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2
LTC1604
DYNAMIC ACCURACY
(Note 5)
SYMBOL PARAMETER
CONDITIONS
S/N
5kHz Input Signal
100kHz Input Signal
Signal-to-Noise Ratio
S/(N + D) Signal-to-(Noise + Distortion) Ratio
THD
Total Harmonic Distortion
Up to 5th Harmonic
LTC1604
MIN
TYP MAX
l
90
90
5kHz Input Signal
100kHz Input Signal (Note 10)
l
90
89
5kHz Input Signal
100kHz Input Signal
l
–100
–94
LTC1604A
MIN
TYP MAX
87
84
UNITS
90
90
dB
dB
90
89
dB
dB
–100
–94
–88
dB
dB
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
96
96
dB
IMD
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
–88
–88
dB
5
5
MHz
350
350
kHz
Full Power Bandwidth
Full Linear Bandwidth (S/(N + D) ≥ 84dB
INTERNAL REFERENCE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VREF Output Voltage
IOUT = 0
2.475
2.500
2.515
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75 ≤ VDD ≤ 5.25V
–5.25V ≤ VSS ≤ –4.75V
0.01
0.01
LSB/V
LSB/V
VREF Output Resistance
0 ≤ |IOUT| ≤ 1mA
7.5
kΩ
REFCOMP Output Voltage
IOUT = 0
DIGITAL INPUTS AND DIGITAL OUTPUTS
4.375
UNITS
V
V
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
l
VIL
Low Level Input Voltage
VDD = 4.75V
l
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
μA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V, IOUT = –10μA
VDD = 4.75V, IOUT = –400μA
l
VDD = 4.75V, IOUT = 160μA
VDD = 4.75V, IOUT = 1.6mA
l
TYP
MAX
2.4
UNITS
V
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
Hi-Z Output Leakage D15 to D0
VOUT = 0V to VDD, CS High
l
±10
μA
COZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 11)
l
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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3
LTC1604
POWER REQUIREMENTS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
(Notes 12, 13)
4.75
5.25
V
VSS
Negative Supply Voltage
(Note 12)
–4.75
–5.25
V
IDD
Positive Supply Current
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
l
18
1.5
1
30
2.4
100
mA
mA
μA
ISS
Negative Supply Current
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
l
26
1
1
40
100
100
mA
μA
μA
PD
Power Dissipation
Nap Mode
Sleep Mode
CS = RD = 0V
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
l
220
7.5
0.01
350
12
1
mW
mW
mW
TYP
MAX
UNITS
2.45
2.8
TIMING CHARACTERISTICS
SYMBOL
(Note 5)
PARAMETER
CONDITIONS
MIN
fSMPL(MAX)
Maximum Sampling Frequency
l
tCONV
Conversion Time
l
tACQ
Acquisition Time
tACQ+CONV
Throughput Time (Acquisition + Conversion)
t1
CS to RD Setup Time
(Note 11)
333
1.5
kHz
μs
l
480
ns
l
3
μs
(Notes 11, 12)
l
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Notes 11, 12)
l
10
ns
t3
SHDN↓ to CS↑ Setup Time
(Notes 11, 12)
l
10
ns
l
40
t4
SHDN↑ to CONVST↓ Wake-Up Time
CS = Low (Note 12)
t5
CONVST Low Time
(Note 12)
t6
CONVST to BUSY Delay
CL = 25pF
t7
Data Ready Before BUSY↑
400
ns
ns
36
l
80
60
ns
ns
l
32
ns
ns
t8
Delay Between Conversions
(Note 12)
l
200
ns
t9
Wait Time RD↓ After BUSY↑
(Note 12)
l
–5
ns
t10
Data Access Time After RD↓
CL = 25pF
CL = 100pF
t11
Bus Relinquish Time
l
l
LTC1604C
LTC1604I
l
l
40
50
60
ns
ns
45
60
75
ns
ns
50
60
70
75
ns
ns
ns
t12
RD Low Time
(Note 12)
l
t10
ns
t13
CONVST High Time
(Note 12)
l
40
ns
t14
Aperture Delay of Sample-and-Hold
2
ns
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4
LTC1604
TIMING CHARACTERISTICS
(Note 5)
The l denotes specifications that apply over the full operating temperature
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = –5V, fSMPL = 333kHz, and tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions. See Figure 17 for
histogram.
Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
2.0
1.0
100
1.5
0.8
90
0.6
80
0.4
70
DNL (LSB)
0.5
0.0
–0.5
0.2
SINAD (dB)
1.0
INL (LSB)
S/(N + D) vs Input Frequency
and Amplitude
0.0
–0.2
40
30
20
–1.5
–0.8
10
–2.0
–32768
–1.0
0
16384
32767
0
–32768
–16384
CODE
0
16384
VIN = –40dB
50
–0.6
–16384
VIN = –20dB
60
–0.4
–1.0
VIN = 0dB
32767
1k
10k
100k
FREQUENCY (Hz)
CODE
1604 G11
1M
1604 G01
1604 G10
Signal-to-Noise Ratio vs
Input Frequency
SIGNAL-TO-NOISE RATIO (dB)
90
80
70
60
50
40
30
20
10
10k
100k
FREQUENCY (Hz)
1M
1604 G03
0
0
–10
–20
–30
–40
–50
–60
–70
–80
THD
3RD
–90
–100
–110
1k
2ND
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G04
SPURIOUS-FREE DYNAMIC RANGE (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
100
0
1k
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1k
10k
100k
INPUT FREQUENCY (Hz)
1M
1604 G05
1604fa
5
LTC1604
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Feedthrough vs
Ripple Frequency
0
fSAMPLE = 333kHz
fIN1 = 29.3kHz
fIN2 = 32.4kHz
–20
AMPLITUDE (dB)
–40
–60
–80
–100
–120
–140
AMPLITUDE OF POWER SUPPLY
FEEDTHROUGH (dB)
0
20
40
60 80 100 120 140 160
FREQUENCY (kHz)
80
fSAMPLE = 333kHz
VRIPPLE = 10mV
–20
–40
–60
–80
AVDD
–100
V SS
–120
0
Input Common Mode Rejection
vs Input Frequency
COMMON MODE REJECTION (dB)
Intermodulaton Distortion
70
60
50
40
30
20
10
0
1k
10k
100k
INPUT FREQUENCY (Hz)
1604 G06
1M
1k
10k
100k
INPUT FREQUENCY (Hz)
1604 G07
1M
1604G09
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
difference voltage between AIN+ and AIN– with a differential range of ±2.5V. AIN+ has a ±2.5V input range when
AIN– is grounded.
OGND (Pin 28): Digital Ground for Output Drivers.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with AIN+.
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with
2.2μF tantalum in parallel with 0.1μF ceramic.
REFCOMP (Pin 4): 4.375 Reference Compensation Pin.
Bypass to AGND with 47μF tantalum in parallel with 0.1μF
ceramic.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10μF tantalum in parallel with 0.1μF ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
OVDD (Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10μF tantalum in parallel with 0.1μF
ceramic.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when
CS is low.
CS (Pin 32): The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
VSS (Pin 34): –5V Negative Supply. Bypass to AGND with
10μF tantalum in parallel with 0.1μF ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10μF tantalum in parallel with 0.1μF ceramic.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10μF tantalum in parallel with 0.1μF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.
1604fa
6
LTC1604
FUNCTIONAL BLOCK DIAGRAM
10μF
2.2μF
10Ω
+
3
VREF
5V 10μF
+
36
AVDD
5V
35
9
AVDD
10μF
+
10
DVDD
DGND
SHDN 33
4 REFCOMP
+
7.5k
1.75X
4.375V
CS 32
CONTROL
LOGIC
AND
TIMING
2.5V
REF
μP
CONTROL
LINES
CONVST 31
RD 30
BUSY 27
47μF
OVDD 29
+
1 AIN+
DIFFERENTIAL
ANALOG INPUT
±2.5V
2 AIN–
OGND 28
+
16-BIT
SAMPLING
ADC
–
AGND
5
AGND
6
OUTPUT
BUFFERS
B15 TO B0
AGND
7
16-BIT
PARALLEL
BUS
D15 TO D0
11 TO 26
AGND VSS
8
5V OR
3V
10μF
1604 TA01
34
+
10μF
–5V
TEST CIRCUIT
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
DN
1k
DN
1k
CL
(A) Hi-Z TO VOH AND VOL TO VOH
DN
DN
1k
CL
(B) Hi-Z TO VOL AND VOH TO VOL
1604 TC01
(A) VOH TO Hi-Z
CL
CL
(B) VOL TO Hi-Z
1604 TC02
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LTC1604
APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1604 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) resets. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSMPL capacitors to ground,
transferring the differential analog input charge onto the
SAMPLE
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 2.45μs and a maximum
conversion time of 2.8μs over the full temperature range.
No external adjustments are required. The guaranteed
maximum acquisition time is 480ns. In addition, a throughput time (acquisition + conversion) of 3μs and a minimum
sampling rate of 333ksps are guaranteed.
The LTC1604 operates on ±5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1604 recognize
3V or 5V inputs. The LTC1604 has a dedicated output
supply pin (OVDD) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.
HOLD
ZEROING SWITCHES
CSMPL
AIN–
DIGITAL INTERFACE
3V Input/Output Compatible
CSMPL
AIN+
summing junctions. This input charge is successively
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 16-bit data word) which
represent the difference of AIN+ and AIN– are loaded into
the 16-bit output latches.
HOLD
SAMPLE
HOLD
HOLD
+CDAC
+
–CDAC
COMP
–
+VDAC
Power Shutdown
–VDAC
16
SAR
OUTPUT
LATCHES
t
t
t
D15
D0
1604 F01
Figure 1. Simplified Block Diagram
The LTC1604 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up
time from Nap to active is 200ns. In Sleep mode all bias
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8
LTC1604
APPLICATIONS INFORMATION
currents are shut down and only leakage current remains
(about 1μA). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47μF
capacitor.
SHDN
t3
CS
1604 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
SHDN
t4
CONVST
1604 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated,
it cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
CS
t2
CONVST
t1
RD
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time tCONV), accuracy is unaffected. For best results, keep t5 less than 500ns or greater
than tCONV.
1604 F03
Figure 3. CS top CONVST Setup Timing
CHANGE IN DNL (LSB)
4
3
2
tCONV
tACQ
1
0
0
400
800
1200
1600
2000
2400
2800
CONVST LOW TIME, t5 (ns)
1604 F04
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD
are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are
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9
LTC1604
APPLICATIONS INFORMATION
t CONV
CS = RD = 0
t5
CONVST
t6
t8
BUSY
t7
DATA
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
DATA (N – 1)
D15 TO D0
1604 F05
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
CS = RD = 0
tCONV
t8
t5
t13
CONVST
t6
t6
BUSY
t7
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F06
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t13
CS = 0
tCONV
t5
t8
CONVST
t6
BUSY
t9
RD
t 12
t 11
t 10
DATA
DATA N
D15 TO D0
1604 F07
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
1604fa
10
LTC1604
APPLICATIONS INFORMATION
CS = 0
t8
t CONV
RD = CONVST
t6
t 11
BUSY
t 10
t7
DATA (N – 1)
D5 TO D0
DATA
DATA N
D15 TO D0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F08
Figure 8. Mode 2. Slow Memory Mode Timing
t CONV
CS = 0
t8
RD = CONVST
t6
t 11
BUSY
t 10
DATA
DATA N
D15 TO D0
DATA (N – 1)
D15 TO D0
1604 F09
Figure 9. ROM Mode Timing
in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared data bus.
DIFFERENTIAL ANALOG INPUTS
In slow memory and ROM modes (Figures 8 and 9) CS
is tied low and CONVST and RD are tied together. The
MPU starts the conversion and reads the output with the
combined CONVST-RD signal. Conversions are started
by the MPU or DSP (no external sample clock is needed).
Driving the Analog Inputs
In slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (=CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor
can read the new result and initiate another conversion.
The differential analog inputs of the LTC1604 are easy
to drive. The inputs may be driven differentially or as a
single-ended input (i.e., the AIN– input is grounded). The
AIN+ and AIN– inputs are sampled at the same instant.
Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low, then the
LTC1604 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
1604fa
11
LTC1604
ACQUISITION TIME (μs)
APPLICATIONS INFORMATION
10
LT®1007: Low Noise Precision Amplifier. 2.7mA supply
current, ±5V to ±15V supplies, gain bandwidth product
8MHz, DC applications.
1
LT1097: Low Cost, Low Power Precision Amplifier. 300μA
supply current, ±5V to ±15V supplies, gain bandwidth
product 0.7MHz, DC applications.
0.1
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current, ±5V to ±15V supplies, low noise and low
distortion.
0.01
1
10
100
1k
SOURCE RESISTANCE (Ω)
10k
1604 F10
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA supply
current, ±5V to ±15V supplies, good AC/DC specs.
Figure 10. tACQ vs Source Resistance
LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA supply current, good AC/DC specs.
starts (settling time must be 200ns for full throughput
rate).
LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback
Amplifiers. 6.3mA supply current per amplifier, good AC/
DC specs.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (
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