LTC1609
16-Bit, 200ksps, Serial ADC
with Multiple Input Ranges
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FEATURES
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DESCRIPTIO
The LTC ®1609 is a 200ksps, serial sampling 16-bit A/D
converter that draws only 65mW (typical) from a single 5V
supply. This easy-to-use device includes a sample-andhold, a precision reference, a switched capacitor successive approximation A/D and trimmed internal clock.
Sample Rate: 200ksps
Input Ranges
Unipolar: 0V to 10V, 0V to 5V and 0V to 4V
Bipolar: ±10V, ±5V and ±3.3V
Guaranteed No Missing Codes
Serial I/O
Single 5V Supply
Power Dissipation: 65mW Typ
Power Down Mode: 50µW
SNR: 87dB Typ
Operates with Internal or External Reference
28-Pin SSOP and 20-Pin SO Packages
Improved 2nd Source to ADS7809 and AD977A
The input range is specified for bipolar inputs of ±10V,
±5V and ±3.3V and unipolar inputs of 0V to 10V, 0V to 5V
and 0V to 4V. Maximum DC specs include ±2LSB INL and
16-bit no missing codes over temperature. It has a typical
signal-to-noise ratio of 87dB.
The ADC has a high speed serial interface. The serial
output data can be clocked out using either the internal
serial shift clock or be clocked out by an external shift
clock. A separate convert start input (R/C) and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
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APPLICATIO S
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Industrial Process Control
Multiplexed Data Acquisition Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
200kHz, 16-Bit Serial Sampling ADC Configured for ±10V Inputs
200Ω
1
2
100Ω
3
33.2k
4
5
2.5V
6
+
2.2µF
2.5V
7
+
2.2µF
8
9
10
11
12
13
14
R1IN
VDIG
AGND1
VANA
R2IN
PWRD
R3IN
BUSY
NC
LTC1609
CAP
CS
NC
REF
NC
NC
R/C
AGND2
NC
NC
TAG
NC
NC
SB/BTC
DATA
EXT/INT DATACLK
DGND
SYNC
28
27
5V
+
10µF
26
Nonaveraged 4096 Point FFT Plot
0.1µF
0
fSAMPLE = 200kHz
fIN = 1kHz
SINAD = 87.2dB
THD = –100.1dB
25
–20
24
23
MAGNITUDE (dB)
ANALOG INPUT
– 10V TO 10V
22
21
20
19
SERIAL INTERFACE
18
17
–40
–60
–80
–100
–120
16
–130
0
15
25
50
75
100
FREQUENCY (kHz)
1609 TA01
1609 G06
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LTC1609
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
VANA .......................................................................... 7V
VDIG to VANA ........................................................... 0.3V
VDIG ........................................................................... 7V
Ground Voltage Difference
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
R1IN, R2IN, R3IN ................................................ ±25V
CAP ............................ VANA + 0.3V to AGND2 – 0.3V
REF .................................... Indefinite Short to AGND2
Momentary Short to VANA
Digital Input Voltage (Note 4) ........ DGND – 0.3V to 10V
Digital Output Voltage ........ DGND – 0.3V to VDIG + 0.3V
Power Dissipation .............................................. 500mW
Operating Ambient Temperature Range
LTC1609AC/LTC1609C ............................ 0°C to 70°C
LTC1609AI/LTC1609I ......................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
ORDER PART
NUMBER
R1IN
1
28 VDIG
AGND1
2
27 VANA
R2IN
3
26 PWRD
R3IN
4
25 BUSY
NC
5
24 CS
R2IN 3
18 PWRD
23 NC
R3IN 4
17 BUSY
CAP 5
16 CS
REF 6
15 R/C
6
CAP
7
REF
8
21 R/C
AGND2
9
20 NC
NC 11
19 TAG
18 NC
SB/BTC 12
17 DATA
EXT/INT 13
16 DATACLK
DGND 14
R1IN 1
20 VDIG
AGND1 2
19 VANA
22 NC
NC
NC 10
TOP VIEW
LTC1609CG
LTC1609IG
LTC1609CSW
LTC1609ISW
LTC1609ACSW
LTC1609AISW
AGND2 7
14 TAG
SB/BTC 8
13 DATA
EXT/INT 9
12 DATACLK
DGND 10
11 SYNC
SW PACKAGE
20-LEAD PLASTIC SO
15 SYNC
TJMAX = 125°C, θJA = 130°C/W
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CONVERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
PARAMETER
CONDITIONS
MIN
LTC1609
TYP
MAX
MIN
LTC1609A
TYP
MAX
UNITS
Resolution
●
16
16
Bits
No Missing Codes
●
15
16
Bits
Transition Noise
Integral Linearity Error
0.9
(Note 7)
Differential Linearity Error
Bipolar Zero Error
External Reference = 2.5V (Note 8), Bipolar Ranges
±3
●
●
●
0.9
–2
3
±10
–1
LSBRMS
±2
LSB
1.75
LSB
±10
mV
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LTC1609
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CONVERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
PARAMETER
CONDITIONS
MIN
LTC1609
TYP
MAX
MIN
LTC1609A
TYP
MAX
±2
Bipolar Zero Error Drift
Bipolar Ranges
Unipolar Zero Error
External Reference = 2.5V, Unipolar Ranges
Unipolar Zero Error Drift
Unipolar Ranges
±2
±10
●
±2
±7
Full-Scale Error Drift
Full-Scale Error
External Reference = 2.5V (Notes 12, 13)
Full-Scale Error Drift
External Reference = 2.5V
Power Supply Sensitivity
VANA = VDIG = VDD
VDD = 5V ±5% (Note 9)
ppm/°C
±10
±2
ppm/°C
±0.25
±2
±2
±8
mV
ppm/°C
±7
±0.50
●
UNITS
%
ppm/°C
±8
LSB
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Analog Input Range (Note 9)
4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V,
CIN
RIN
LTC1609/LTC1609A
TYP
MAX
UNITS
±10, 0V to 5V, etc.
(See Tables 1a and 1b)
V
Analog Input Capacitance
10
pF
Analog Input Impedance
See Tables 1a and 1b
kΩ
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DY A IC ACCURACY
●
(Notes 5, 14)
MIN
LTC1609
TYP
MAX
MIN
LTC1609A
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-(Noise
+ Distortion) Ratio
1kHz Input Signal (Note 14)
10kHz Input Signal
20kHz, – 60dB Input Signal
87.5
87
30
THD
Total Harmonic
Distortion
1kHz Input Signal, First 5 Harmonics
10kHz Input Signal, First 5 Harmonics
– 100
– 94
– 100
– 94
Peak Harmonic or
Spurious Noise
1kHz Input Signal
10kHz Input Signal
– 102
– 94
– 102
– 94
dB
dB
Full-Power Bandwidth
(Note 15)
275
275
kHz
85
87.5
87
30
UNITS
dB
dB
dB
–96
dB
dB
–3dB Input Bandwidth
1
1
MHz
Aperture Delay
40
40
ns
Aperture Jitter
Sufficient to Meet AC Specs Sufficient to Meet AC Specs
Transient Response
Full-Scale Step (Note 9)
Overvoltage Recovery
(Note 16)
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INTERNAL REFERENCE CHARACTERISTICS
2
µs
2
150
150
ns
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
MIN
●
2.470
Internal Reference Source Current
External Reference Voltage for Specified Linearity
(Notes 9, 10)
External Reference Current Drain
External Reference = 2.5V (Note 9)
CAP Output Voltage
IOUT = 0
LTC1609/LTC1609A
TYP
MAX
2.30
2.500
2.520
UNITS
V
±5
ppm/°C
1
µA
2.50
●
2.50
2.70
V
100
µA
V
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LTC1609
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
IIN
Digital Input Current
VIN = 0V to VDD
●
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 4.75V
IO = –10µA
VOL
Low Level Output Voltage
VDD = 4.75V
IO = 160µA
IO = – 200µA
IO = 1.6mA
●
LTC1609/LTC1609A
TYP
MAX
UNITS
2.4
V
0.8
V
±10
µA
5
pF
4.5
V
4.0
V
0.05
0.10
●
V
0.4
V
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
MIN
LTC1609/LTC1609A
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
t1
Convert Pulse Width
(Note 11)
●
t2
R/C, CS to BUSY Delay
CL = 25pF
●
80
ns
t3
BUSY Low Time
●
3
µs
t4
BUSY Delay After End of Conversion
t5
Aperture Delay
t6
Conversion Time
●
t7
Acquisition Time
●
t6 + t 7
Throughput Time
●
t8
R/C Low to DATACLK Delay
260
ns
t9
DATACLK Period
150
ns
t10
DATA Valid Setup Time
●
15
ns
t11
DATA Valid Hold Time
●
40
ns
t12
External DATACLK Period
●
50
ns
t13
External DATACLK High
●
20
ns
t14
External DATACLK Low
●
20
ns
t15
R/C, CS to External DATACLK Setup Time
●
15
t16
R/C to CS Setup Time
●
10
t17
External DATACLK to SYNC Delay
●
6
50
ns
t18
External DATACLK to DATA Valid Delay
●
10
50
ns
t19
CS to External DATACLK Rising Edge Delay
●
10
ns
t20
Previous DATA Valid After CS, R/C Low
(Note 9)
●
2.2
µs
t21
BUSY to External DATACLK Setup Time
(Note 9)
●
5
ns
t22
BUSY Falling Edge to Final External DATACLK
(Notes 10, 17)
●
t23
TAG Valid Setup Time
●
0
ns
t24
TAG Valid Hold Time
●
15
ns
40
UNITS
ns
100
ns
5
ns
3
µs
µs
2
5
t12
µs
ns
ns
1.2
µs
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LTC1609
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POWER REQUIREMENTS
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1609/LTC1609A
TYP
MAX
UNITS
VDD
Positive Supply Voltage
(Notes 9, 10)
4.75
5.25
V
IDD
Positive Supply Current
PWRD = Low
PDIS
Power Dissipation
PWRD = Low
PWRD = High
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VANA =
VDIG = VDD, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above VDD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a VIN input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5 LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Unipolar zero error is the offset voltage measured from
0.5LSB when the output codes flickers between 0000. . .0000 and 0000. .
.0001.
●
13
20
mA
65
50
100
mW
µW
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 1.2µs after the
start of the conversion.
Note 12: As measured with fixed 1% resistors shown in Figures 3a and
3b. Adjustable to zero with external potentiometer.
Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of
offset error. For unipolar input ranges full-scale error is the deviation of
the last code transition from ideal divided by the transiton voltage and
includes the effect of offset error.
Note 14: All specifications in dB are referred to a full-scale ±5V input.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 17: When data is shifted out during a conversion, with an external
data clock, complete the process within 1.2µs from the start of the
conversion (BUSY falling). This will help keep any external disturbances
from causing an error in the conversion result.
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LTC1609
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TYPICAL PERFOR A CE CHARACTERISTICS
Change in CAP Voltage
vs Load Current
Supply Current vs Supply Voltage
0.05
fSAMPLE = 200kHz
0
CHANGE IN CAP VOLTAGE (V)
14.5
14.0
13.5
13.0
12.5
12.0
11.5
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
11.0
4.5
5.0
4.75
5.25
SUPPLY VOLTAGE (V)
–0.05
–14 –12 –10 –8 –6 –4 –2 0
LOAD CURRENT (mA)
5.5
Typical INL Curve
–20
–30
–40
–50
–60
–70
4
1
1.5
1.5
–20
1.0
1.0
0.5
0.5
0
–0.5
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–2.0
32768
49152
65535
MAGNITUDE (dB)
0
16384
1M
fSAMPLE = 200kHz
fIN = 1kHz
SINAD = 87.2dB
THD = –100.1dB
–40
–60
–80
–100
–120
–130
0
16384
CODE
32768
65535
49152
0
CODE
25
50
75
100
FREQUENCY (kHz)
1609 G04
1609 G05
SINAD vs Input Frequency
1609 G06
THD vs Input Frequency
95
–40
90
–50
85
–60
THD (dB)
SINAD (dB)
100
1k
10k 100k
RIPPLE FREQUENCY (Hz)
Nonaveraged 4096 Point FFT Plot
Typical DNL Curve
2.0
0
10
1609 G03
2.0
DNL (LSB)
INL (LSB)
2
–10
1609 G02
1609 G01
0
fSAMPLE = 200kHz
0.04
POWER SUPPLY REJECTION (dB)
15.0
SUPPLY CURRENT (mA)
Power Supply Rejection
vs Ripple Frequency
80
75
–70
–80
70
–90
65
–100
60
–110
1
10
FREQUENCY (kHz)
100
1609 G07
1
10
FREQUENCY (kHz)
100
1609 G08
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LTC1609
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PIN FUNCTIONS
(20-Pin SO/28-Pin SSOP)
R1IN (Pin 1/Pin 1): Analog Input. See Table 1 and Figure␣ 1
for input range connections.
low, 16 clock pulses are output during each conversion.
The pin will stay low between conversions.
AGND1 (Pin 2/Pin 2): Analog Ground. Tie to analog ground
plane.
DATA (Pin 13/Pin 17): Serial Data Output. The output data
is synchronized to the DATACLK and the format is determined by SB/BTC. In the external shift clock mode, after 16
bits of data have been shifted out and CS is low and R/C is
high, the level in the TAG pin will be outputted. This can be
used to daisy-chain the serial data output from several
LTC1609s. If EXT/INT is low, the output data is valid on
both the rising and falling edge of the internal shift clock
which is outputted on DATACLK. In between conversions,
DATA will stay at the level of the TAG input when the
conversion was started.
R2IN (Pin 3/Pin 3): Analog Input. See Table 1 and Figure␣ 1
for input range connections.
R3IN (Pin 4/Pin 4): Analog Input. See Table 1 and Figure␣ 1
for input range connections.
NC (28-Pin SSOP Only—Pins 5, 8, 10, 11, 18, 20, 22,
23): No Connect.
CAP (Pin 5/Pin 6): Reference Buffer Output. Bypass with
2.2µF tantalum capacitor.
REF (Pin 6/Pin 7): 2.5V Reference Output. Bypass with
2.2µF tantalum capacitor. Can be driven with an external
reference.
AGND2 (Pin 7/Pin 9): Analog Ground. Tie to analog
ground plane.
SB/BTC (Pin 8/Pin 12): Select straight binary or two’s
complement data output format. Tie pin high for straight
binary or tie low for two’s complement format.
EXT/INT (Pin 9/Pin 13): Select external or internal clock
for shifting out the output data. Tie the pin high to
synchronize the output data to the clock that is applied to
the DATACLK pin. If the pin is tied low, a convert command
will start transmitting the output data from the previous
conversion synchronized to 16 clock pulses that are
outputted on the DATACLK pin.
TAG (Pin 14/Pin 19): Tag input is used in the external clock
mode. If EXT/INT is high, digital inputs applied to TAG will
be shifted out on DATA delayed 16 DATACLK pulses as
long as CS is low and R/C is high.
R/C (Pin 15/Pin 21): Read/Convert Input. With CS low, a
falling edge on R/C puts the internal sample-and-hold into
the hold state and starts a conversion. With CS low, a
rising edge on R/C enables the serial output data.
CS (Pin 16/Pin 24): Chip Select. Internally OR’d with R/C.
With R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the serial
output data.
DGND (Pin 10/Pin 14): Digital Ground.
BUSY (Pin 17/Pin 25): Output Shows Converter Status. It
is low when a conversion is in progress. Data valid on the
rising edge of BUSY. CS or R/C must be high when BUSY
rises or another conversion will start without time for
signal acquisition.
SYNC (Pin 11/Pin 15): Sync Output. If EXT/INT is high,
either a rising edge on R/C with CS low or a falling edge on
CS with R/C high will output a pulse on SYNC synchronized to the external clock applied on the DATACLK pin.
PWRD (Pin 18/Pin 26): Power Down Input. If the pin is tied
high, conversions are inhibited and power consumption is
reduced (10µA typ). Results from the previous conversion
are maintained in the output shift register.
DATACLK (Pin 12/Pin 16): Either an input or an output
depending on the level set on EXT/INT. The output data is
synchronized to this clock. When EXT/INT is high an
external shift clock is applied to this pin. If EXT/INT is taken
VANA (Pin 19/Pin 27): 5V Analog Supply. Bypass to ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
VDIG (Pin 20/Pin 28): 5V Digital Supply. Connect directly
to VANA.
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LTC1609
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FUNCTIONAL BLOCK DIAGRA
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R1IN
R2IN
CSAMPLE
20k
10k
20k
VANA
CSAMPLE
5k
R3IN
REF
VDIG
ZEROING SWITCHES
4k
2.5V REF
+
REF BUF
COMP
16-BIT CAPACITIVE DAC
–
CAP
(2.5V)
DATA
SUCCESSIVE APPROXIMATION
REGISTER
AGND1
DATACLK
SERIAL INTERFACE
AGND2
SYNC
INTERNAL
CLOCK
DGND
CONTROL LOGIC
1609 BD
CS
R/C
PWRD
SB/BTC
BUSY
EXT/INT
TAG
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APPLICATIO S I FOR ATIO
Conversion Details
The LTC1609 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit serial output. The ADC is complete
with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs. (Please refer to the Digital Interface section for
timing information.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches CSAMPLE to ground,
injecting the analog input charge onto the summing junction. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
SAMPLE
RIN1
SAMPLE
SI
CSAMPLE
–
VIN
RIN2
HOLD
+
CDAC
COMPARATOR
DAC
VDAC
S
A
R
16-BIT
SHIFT REGISTER
1609 F01
Figure 1. LTC1609 Simplified Equivalent Circuit
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LTC1609
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APPLICATIO S I FOR ATIO
the end of a conversion, the DAC output balances the VIN
input charge. The SAR contents (a 16-bit data word) that
represents the VIN are loaded into the 16-bit output shift
register.
Driving the Analog Inputs
The LTC1609 analog input ranges, along with the nominal
input impedances, are shown in Tables 1a and 1b. The
inputs are overvoltage protected to ±25V. The input impedance can get as low as 10kΩ, therefore, it should be
driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1609. More detailed information is available in the
Linear Technology data books and LinearViewTM CD-ROM.
200Ω
AIN1
R1IN
1000pF
LTC1609
100Ω
AIN2
R2IN
1000pF
AIN3
R3IN
1000pF
1609 F02
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply current. ±5V to ±15V supplies. Good AC/DC specs.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good
AC/DC specs.
LT1468 - 90MHz, 22V/µs 16-bit accurate amplifier
LT1469 - Dual LT1468
Offset and Gain Adjustments
The LTC1609 is specified to operate with three unipolar
and three bipolar input ranges. Pins R1IN, R2IN and R3IN
are connected as shown in Tables 1a and 1b for the
different input ranges. The tables also list the nominal
input impedance for each range. Table 1c shows the
output codes for the ideal input voltages of each of the six
input ranges.
The LTC1609 offset and full-scale errors have been trimmed
at the factory with the external resistors shown in Figures
3a and 3b. This allows for external adjustment of offset and
full scale in applications where absolute accuracy is important. The offset and gain adjustment circuits for the six
input ranges are also shown in Figures 3a and 3b. To
adjust the offset for a bipolar input range, apply an input
voltage equal to – 0.5LSB where 1LSB = (+ FS – – FS)/
65536 and change the offset resistor so the output code is
changing between 1111 1111 1111 1111 and 0000 0000
0000 0000. The gain is trimmed by applying an input
voltage of + FS – 1.5LSB and adjusting the gain trim resistor until the output code is changing between 0111 1111
1111 1110 and 0111 1111 1111 1111. In both cases the
data is in two’s complement format (SB/BTC = LOW)
To adjust the offset for a unipolar input range, apply an
input voltage equal to + 0.5LSB where 1LSB = + FS/65536.
Then adjust the offset trim resistor until the output code
changes between 0000 0000 0000 0000 and 0000 0000
0000 0001. To adjust the gain, apply an input voltage equal
to + FS – 1.5LSB and vary the gain trimming resistor until
the output code is changing between 1111 1111 1111 1110
and 1111 1111 1111 1111. In the unipolar case, the data
is in straight binary format (SB/BTC = HIGH). Figures 4a
and 4b show the transfer characteristics of the LTC1609.
LinearView is a trademark of Linear Technology Corporation.
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INPUT RANGE
WITH TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
WITHOUT TRIM
LTC1609
LTC1609
R1IN
R1IN
200Ω
200Ω
AGND1
AGND1
100Ω
100Ω
VIN
0V TO 10V
R2IN
R2IN
OFFSET
50k
TRIM
R3IN
33.2k
33.2k VIN
5V
+
R3IN
2.2µF
CAP
+
+
CAP
5V
576k
GAIN 50k
TRIM
REF
2.2µF 2.2µF
+
AGND2
AGND2
LTC1609
LTC1609
R1IN
R1IN
200Ω
200Ω
AGND1
AGND1
100Ω
100Ω
5V
R2IN
0V TO 5V
REF
2.2µF
VIN
33.2k
33.2k
R3IN
VIN
CAP
+
+
+
R2IN
OFFSET
50k
TRIM
REF
2.2µF
CAP
5V
576k
GAIN
TRIM 50k
+
2.2µF 2.2µF
REF
2.2µF
AGND2
200Ω
AGND2
LTC1609
200Ω
R1IN
VIN
AGND1
AGND1
100Ω
R2IN
0V TO 4V
R2IN
R3IN
R3IN
33.2k
33.2k
CAP
+
LTC1609
R1IN
VIN
100Ω
+
R3IN
+
5V
OFFSET
50k
TRIM
REF
2.2µF 2.2µF
5V
GAIN
50k
TRIM
2.2µF
CAP
576k
+
REF
2.2µF
AGND2
AGND2
1609 F03a
Figure 3a. Offset/Gain Circuits for Unipolar Input Ranges
Table 1a. Analog Input Range Connections for Figure 3a
ANALOG INPUT
RANGE
CONNECT R1IN
VIA 200Ω TO
CONNECT R2IN
VIA 100Ω TO
CONNECT R3IN
TO
INPUT
IMPEDANCE
0V to 10V
AGND
VIN
AGND
13.3kΩ
0V to 5V
AGND
AGND
VIN
10kΩ
0V to 4V
VIN
AGND
VIN
10.7kΩ
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INPUT RANGE
WITH TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
WITHOUT TRIM
200Ω
VIN
LTC1609
200Ω
R1IN
VIN
AGND1
AGND1
R2IN
± 10V
R2IN
100Ω
100Ω
R3IN
33.2k
CAP
+
+
R3IN
+
33.2k
2.2µF
5V
OFFSET
50k
TRIM
REF
CAP
5V
576k
GAIN
50k
TRIM
+
2.2µF 2.2µF
AGND2
LTC1609
LTC1609
R1IN
R1IN
200Ω
200Ω
AGND1
AGND1
33.2k
100Ω
VIN
R2IN
OFFSET
50k
TRIM
+
R2IN
+
R3IN
2.2µF
CAP
+
100Ω
VIN
5V
R3IN
33.2k
CAP
5V
576k
GAIN
TRIM 50k
REF
+
2.2µF 2.2µF
AGND2
LTC1609
200Ω
100Ω
LTC1609
200Ω
R1IN
VIN
R1IN
VIN
AGND1
AGND1
100Ω
R2IN
33.2k
R2IN
+
R3IN
33.2k
CAP
+
+
REF
2.2µF
AGND2
± 3.3V
REF
2.2µF
AGND2
± 5V
LTC1609
R1IN
5V
OFFSET
50k
TRIM
REF
2.2µF 2.2µF
R3IN
2.2µF
CAP
5V
GAIN
50k
TRIM
576k
+
REF
2.2µF
AGND2
AGND2
1609 F03b
Figure 3b. Offset/Gain Circuits for Bipolar Input Ranges
Table 1b. Analog Input Range Connections for Figure 3b
ANALOG INPUT
RANGE
CONNECT R1IN
VIA 200Ω TO
CONNECT R2IN
VIA 100Ω TO
CONNECT R3IN
TO
INPUT
IMPEDANCE
±10V
VIN
AGND
CAP
22.9kΩ
±5V
AGND
VIN
CAP
13.3kΩ
±3.3V
VIN
VIN
CAP
10.7kΩ
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Table 1c. LTC1609 Output Codes for Ideal Input Voltages
DESCRIPTION
ANALOG INPUT
Full-Scale Range
±10V
±5V
±3.34
0V to 10V
0V to 5V
0V to 4V
Least Significant Bit
305µV
153µV
102µV
153µV
76µV
61µV
+Full Scale (FS – 1LSB) 9.999695V 4.999847V
Midscale
1LSB Below Midscale
0V
0V
0V
– 305µV
–153µV
–102µV
–10V
– 5V
– 3.340000V
9.999847V 4.999924V 3.999939V
5V
2.5V
2V
4.999847V 2.499924V 1.999939V
0V
0V
0V
STRAIGHT BINARY
(SB/BTC HIGH)
0111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
0111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0000
111...111
011...111
BIPOLAR
ZERO
011...110
111...110
OUTPUT CODE
OUTPUT CODE (TWO’S COMPLIMENT)
– Full Scale
3.339898V
TWO’S COMPLEMENT
(SB/BTC LOW)
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–FSR/2
100...001
100...000
011...111
011...110
000...001
1LSB = FS/65536
000...000
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
0V
FS – 1LSB
INPUT VOLTAGE (V)
1609 F04b
1609 F04a
The ideal ±FS value for the ±3.3V range is 3.340000V – 1LSB
and – 3.340000V, respectively. The external 33.2k resistor
that is connected between the CAP pin and the R2IN pin,
slightly attenuates the input signal applied to R2IN. Without the 33.2k resistor the ±FS value would be 3.333333V
– 1LSB and – 3.333333V (zero volt offset), respectively.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conversions. For example in Figure 5 the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.9LSB.
Figure 4b. LTC1609 Unipolar Transfer Characteristics
2000
1500
COUNT
Figure 4a. LTC1609 Bipolar Transfer Characteristics
1000
500
0
–3
–2
–1
0
CODE
1
2
3
1609 F05
Figure 5. Histogram for 4096 Conversions
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Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 6 shows
a typical LTC1609 FFT plot which yields a SINAD of
87.2dB and THD of – 100dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 6 shows a typical SINAD of 87.2dB with
a 200kHz sampling rate and a 1kHz input.
0
fSAMPLE = 200kHz
fIN = 1kHz
SINAD = 87.2dB
THD = –100.1dB
MAGNITUDE (dB)
–20
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Voltage Reference
The LTC1609 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC scales
with VREF. The output of the reference is connected to the
input of a unity-gain buffer through a 4k resistor (see
Figure 7). The input to the buffer or the output of the
reference is available at REF. The internal reference can be
overdriven with an external reference if more accuracy is
needed. The buffer output drives the internal DAC and is
available at CAP. The CAP pin can be used to drive a steady
DC load of less than 2mA. Driving an AC load is not
recommended because it can cause the performance of
the converter to degrade.
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
–40
–60
–80
REF
(2.5V)
–100
2.2µF
4k
7
BANDGAP
REFERENCE
S
+
VANA
–120
–
–130
0
25
50
100
75
CAP
(2.5V)
FREQUENCY (kHz)
1609 F06
Figure 6. LTC1609 Nonaveraged 4096 Point FFT Plot
S
INTERNAL
CAPACITOR
DAC
1609 F07
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
2
2.2µF
6
2
2
Figure 7. Internal or External Reference Source
2
V + V3 + V4 ... + VN
THD = 20 log 2
V1
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Power Shutdown
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
When the PWRD pin is tied high, power consumption
drops to a typical value of 50µW from a specified maximum of 100mW. In the power shutdown mode, the result
from the previous conversion is still available in the
internal shift register, assuming the data had not been
clocked out before going into power shutdown.
The conversion result is clocked out serially on the DATA
pin. It can be synchronized by using the internal data clock
or by using an external clock provided by the user. Tying
the EXT/INT pin high puts the LTC1609 in the external
clock mode and the DATACLK pin is a digital input. Tying
the EXT/INT pin low puts the part in the internal clock mode
and the DATACLK pin becomes a digital output.
The internal reference buffer and the reference are shut
down, so the power-up recovery time will be dependent
upon how fast the bypass capacitors on these pins can be
charged. If the internal reference is used, the 4k resistor in
series with the output and the external bypass capacitor,
typically 2.2µF, will be the main time constant for the
power-up recovery time. If an external reference is used,
the reference buffer output will be able to ramp from 0V to
2.5V in 1ms, while charging a typical bypass capacitor of
2.2µF. The recovery time will be less if the bypass capacitor has not completely discharged.
Internal Clock Mode
With the EXT/INT pin tied low, the LTC1609 provides the
data clock on the DATACLK pin. The timing diagram is
shown in Figure 8. Typically, CS is tied low and the R/C
pin is used to start a conversion. During the conversion
a 16-bit word will be shifted out MSB-first on the DATA
pin. This word represents the result from the previous
conversion. The DATACLK pin outputs 16 clock pulses
used to synchronize the data. The output data is valid on
both the rising and falling edges of the clock. After the
LSB bit has been clocked out, the DATA pin will take on
the state of the TAG pin at the start of the conversion. The
DATACLK pin goes low until the next conversion is
requested. The data clock is derived from the internal
conversion clock. To avoid errors from occurring during
the current conversion, minimize the loading on the
DATACLK pin and the DATA pin. For the best conversion
results the external clock mode is recommended.
DIGITAL INTERFACE
Internal Conversion Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 2.7µs. No external adjustments are required and, with the typical acquisition time of
1.5µs, throughput performance of 200ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
t8
R/C
t9
t1
DATACLK
1
B15
(MSB)
t2
3
14
15
16
B13
B2
B1
B0
t11
t10
DATA
2
B14
t3
BUSY
1609 F08
Figure 8. Serial Data Timing Using Internal Clock (CS, EXT/INT and TAG Tied Low)
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External Clock Mode
pulse on the SYNC pin will be generated on the rising edge
of DATACLK #0. The SYNC output can be captured on the
falling edge of DATACLK #0 or on the rising edge of
DATACLK #1. After the rising edge of DATACLK #1, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #1 or on the rising edge of DATACLK #2. The
LSB will be valid on the falling edge of DATACLK #16 or the
rising edge of DATACLK #17. After the rising edge of
DATACLK #17 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #1.
A minimum of 17 clock pulses are required if the data is
captured on falling clock edges.
With the EXT/INT pin tied high, the DATACLK pin becomes
a digital input and the LTC1609 can accept an externally
supplied data clock. There are several ways in which the
conversion results can be clocked out. The data can be
clocked out during or after a conversion with a continuous
or discontinuous data clock. Figures 9 to 12 show the
timing diagram for each of these methods.
External Discontinuous Data Clock Data Read
After the Conversion
Figure 9 shows how the result from the current conversion can be read out after the conversion has been
completed. The externally supplied data clock is running
discontinuously. R/C is used to initiate a conversion with
CS tied low. The conversion starts on the falling edge of
R/C. R/C should be returned high within 1.2µs to prevent
the transition from disturbing the conversion. After the
conversion has been completed (BUSY returning high), a
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will
not degrade the 200kHz throughput. This method minimizes the possible external disturbances that can occur
while a conversion is in progress and will yield the best
performance.
t12
t14
t13
0
1
2
3
15
16
17
EXTERNAL
DATACLK
t1
R/C
t2
t21
t3
BUSY
t17
SYNC
t12
DATA
t23
TAG
TAG0
t18
B15
(MSB)
t24
TAG1
B14
B13
B1
B0
TAG0
TAG1
TAG2
TAG2
TAG3
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F09
Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion
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External Data Clock Data Read After the Conversion
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will not
degrade the 200kHz throughput.
Figure 10 shows how the result from the current conversion can be read out after the conversion has been completed. The externally supplied data clock is running
continuously. CS and R/C are first used together to initiate
a conversion and then CS is used to read the result. The
conversion starts on the falling edge of CS with R/C low.
Both CS and R/C should be returned high within 1.2µs to
prevent the transition from disturbing the conversion.
After the conversion has been completed (BUSY returning
high), a pulse on the SYNC pin will be generated after the
first rising edge of DATACLK #1 that occurs after CS goes
low (R/C high). The SYNC output can be captured on the
falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. After the rising edge of DATACLK #2, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #2 or on the rising edge of DATACLK #3. The
LSB will be valid on the falling edge of DATACLK #17 or the
rising edge of DATACLK #18. After the rising edge of
DATACLK #18 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #2.
External Discontinuous Data Clock Data Read
During the Conversion
Figure 11 shows how the result from the previous conversion can be read out during the current conversion. The
externally supplied data clock is running discontinuously.
R/C is used to initiate a conversion with CS tied low. The
conversion starts on the falling edge of R/C. R/C should be
returned high within 1.2µs to prevent the transition from
disturbing the conversion. A pulse on the SYNC pin will be
generated on rising edge of DATACLK #0. The SYNC
output can be captured on the falling edge of DATACLK #0
or on the rising edge of DATACLK #1. After the rising edge
of DATACLK #1, the SYNC output will go low and the MSB
will be clocked out on the DATA pin. This bit can be latched
on the falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. The LSB will be valid on the falling edge of
DATACLK #16. Another clock pulse would be needed if the
LSB is captured on a rising edge. A minimum of 17 clock
pulses are required if the data is captured on falling clock
edges.
t12
t13
t14
0
1
2
3
4
17
18
EXTERNAL
DATACLK
t19
t15
t1
CS
t16
t16
R/C
t2
t3
BUSY
t17
SYNC
t12
DATA
t23
TAG
TAG0
t18
B15
(MSB)
t24
TAG1
B14
B1
B0
TAG0
TAG2
TAG15
TAG16
TAG17
TAG1
TAG18
TAG19
1606 F10
Figure 10. Conversion and Read Timing with External Clock (EXT/INT Tied High). Read After Conversion
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t12
t13
t14
0
1
2
15
16
EXTERNAL
DATACLK
t15
t1
R/C
t2
BUSY
t3
t21
t22
t17
SYNC
t18
DATA
B15
(MSB)
B14
B1
B0
1606 F11
Figure 11. Conversion and Read Timing Using a Discontinuous Data Clock (EXT/INT Tied High, CS Tied Low).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2µs
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2µs from the start of the conversion. Using the maximum data clock frequency of 20MHz
will ensure this condition is met.
External Data Clock Data Read During the Conversion
Figure 12 shows how the result from the previous conversion can be read out during the current conversion. The
externally supplied data clock is running continuously. CS
and R/C are used to initiate a conversion and read the data
from the previous conversion. The conversion starts on
the falling edge of CS after R/C is low. A pulse on the SYNC
pin will be generated on the first rising edge of DATACLK
#1 after R/C has returned high. The SYNC output can be
captured on the falling edge of DATACLK #1 or on the
rising edge of DATACLK #2. After the rising edge of
DATACLK #2 the SYNC output will go low and the MSB will
be clocked out on the DATA pin. This bit can be latched on
the falling edge of DATACLK #2 or on the rising edge of
DATACLK #3. The LSB will be valid on the falling edge of
DATACLK #17 or the rising edge of DATACLK #18. After
the rising edge of DATACLK #18 the DATA pin will take on
the value of the TAG pin that occurred at the rising edge of
DATACLK #2.
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2µs from the start of the conversion. Using the maximum data clock frequency of 20MHz
will ensure this condition is met. Since there is no throughput penalty for clocking the data out after the conversion,
clocking the data out during the conversion is not recommended.
Use of the TAG Input
The TAG input pin is used to daisy-chain multiple converters. This is useful for applications where hardware constraints may limit the number of lines needed to interface
to a large number of converters. This mode of operation
works only using the external clock method of shifting out
the data.
Figure 13 shows how this feature can be used. R/C, CS and
the DATACLK are tied together on both LTC1609s. CS can
be grounded if a discontinuous data clock is used. A falling
edge on R/C will allow both LTC1609s to capture their
respective analog input signals simultaneously. Once the
conversion has been completed the external data clock
DCLK is started. The MSB from device #1 will be valid after
the rising edge of DCLK #1. Once the LSB from device #1
has been shifted out on the rising edge of DCLK #16, a null
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t12
0
t14
t13
1
2
3
4
16
17
18
t19
EXTERNAL
DATACLK
CS
t16
t15
R/C
t2
t3
BUSY
t17
SYNC
t12
DATA
t23
TAG
TAG0
t18
B15
(MSB)
t24
TAG1
B14
B13
B1
B0
TAG0
TAG1
TAG2
TAG3
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F12
Figure 12. Conversion and Read Timing Using an External Data Clock (EXT/INT Tied High).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2µs
DCLK IN
R/C IN
CS IN
LTC1609
#2
TAG
DATA
LTC1609
#1
TAG
DATA
CS
CS
R/C
R/C
DCLK
DCLK
DATA OUT
1609 F13
Figure 13. Two LTC1609s Cascaded
Together Using the TAG Input
bit will be shifted out on the following clock pulse before
the MSB from device #2 becomes available (Figure 14).
The reason for this is the MSB from device #2 will not be
valid soon enough to meet the minimum setup time of
device #1’s TAG input. A minimum of 34 clock pulses are
needed to shift out the results from both LTC1609s
assuming the data is captured on the falling clock edge.
Using the highest frequency permitted for DATACLK
(20MHz), a 200kHz throughput can still be achieved.
1609fa
18
LTC1609
U
W
U U
APPLICATIO S I FOR ATIO
R/C
BUSY
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DCLK
•••
DATA
OUT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
DEVICE DATA #1
B5
B4
B3
B2
B1
B0
NULL
BIT B15
B14
B13
B12
B11
DEVICE DATA #2
B10 • • •
1609 F14
Figure 14. Data Output from Cascading Two (CS = Low, TAG (#2) = Low) LTC1609s Together
Output Data Format
The SB/BTC pin controls the format of the serial digital
output word. With the pin tied high the format is straight
binary. With the pin tied low the data format is two’s
complement. See Table 1c.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1609, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
Pay particular attention to the design of the analog and
digital ground planes. Placing the bypass capacitor as
close as possible to the VDIG and VANA pins, the REF pin
and reference buffer output is very important. Low impedance common returns for these bypass capacitors are
essential to low noise operation of the ADC, and the foil
width for these tracks should be as wide as possible. Also,
since any potential difference in grounds between the
signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling
clock have been placed on the digital ground plane. The
two ground planes are tied together at the power supply
ground connection.
A “postage stamp” (1.6in × 1.5in) evaluation board is
available and allows fast in-situ evaluation of the LTC1609.
See Figures 15a through 15d, inclusive.
1609fa
19
LTC1609
U
W
U U
APPLICATIO S I FOR ATIO
C6
2.2µF
E14
GND
C4
1000pF
C2
1000pF
C5
2.2µF
C3
1000pF
E8
5V
E15
R4
E16
R5
E17
R6
C1
10µF
R4
200Ω
1
2
R5
100Ω
R6
33k
3
4
E1
R3IN
5
6
7
8
9
10
11
5V
12
JP1
13
14
JP2
R1IN
VDIG
AGND1
VANA
R2IN
PWRD
R3IN
BUSY
NC
LTC1609
CS
CAP
NC
REF
NC
NC
R/C
AGND2
NC
NC
TAG
NC
NC
SB/BTC
DATA
EXT/INT DATACLK
DGND
SYNC
28
C7
0.1µF
27
R1 10k
26
25
24
E3
BUSY
R2 10k
E13
PWRD
E12
CS
23
22
21
E4
RC
20
R3 10k
19
E11
TAG
18
17
16
E6
DATACLK
15
E5
DATA
E7
SYNC
E10
GND
E2
GND
1609 F15a
Figure 15a. LTC1609 “Postage Stamp” Evaluation Circuit Schematic
1609fa
20
LTC1609
U
W
U U
APPLICATIO S I FOR ATIO
Figure 15b. LTC1609 “Postage Stamp” Evaluation Board
Silkscreen (2× Actual Size)
Figure 15c. LTC1609 “Postage Stamp” Evaluation Board
Top Metal Layer (2× Actual Size)
Figure 15d. LTC1609 “Postage Stamp” Evaluation Board
Bottom Metal Layer (2× Actual Size)
1609fa
21
LTC1609
U
W
U U
APPLICATIO S I FOR ATIO
LTC1609
200Ω
R1IN
LTC1609
R1IN
VIN
200Ω
AGND1
33.2k
0V TO 10V
100Ω
VIN
AGND1
±10V
R2IN
R2IN
100Ω
LTC1662
CS/LD
SCK
SDI
5V
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
OFFSET
TRIM
R3IN
CAP
GAIN
TRIM
787k
+
+
REF
LTC1662
CS/LD
SCK
SDI
5V
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
33.2k
OFFSET
TRIM
CAP
GAIN
TRIM
787k
+
2.2µF
2.2µF
R3IN
+
2.2µF
2.2µF
AGND2
0.1µF
AGND2
0.1µF
LTC1609
LTC1609
R1IN
R1IN
200Ω
200Ω
AGND1
0V TO 5V
LTC1662
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
OFFSET
TRIM
VIN
100Ω
VIN
R3IN
CAP
GAIN
TRIM
787k
+
+
2.2µF
REF
LTC1662
CS/LD
SCK
SDI
5V
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
OFFSET
TRIM
R2IN
+
R3IN
2.2µF
CAP
GAIN
TRIM
787k
+
2.2µF
AGND2
200Ω
AGND2
0.1µF
LTC1609
R1IN
VIN
AGND1
AGND1
100Ω
±3.3V
100Ω
LTC1609
200Ω
R1IN
VIN
R2IN
LTC1662
CS/LD
SCK
SDI
5V
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
OFFSET
TRIM
R2IN
33.2k
33.2k
R3IN
+
GAIN
TRIM
2.2µF
CAP
787k
+
REF
LTC1662
CS/LD
SCK
SDI
5V
CS/LD VOUTA
GND
SCK
VCC
SDI
VOUTB
REF
OFFSET
TRIM
+
R3IN
2.2µF
CAP
GAIN
TRIM
2.2µF
0.1µF
REF
2.2µF
0.1µF
0V TO 4V
AGND1
33.2k
±5V
100Ω
33.2k
R2IN
CS/LD
SCK
SDI
5V
REF
787k
+
REF
2.2µF
AGND2
0.1µF
AGND2
1609 F16
OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
Figure 16. Digitally-Controlled Offset and Full-Scale Adjust Circuits Using
the LTC1662 Dual 10-Bit VOUT DAC (Adjust Offset First at 0V, Then Adjust Gain)
1609fa
22
LTC1609
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
10.07 – 10.33*
(.397 – .407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 – 7.90
(.301 – .311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.20 – 5.38**
(.205 – .212)
1.73 – 1.99
(.068 – .078)
0° – 8°
.13 – .22
(.005 – .009)
.55 – .95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
.65
(.0256)
BSC
.25 – .38
(.010 – .015)
.05 – .21
(.002 – .008)
G28 SSOP 0501
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1609fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1609
U
PACKAGE DESCRIPTIO
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
20
19
18
17
16
15
14
13
12
11
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
1
3
4
5
6
7
8
9
10
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
TYP
S20 (WIDE) 1098
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Low Power 400ksps 14-Bit ADC
20mW, Single 5V or ±5V, Serial I/O
LTC1418
Low Power 200ksps 14-Bit ADC
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LTC1595/LTC1596
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LTC1604
16-Bit 333ksps Sampling ADC
±2.5V Input, 90dB SINAD, 100dB THD, Parallel I/O
LTC1605
Low Power 100ksps 16-Bit ADC
Single 5V, ±10V Input
LTC1605-1
Low Power 100ksps 16-Bit ADC
Single 5V, 0V to 4V Input
LTC1605-2
Low Power 100ksps 16-Bit ADC
Single 5V, ±4V Input
LTC1606
Low Power 250ksps 16-Bit ADC
Single 5V, ±10V Input, Parallel I/O
LTC1608
16-Bit 500ksps Sampling ADC
±2.5V Input, Pin Compatible with LTC1604
LTC1650
16-Bit ±5V Voltage Output DAC
Low Glitch, 4µs Settling Time, Serial I/O
LTC1655/LTC1655L
16-Bit Single 5V/3V Voltage Output DACs
SO-8 Package, Micropower, Serial I/O
1609fa
24
Linear Technology Corporation
LT/TP 0302 1.5K REV A • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2000
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