LTC1666/LTC1667/LTC1668
12-Bit, 14-Bit, 16-Bit,
50Msps DACs
DESCRIPTIO
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FEATURES
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50Msps Update Rate
Pin Compatible 12-Bit, 14-Bit and 16-Bit Devices
High Spectral Purity: 87dB SFDR at 1MHz fOUT
5pV-s Glitch Impulse
Differential Current Outputs
20ns Settling Time
Low Power: 180mW from ±5V Supplies
TTL/CMOS (3.3V or 5V) Inputs
Small Package: 28-Pin SSOP
Operating from ±5V supplies, the LTC1666/LTC1667/
LTC1668 can be configured to provide full-scale output
currents up to 10mA. The differential current outputs of
the DACs allow single-ended or true differential operation.
The – 1V to 1V output compliance of the LTC1666/
LTC1667/LTC1668 allows the outputs to be connected
directly to external resistors to produce a differential output voltage without degrading the converter’s linearity. Alternatively, the outputs can be connected to the summing
junction of a high speed operational amplifier, or to a
transformer.
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APPLICATIO S
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The LTC®1666/LTC1667/LTC1668 are 12-/14-/16-bit,
50Msps differential current output DACs implemented on
a high performance BiCMOS process with laser trimmed,
thin-film resistors. The combination of a novel currentsteering architecture and a high performance process
produces DACs with exceptional AC and DC performance.
The LTC1668 is the first 16-bit DAC in the marketplace to
exhibit an SFDR (spurious free dynamic range) of 87dB
for an output signal frequency of 1MHz.
Cellular Base Stations
Multicarrier Base Stations
Wireless Communication
Direct Digital Synthesis (DDS)
xDSL Modems
Arbitrary Waveform Generation
Automated Test Equipment
Instrumentation
The LTC1666/LTC1667/LTC1668 are pin compatible and
are available in a 28-pin SSOP and are fully specified over
the industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
LTC1668, 16-Bit, 50Msps DAC
5V
LTC1668 SFDR vs fOUT and f CLOCK
0.1µF
REFOUT
0.1µF
RSET
2k
2.5V
REFERENCE
VDD
100
LTC1668
5MSPS
90
IREFIN
25MSPS
IOUT A
+
16-BIT
HIGH SPEED
DAC
–
+
52.3Ω
IOUT B
VOUT 1VP-P
DIFFERENTIAL
–
SFDR (dB)
52.3Ω
80
50MSPS
70
COMP1
C1
0.1µF
LADCOM
COMP2
C2
0.1µF
VSS
AGND DGND
CLK
DB15
DB0
0.1µF
DIGITAL AMPLITUDE = 0dBFS
50
1666/7/8 TA01
CLOCK 16-BIT DATA
INPUT
INPUT
60
0.1
1.0
10
100
fOUT (MHz)
1666/7/8 G05
– 5V
1
LTC1666/LTC1667/LTC1668
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ABSOLUTE
RATI GS
(Note 1)
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS) ............................... – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Digital Input Voltage .................... – 0.3V to (VDD + 0.3V)
Analog Output Voltage
(IOUT A and IOUT B) ........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1666C/LTC1667C/LTC1668C ........... 0°C to 70°C
LTC1666I/LTC1667I/LTC1668I .......... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
DB9
1
28 DB10
DB8
2
27 DB11 (MSB)
DB7
3
26 CLK
DB6
4
25 VDD
DB5
5
24 DGND
DB4
6
23 VSS
DB3
7
22 COMP2
DB2
8
21 COMP1
DB1
9
20 IOUT A
DB0 (LSB) 10
19 IOUT B
LTC1666CG
LTC1666IG
NC 11
18 LADCOM
NC 12
17 AGND
NC 13
16 IREFIN
NC 14
15 REFOUT
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 100°C/W
TOP VIEW
DB11
1
28 DB12
DB10
2
27 DB13 (MSB)
DB9
3
26 CLK
DB8
4
25 VDD
DB7
5
24 DGND
ORDER PART
NUMBER
LTC1667CG
LTC1667IG
TOP VIEW
DB13
1
28 DB14
DB12
2
27 DB15 (MSB)
DB11
3
26 CLK
DB10
4
25 VDD
DB9
5
24 DGND
6
23 VSS
DB6
6
23 VSS
DB8
DB5
7
22 COMP2
DB7
7
22 COMP2
DB4
8
21 COMP1
DB6
8
21 COMP1
DB3
9
20 IOUT A
DB5
9
20 IOUT A
DB2 10
19 IOUT B
DB4 10
19 IOUT B
DB1 11
18 LADCOM
DB3 11
18 LADCOM
DB0 (LSB) 12
17 AGND
DB2 12
17 AGND
NC 13
16 IREFIN
DB1 13
16 IREFIN
NC 14
15 REFOUT
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
DB0 (LSB) 14
15 REFOUT
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 100°C/W
ORDER PART
NUMBER
LTC1668CG
LTC1668IG
LTC1666/LTC1667/LTC1668
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = – 5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
SYMBOL PARAMETER
CONDITIONS
MIN
LTC1666
TYP MAX
MIN
LTC1667
TYP MAX
MIN
LTC1668
TYP MAX
UNITS
DC Accuracy (Measured at IOUT A, Driving a Virtual Ground)
Resolution
●
Monotonicity
INL
DNL
Integral Nonlinearity
(Note 2)
Differential Nonlinearity
(Note 2)
12
14
16
Bits
12
14
14
Bits
±1
±1
Offset Error
0.1
Offset Error Drift
GE
PSRR
±2
±0.2
0.1
5
Gain Error
Internal Reference, RIREFIN = 2k
External Reference,
VREF = 2.5V, RIREFIN = 2k
Gain Error Drift
Internal Reference
External Reference
Power Supply
Rejection Ratio
VDD = 5V ±5%
VSS = – 5V ±5%
±8
±1
±1
±4
±0.2
0.1
±0.2
5
2
1
5
2
1
50
30
±0.1
±0.2
50
30
±0.1
±0.2
LSB
% FSR
ppm/°C
2
1
50
30
LSB
% FSR
% FSR
ppm/°C
ppm/°C
±0.1 % FSR/V
±0.2 % FSR/V
AC Linearity
SFDR
Spurious Free Dynamic
Range to Nyquist
Spurious Free Dynamic
Range Within a Window
fCLK = 25Msps, fOUT = 1MHz
0dB FS Output
– 6dB FS Output
–12dB FS Output
87
87
83
dB
dB
dB
fCLK = 50Msps, fOUT = 1MHz
85
dB
fCLK = 50Msps, fOUT = 2.5MHz
81
dB
fCLK = 50Msps, fOUT = 5MHz
79
dB
fCLK = 50Msps, fOUT = 20MHz
70
dB
96
dB
88
dB
fCLK = 25Msps,
fOUT = 1MHz, 2MHz Span
76
78
85
78
86
86
fCLK = 50Msps,
fOUT = 5MHz, 4MHz Span
THD
Total Harmonic Distortion fCLK = 25Msps, fOUT = 1MHz
fCLK = 50Msps, fOUT = 5MHz
–75
–77
– 84
– 78
– 77
dB
dB
3
LTC1666/LTC1667/LTC1668
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V, VSS = – 5V, LADCOM = AGND = DGND = 0V, IOUTFS = 10mA.
SYMBOL
PARAMETER
LTC1666/LTC1667/LTC1668
MIN
TYP
MAX
CONDITIONS
UNITS
Analog Output
IOUTFS
Full-Scale Output Current
●
1
Output Compliance Range
IFS = 10mA
●
–1
Output Resistance; RIOUT A, RIOUT B
IOUT A, B to LADCOM
●
0.7
Output Capacitance
10
1
1.1
1.5
5
mA
V
kΩ
pF
Reference Output
Reference Voltage
REFOUT Tied to IREFIN Through 2kΩ
2.475
Reference Output Drift
Reference Output Load Regulation
2.5
2.525
V
25
ppm/°C
ILOAD = 0mA to 5mA
6
mV/mA
IFS = 10mA, CCOMP1 = 0.1µF
20
kHz
Reference Input
Reference Small-Signal Bandwidth
Power Supply
VDD
Positive Supply Voltage
●
4.75
5
5.25
VSS
Negative Supply Voltage
IDD
Positive Supply Current
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
●
ISS
Negative Supply Current
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
●
PDIS
Power Dissipation
IFS = 10mA, fCLK = 25Msps, fOUT = 1MHz
IFS = 1mA, fCLK = 25Msps, fOUT = 1MHz
V
●
–4.75
–5
–5.25
3
5
mA
33
40
mA
V
180
85
mW
mW
75
Msps
Dynamic Performance (Differential Transformer Coupled Output, 50Ω Double Terminated, Unless Otherwise Noted)
fCLOCK
Maximum Update Rate
tS
Output Settling Time
tPD
Output Propagation Delay
Glitch Impulse
●
50
To 0.1% FSR
Single Ended
Differential
20
ns
8
ns
15
5
pV-s
pV-s
tr
Output Rise Time
4
ns
tf
Output Fall Time
4
ns
iNO
Output Noise
50
pA/√Hz
Digital Inputs
VIH
Digital High Input Voltage
●
VIL
Digital Low Input Voltage
●
0.8
V
IIN
Digital Input Current
●
±10
µA
CIN
Digital Input Capacitance
tDS
Input Setup Time
●
8
ns
tDH
Input Hold Time
●
4
ns
tCLKH
Clock High Time
●
5
ns
tCLKL
Clock Low Time
●
8
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
4
2.4
V
5
pF
Note 2: For the LTC1666, ±1LSB = ±0.024% of full scale;
for the LTC1667, ±1LSB = ±0.006% of full scale = ±61ppm of full scale;
for the LTC1668, ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
LTC1666/LTC1667/LTC1668
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TYPICAL PERFOR A CE CHARACTERISTICS
Single Tone SFDR at 50MSPS
2-Tone SFDR
–30
–40
–50
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
–10
0
5
10
15
FREQUENCY (MHz)
20
25
5.0
FREQUENCY (MHz)
–80
SFDR > 82dB
fCLOCK = 5MSPS
fOUT1 = 0.5MHz
fOUT2 = 0.65MHz
fOUT3 = 1.10MHz
fOUT4 = 1.25MHz
AMPL = 0dBFS
1
4.6
8.2
11.8
15.4
FREQUENCY (MHz)
100
90
80
50MSPS
SFDR (dB)
SFDR (dB)
25MSPS
–70
19
SFDR vs f OUT and Digital Amplitude
(dBFS) at fCLOCK = 5MSPS
5MSPS
–60
–70
1666/7/8 G03
100
0
–50
–60
SFDR vs f OUT and fCLOCK
–10
–40
–50
1666/7/8 G02
4-Tone SFDR, f CLOCK = 5MSPS
–30
–40
–110
5.5
1666/7/8 G01
–20
SFDR > 74dB
fCLOCK = 50MSPS
fOUT1 = 5.02MHz
fOUT2 = 6.51MHz
fOUT3 = 11.02MHz
fOUT4 = 12.51MHz
AMPL = 0dBFS
–30
–100
–100
4.5
–100
–20
–90
–90
–90
SIGNAL AMPLITUDE (dBFS)
0
SIGNAL AMPLITUDE (dBFS)
–20
SFDR > 86dB
fCLOCK = 50MSPS
fOUT1 = 4.9MHz
fOUT2 = 5.09MHz
AMPL = 0dBFS
–10
SIGNAL AMPLITUDE (dBFS)
SFDR = 87dB
fCLOCK = 50MSPS
fOUT = 1.002MHz
AMPL = 0dBFS
= –8.25dBm
–10
SIGNAL AMPLITUDE (dBFS)
4-Tone SFDR, f CLOCK = 50MSPS
0
0
70
95
0dBFS
90
–6dBFS
85
–12dBFS
80
75
70
65
–80
60
60
–90
55
–100
–110
0.1
DIGITAL AMPLITUDE = 0dBFS
50
0.46
0.82
1.18
1.54
FREQUENCY (MHz)
1.0
0.1
1.9
10
50
100
0
–6dBFS
90
95
85
90
SFDR (dB)
70
65
80
75
70
–12dBFS
–6dBFS
65
75
60
55
55
55
50
50
2
6
fOUT (MHz)
4
8
10
1666/7/8 G07
IOUTFS = 2.5mA
65
60
0
IOUTFS = 5mA
70
60
50
IOUTFS = 10mA
85
SFDR (dB)
80
2.0
DIGITAL AMPLITUDE = 0dBFS
0dBFS
80
–12dBFS
1.6
SFDR vs f OUT and IOUTFS at
fCLOCK = 25MSPS
0dBFS
75
1.2
fOUT (MHz)
1666/7/8 G06
SFDR vs f OUT and Digital Amplitude
(dBFS) at fCLOCK = 50MSPS
95
85
0.8
1666/7/8 G05
SFDR vs f OUT and Digital Amplitude
(dBFS) at fCLOCK = 25MSPS
90
0.4
fOUT (MHz)
1666/7/8 G04
SFDR (dB)
(LTC1668)
0
5
10
fOUT (MHz)
15
20
1666/7/8 G08
0
2.5
5
fOUT (MHz)
7.5
10
1666/7/8 G09
5
LTC1666/LTC1667/LTC1668
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TYPICAL PERFOR A CE CHARACTERISTICS
SFDR vs Digital Amplitude (dBFS)
and fCLOCK at fOUT = fCLOCK/11
SFDR vs Digital Amplitude (dBFS)
and fCLOCK at fOUT = fCLOCK/5
Single-Ended Outputs
Full-Scale Transition
100
100
95
95
455kHz AT 5MSPS
90
90
85
85
80
80
SFDR (dB)
SFDR (dB)
(LTC1668)
4.55MHz AT 50MSPS
75
2.277MHz AT 25MSPS
70
1MHz AT 5MSPS
5MHz AT 25MSPS
75
70
65
60
60
55
55
50
–20
50
–20
0
0000
FFFF
10MHz AT 50MSPS
65
–15
–10
–5
DIGITAL AMPLITUDE (dBFS)
V(IOUTB)
100mV
/DIV
V(IOUTA)
CLOCK INPUT
CLK IN
5V/DIV
–15
–10
–5
DIGITAL AMPLITUDE (dBFS)
1666/7/8 G10
0
5ns/DIV
1666/7/8 G12
1666/7/8 G11
Differential Output
Full-Scale Transition
Differential Output
Full-Scale Transition
Single-Ended Output
Full-Scale Transition
V(IOUTA) – V(IOUTB)
V(IOUTA) – V(IOUTB)
V(IOUTA)
100mV
/DIV
0000
100mV
/DIV
FFFF
FFFF
100mV
/DIV
0000
FFFF
0000
V(IOUTB)
CLOCK INPUT
CLK IN
5V/DIV
CLK IN
5V/DIV
5ns/DIV
5ns/DIV
5ns/DIV
1666/7/8 G14
1666/7/8 G13
Single-Ended Midscale
Glitch Impulse
1666/7/8 G15
Differential Midscale
Glitch Impulse
V(IOUTA) – V(IOUTB)
8000
7FFF
1mV/DIV
Integral Nonlinearity
8000
1mV/DIV
CLK IN
5V/DIV
CLK IN
5V/DIV
5ns/DIV
4
3
2
1
0
–1
–2
–3
–4
–5
5ns/DIV
1666/7/8 G16
5
INTEGRAL NONLINEARITY (LSB)
V(IOUTA), V(IOUTB)
7FFF
CLK IN
5V/DIV
1666/7/8 G17
49152
32768
16384
DIGITAL INPUT CODE
65535
1666/7/8 G18
6
LTC1666/LTC1667/LTC1668
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TYPICAL PERFOR A CE CHARACTERISTICS
(LTC1668)
Differential Nonlinearity
DIFFERENTIAL NONLINEARITY (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
32768
16384
49152
DIGITAL INPUT CODE
65535
1666/7/8 G19
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PI FU CTIO S
LTC1666
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
COMP1 (Pin 21): Current Source Control Amplifier Compensation. Bypass to VSS with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to VSS
with 0.1µF.
IREFIN (Pin 16): Reference Input Current. Nominal value is
1.25mA for IFS = 10mA. IFS = IREFIN • 8.
VSS (Pin 23): Negative Supply Voltage. Nominal value is
– 5V.
AGND (Pin 17): Analog Ground.
DGND (Pin 24): Digital Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.
IOUT B (Pin 19): Complementary DAC Output Current. Fullscale output current occurs when all data bits are 0s.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
DB11 to DB0 (Pins 27, 28, 1 to 10 ): Digital Input Data Bits.
IOUT A (Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
7
LTC1666/LTC1667/LTC1668
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PI FU CTIO S
LTC1667
LTC1668
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1µF bypass capacitor
to AGND.
IREFIN (Pin 16): Reference Input Current. Nominal value is
1.25mA for IFS = 10mA. IFS = IREFIN • 8.
IREFIN (Pin 16): Reference Input Current. Nominal value is
1.25mA for IFS = 10mA. IFS = IREFIN • 8.
AGND (Pin 17): Analog Ground.
AGND (Pin 17): Analog Ground.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.
IOUT B (Pin 19): Complementary DAC Output Current. Fullscale output current occurs when all data bits are 0s.
IOUT B (Pin 19): Complementary DAC Output Current. Fullscale output current occurs when all data bits are 0s.
IOUT A (Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
IOUT A (Pin 20): DAC Output Current. Full-scale output
current occurs when all data bits are 1s.
COMP1 (Pin 21): Current Source Control Amplifier Compensation. Bypass to VSS with 0.1µF.
COMP1 (Pin 21): Current Source Control Amplifier Compensation. Bypass to VSS with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to VSS
with 0.1µF.
COMP2 (Pin 22): Internal Bypass Point. Bypass to VSS
with 0.1µF.
VSS (Pin 23): Negative Supply Voltage. Nominal value is
– 5V.
VSS (Pin 23): Negative Supply Voltage. Nominal value is
– 5V.
DGND (Pin 24): Digital Ground.
DGND (Pin 24): Digital Ground.
VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.
VDD (Pin 25): Positive Supply Voltage. Nominal value is 5V.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.
DB13 to DB0 (Pins 27, 28, 1 to 12 ): Digital Input Data Bits.
DB15 to DB0 (Pins 27, 28, 1 to 14 ): Digital Input Data Bits.
8
LTC1666/LTC1667/LTC1668
W
BLOCK DIAGRA
LTC1666
5V
0.1µF
25
VDD
VREF
15
REFOUT
2.5V
REFERENCE
0.1µF
ATTENUATOR
LADDER
RSET
2k
16
IFS/8
+
IINT
22
0.1µF
IOUT A
20
+
IOUT B
19
–
52.3Ω
52.3Ω
VOUT
1VP-P
DIFFERENTIAL
CURRENT SOURCE ARRAY
–
21
18
SEGMENTED SWITCHES
FOR DB15–DB12
LSB SWITCHES
IREFIN
LADCOM
•••
•••
COMP1
INPUT LATCHES
COMP2
0.1µF
VSS
23
AGND
DGND
17
24
DB11
•••
DB0
27
10
1666 BD
•••
0.1µF
–5V
CLK
26
CLOCK
INPUT
12-BIT
DATA INPUT
LTC1667
5V
0.1µF
25
VDD
VREF
15
REFOUT
2.5V
REFERENCE
0.1µF
ATTENUATOR
LADDER
RSET
2k
16
IFS/8
+
IINT
22
0.1µF
IOUT A
20
+
IOUT B
19
–
52.3Ω
52.3Ω
VOUT
1VP-P
DIFFERENTIAL
CURRENT SOURCE ARRAY
–
21
18
SEGMENTED SWITCHES
FOR DB15–DB12
LSB SWITCHES
IREFIN
LADCOM
•••
•••
COMP1
INPUT LATCHES
COMP2
0.1µF
VSS
23
–5V
0.1µF
AGND
DGND
17
24
CLK
26
DB13
•••
27
DB0
12
1667 BD
•••
CLOCK
INPUT
14-BIT
DATA INPUT
9
LTC1666/LTC1667/LTC1668
W
BLOCK DIAGRA
LTC1668
5V
0.1µF
25
VDD
VREF
15
REFOUT
2.5V
REFERENCE
0.1µF
IFS/8
+
IINT
22
0.1µF
20
+
IOUT B
19
–
52.3Ω
CURRENT SOURCE ARRAY
–
21
IOUT A
SEGMENTED SWITCHES
FOR DB15–DB12
LSB SWITCHES
IREFIN
18
ATTENUATOR
LADDER
RSET
2k
16
LADCOM
•••
•••
COMP1
INPUT LATCHES
COMP2
0.1µF
VSS
23
AGND
DGND
17
24
DB15
26
•••
DB0
27
14
1668 BD
•••
0.1µF
–5V
CLK
CLOCK
INPUT
16-BIT
DATA INPUT
WU
W
TI I G DIAGRA
DATA
INPUT
N–1
N
tDS
N+1
tDH
CLK
tCLKL
tCLKH
tST
tPD
IOUT A/IOUT B
N–1
N
0.1%
1666/7/8 TD
10
52.3Ω
VOUT
1VP-P
DIFFERENTIAL
LTC1666/LTC1667/LTC1668
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Theory of Operation
The LTC1666/LTC1667/LTC1668 are high speed current
steering 12-/14-/16-bit DACs made on an advanced
BiCMOS process. Precision thin film resistors and well
matched bipolar transistors result in excellent DC linearity
and stability. A low glitch current switching design gives
excellent AC performance at sample rates up to 50Msps.
The devices are complete with a 2.5V internal bandgap
reference and edge triggered latches, and set a new
standard for DAC applications requiring very high dynamic range at output frequencies up to several megahertz.
Referring to the Block Diagrams, the DACs contain an
array of current sources that are steered to IOUTA or IOUTB
with NMOS differential current switches. The four most
significant bits are made up of 15 current segments of
equal weight. The remaining lower bits are binary weighted,
using a combination of current scaling and a differential
resistive attenuator ladder. All bits and segments are
precisely matched, both in current weight for DC linearity,
and in switch timing for low glitch impulse and low
spurious tone AC performance.
Setting the Full-Scale Current, IOUTFS
The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC performance, CCOMP1 should be connected to VSS and be placed
very close to the package (less than 0.1").
For fixed reference voltage applications, CCOMP1 should
be 0.1µF or more. The reference control loop small-signal
bandwidth is approximately 1/(2π) • CCOMP1 • 80 or 20kHz
for CCOMP1 = 0.1µF.
Reference Operation
The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to IREFIN, corresponding to a
1.25mA load (IOUTFS = 10mA). REFOUT has nominal
output impedance of 6Ω, or 0.24% per mA, so it must be
buffered to drive any additional external load. A 0.1µF
capacitor is required on the REFOUT pin for compensation. Note that this capacitor is required for stability, even
if the internal reference is not being used.
External Reference Operation
Figure 1, shows how to use an external reference to control
the LTC1666/LTC1667/LTC1668 full-scale current.
The full-scale DAC output current, IOUTFS, is nominally
10mA, and can be adjusted down to 1mA. Placing a
resistor, RSET, between the REFOUT pin, and the IREFIN pin
sets IOUTFS as follows.
The internal reference control loop amplifier maintains a
virtual ground at IREFIN by servoing the internal current
source, IINT, to sink the exact current flowing into IREFIN.
IINT is a scaled replica of the DAC current sources and
IOUTFS = 8 • (IINT), therefore:
IOUTFS = 8 • (IREFIN) = 8 • (VREF/RSET)
(1)
For example, if RSET = 2k and is tied to VREF = REFOUT =
2.5V, IREFIN = 2.5/2k = 1.25mA and IOUTFS = 8 • (1.25mA)
= 10mA.
REFOUT
5V
2.5V
REFERENCE
0.1µF
EXTERNAL
REFERENCE
IREFIN
LTC1666/
LTC1667/
LTC1668
RSET
+
–
1666/7/8 F02
Figure 1. Using the LTC1666/LTC1667/LTC1668
with an External Reference
11
LTC1666/LTC1667/LTC1668
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Adjusting the Full-Scale Output
VOUT A = IOUT A • RLOAD
(8)
In Figure 2, a serial interfaced DAC is used to set IOUTFS.
The LTC1661 is a dual 10-bit VOUT DAC with a buffered
voltage output that swings from 0V to VREF.
VOUT B = IOUT B • RLOAD
(9)
5V
2.5V
REFERENCE
REF
0.1µF
IREFIN
1/2 LTC1661
RSET
1.9k
VDIFF = VOUT A – VOUT B
= (IOUT A – IOUT B) • (RLOAD)
(10)
Substituting the values found earlier for IOUT A, IOUT B and
IOUTFS (LTC1668):
LTC1666/
LTC1667/
LTC1668
VDIFF = {2 • DAC Code – 65535)/65536} • 8 •
(RLOAD/RSET) • (VREF)
+
–
1666/7/8 F03
Figure 2. Adjusting the Full-Scale Current of
the LTC1666/LTC1667/LTC1668 with a DAC
DAC Transfer Function
The LTC1666/LTC1667/LTC1668 use straight binary digital
coding. The complementary current outputs, IOUT A and IOUT
B, sink current from 0 to IOUTFS. For IOUTFS = 10mA (nominal), IOUT A swings from 0mA when all bits are low (e.g.,
Code␣ = 0) to 10mA when all bits are high (e.g., Code = 65535
for LTC1668) (decimal representation). IOUT B is complementary to IOUT A. IOUT A and IOUT B are given by the following
formulas:
LTC1666:
IOUT A = IOUTFS • (DAC Code/4096)
(2)
IOUT B = IOUTFS • (4095 – DAC Code)/4096
(3)
LTC1667:
IOUT A = IOUTFS • (DAC Code/16384)
(4)
IOUT B = IOUTFS • (16383 – DAC Code)/16384
(5)
LTC1668:
IOUT A = IOUTFS • (DAC Code/65536)
(6)
IOUT B = IOUTFS • (65535 – DAC Code)/65536
(7)
In typical applications, the LTC1666/LTC1667/LTC1668
differential output currents either drive a resistive load
directly or drive an equivalent resistive load through a
transformer, or as the feedback resistor of an I-to-V
converter. The voltage outputs generated by the IOUT A and
IOUT B output currents are then:
12
The differential voltage is:
(11)
From these equations some of the advantages of differential mode operation can be seen. First, any common mode
noise or error on IOUT A and IOUT B is cancelled. Second, the
signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times IOUT A and
IOUT B, such as reference or IOUTFS noise, cancel near
midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.
Note that the term (RLOAD/RSET) appears in both the
differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
RLOAD to RSET, and the Gain Error tempco is affected by the
temperature tracking of RLOAD with RSET. Note also that
the absolute tempco of RLOAD is very critical for DC
nonlinearity. As the DAC output changes from 0mA to
10mA the RLOAD resistor will heat up slightly, and even a
very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.
Analog Outputs
The LTC1666/LTC1667/LTC1668 have two complementary current outputs, IOUT A and IOUT B (see DAC Transfer
Function). The output impedance of IOUT A and IOUT B
(RIOUT A and RIOUT B) is typically 1.1kΩ to LADCOM. (See
Figure 3.)
LTC1666/LTC1667/LTC1668
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LADCOM
LTC1666/LTC1667/LTC1668
RIOUT B
1.1k
RIOUT A
1.1k
IOUT A
IOUT B
Output Compliance
18
The specified output compliance voltage range is ±1V. The
DC linearity specifications, INL and DNL, are trimmed and
guaranteed on IOUT A into the virtual ground of an
I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linearity. Below –1V, the DAC switches will start to approach the
transition from saturation to linear region. This will degrade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than ±0.5VP-P on IOUT A and
IOUT B due to nonlinear capacitance and other large-signal
effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC performance generally behave as additive currents, so decreasing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.
20
52.3Ω
19
52.3Ω
5pF
5pF
VSS
– 5V
23
1666/7/8 F04
Figure 3. Equivalent Analog Output Circuit
LADCOM
The LADCOM pin is the common connection for the
internal DAC attenuator ladder. It usually is tied to analog
ground, but more generally it should connect to the same
potential as the load resistors on IOUT A and IOUT B. The
LADCOM pin carries a constant current to VSS of approximately 0.32 • (IOUTFS), plus any current that flows from
IOUT A and IOUT B through the RIOUT A and RIOUT B resistors.
5V
0.1µF
REFOUT
0.1µF
RSET
2k
2.5V
REFERENCE
VDD
LTC1668
MINI-CIRCUITS
T1–1T
IREFIN
IOUT A
+
16-BIT
HIGH SPEED
DAC
–
110Ω
IOUT B
COMP1
C1
0.1µF
50Ω
50Ω
LADCOM
COMP2
C2
0.1µF
TO HP3589A
SPECTRUM
ANALYZER
50Ω INPUT
AGND DGND
VSS
CLK
DB15
DB0
16
0.1µF
DIGITAL
DATA
– 5V
OUT 1 OUT 2
CLK HP8110A DUAL
IN PULSE GENERATOR
HP1663EA
CLK
LOGIC ANALYZER WITH
IN
PATTERN GENERATOR
1666/7/8 F05
LOW JITTER
CLOCK SOURCE
Figure 4. AC Characterization Setup (LTC1668)
13
LTC1666/LTC1667/LTC1668
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Operating with Reduced Output Currents
Differential Transformer-Coupled Outputs
The LTC1666/LTC1667/LTC1668 are specified to operate
with full-scale output current, IOUTFS, from the nominal
10mA down to 1mA. This can be useful to reduce power
dissipation or to adjust full-scale value. However, the DC
and AC accuracy is specified only at IOUTFS = 10mA, and
DC and AC accuracy will fall off significantly at lower IOUTFS
values. At IOUTFS = 1mA, the LTC1668 INL and DNL
typically degrade to the 14-bit to 13-bit level, compared to
16-bit to 15-bit typical accuracy at 10mA IOUTFS. Increasing IOUTFS from 1mA, the accuracy improves rapidly,
roughly in proportion to 1/IOUTFS. Note that the AC performance (SFDR) is affected much more by reduced IOUTFS
than it is by reduced digital amplitude (see Typical Performance Characteristics). Therefore it is usually better to
make large gain adjustments digitally, keeping IOUTFS
equal to 10mA.
Differential transformer-coupled output configurations
usually give the best AC performance. An example is
shown in Figure 5. The advantages of transformer coupling include excellent rejection of common mode distortion and noise over a broad frequency range and convenient differential-to-single-ended conversion with isolation or level shifting. Also, as much as twice the power can
be delivered to the load, and impedance matching can be
accomplished by selecting the appropriate transformer
turns ratio. The center tap on the primary side of the
transformer is tied to ground to provide the DC current
path for IOUT A and IOUT B. For low distortion, the DC
average of the IOUT A and IOUT B currents must be exactly
equal to avoid biasing the core. This is especially important for compact RF transformers with small cores. The
circuit in Figure 5 uses a Mini-Circuits T1-1T RF transformer with a 1:1 turns ratio. The load resistance on
IOUT A and IOUT B is equivalent to a single differential
resistor of 50Ω, and the 1:1 turns ratio means the output
impedance from the transformer is 50Ω. Note that the
load resistors are optional, and they dissipate half of the
output power. However, in lab environments or when
driving long transmission lines it is very desirable to have
a 50Ω output impedance. This could also be done with a
50Ω resistor at the transformer secondary, but putting
the load resistors on IOUT A and IOUT B is preferred since
it reduces the current through the transformer. At signal
frequencies lower than about 1MHz, the transformer core
size required to maintain low distortion gets larger, and at
some lower frequencies this becomes impractical.
Output Configurations
Based on the specific application requirements, the
LTC1666/LTC1667/LTC1668 allow a choice of the best of
several output configurations. Voltage outputs can be
generated by external load resistors, transformer coupling
or with an op amp I-to-V converter. Single-ended DAC
output configurations use only one of the outputs, preferably IOUT A, to produce a single-ended voltage output.
Differential mode configurations use the difference between IOUT A and IOUT B to generate an output voltage,
VDIFF, as shown in equation 11. Differential mode gives
much better accuracy in most AC applications. Because
the DAC chip is the point of interface between the digital
input signals and the analog output, some small amount
of noise coupling to IOUT A and IOUT B is unavoidable. Most
of that digital noise is common mode and is canceled by
the differential mode circuit. Other significant digital noise
components can be modeled as VREF or IOUTFS noise. In
single-ended mode, IOUTFS noise is gone at zero scale and
is fully present at full scale. In differential mode, IOUTFS
noise is cancelled at midscale input, corresponding to zero
analog output. Many AC signals, including broadband and
multitone communications signals with high peak to average ratios, stay mostly near midscale.
14
MINI-CIRCUITS
T1-1T
IOUT A
LTC1666/
LTC1667/
LTC1668
50Ω
110Ω
RLOAD
IOUT B
50Ω
1666/7/8 F06
Figure 5. Differential Transformer-Coupled Outputs
LTC1666/LTC1667/LTC1668
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Resistor Loaded Outputs
A differential resistor loaded output configuration is shown
in Figure 6. It is simple and economical, but it can drive
only differential loads with impedance levels and amplitudes appropriate for the DAC outputs.
The recommended single-ended resistor loaded configuration is essentially the same circuit as the differential
resistor loaded, case—simply use the IOUT A output,
referred to ground. Rather than tying the unused IOUT B
output to ground, it is preferred to load it with the equivalent RLOAD of IOUT A. Then IOUT B will still swing with a
waveform complementary to IOUT A.
52.3Ω
52.3Ω
IOUT A
LTC1666/
LTC1667/
LTC1668
IOUT B
1666/7/8 F07
Figure 6. Differential Resistor-Loaded Output
Op Amp I to V Converter Outputs
Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 7.
This circuit complements the capabilities of the transformer-coupled application at lower frequencies, since
available op amps can deliver good AC distortion performance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
±1V around ground.
Figure 8 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.
Digital Interface
The LTC1666/LTC1667/LTC1668 have parallel inputs that
are latched on the rising edge of the clock input. They
accept CMOS levels from either 5V or 3.3V logic and can
accept clock rates of up to 50MHz.
Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, VIH =
2.4V min, VIL = 0.8V max, work with 3.3V or 5V CMOS
levels over temperature. The guaranteed setup time, tDS,
is 8ns minimum and the hold time, tDH, is 4ns minimum.
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1666/LTC1667/LTC1668 to be clocked at up to 50Msps
minimum.
For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is important. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually inCOUT
500Ω
IOUTFS
10mA
200Ω
IOUT A
LTC1666/
LTC1667/
LTC1668
RFB
200Ω
–
60pF
LT1809
200Ω
IOUT B
IOUT A
+
±1V
10dBm
VOUT
52.3Ω
52.3Ω
LADCOM
500Ω
U1
LT®1812
LTC1666/
LTC1667/
LTC1668
IOUT B
–
+
VOUT
0V TO 2V
200Ω
1666/7/8 F09
1666/7/8 F08
Figure 7. Differential to Single-Ended Op Amp I-V Converter
Figure 8. Single-Ended Op Amp I to V Converter
15
LTC1666/LTC1667/LTC1668
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cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.
necessity. Figures 11 to 15 are the printed circuit board
layers for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1µF or larger with low ESR.
Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will
cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled impedance and should be well terminated near the LTC1666/
LTC1667/LTC1668.
Bypass capacitors are required on VSS, VDD and REFOUT,
and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1µF bypass capacitor. It should be bypassed
to VSS along with COMP1. The AGND and DGND pins
should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The IOUT A and
IOUT B traces should be close together, short, and well
matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.
Suggested Evaluation Circuit
Figure 10 is the schematic and Figures 11 to 15 are the
circuit board layouts for a suggested evaluation circuit,
DC245A. The circuit can be programmed with component
selection and jumpers for a variety of differentially coupled
transformer output and differential and single-ended resistor loaded output configurations.
Printed Circuit Board Layout Considerations—
Grounding, Bypassing and Output Signal Routing
The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute
52.3Ω
REFOUT
0.1µF
IREFIN
REF
SERIAL
INPUT
1/2 LTC1661
U3
LTC1668
U1
I-CHANNEL
2k
VOUT
LADCOM
IOUT A
LOCAL
OSCILLATOR
2.1k
90°
52.3Ω
21k
QUADRATURE
MODULATOR
LOW-PASS
FILTER
IOUT B
CLK
REFOUT
±5%
RELATIVE GAIN
ADJUSTMENT RANGE
52.3Ω
LTC1668
U2
Q-CHANNEL
0.1µF
IREFIN
LADCOM
IOUT A
IOUT B
∑
52.3Ω
LOW-PASS
FILTER
CLK
1666/7/8 F10
CLOCK
INPUT
Figure 9. QAM Modulation Using LTC1668 with
Digitally Controlled I vs Q Channel Gain Adjustment
16
QAM
OUTPUT
J10
J7
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+5VD
4
GND
+
C14
10µF
25V
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
J11
J8
10
9
7
8
C21
0.1µF
11
6
+5VA
12
5
22Ω
13
4
9
8
14
10
7
15
11
6
3
12
5
2
13
4
16
14
3
1
15
2
22Ω
RN6
16
+
C15
10µF
25V
TP9
TESTPOINT BLK
C23
0.1µF
1
16
JP9
2
26
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
27
J9
R12
49.9Ω
3 1%
CLK
IOUT B
–5V
C17
0.1µF
J6
EXTCLK
24
17
25
23
22
21
18
–5V
C11
0.1µF
C8
0.1µF
C20
0.1µF
C16
10µF
25V
TP8
TESTPOINT RED
AGND DGND
GROUND PLANE
TIE POINT
5V
C10
0.1µF
C7
0.1µF
TP5
TESTPOINT WHT
19
20
15
C22
0.1µF
DGND
AGND
VDD
VSS
COMP2
COMP1
LADCOM
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
IOUT A
REFOUT
DB15 (MSB)
REFIN
LTC1668
C3
0.1µF
Figure 10. Suggested Evaluation Circuit
R3
1.91k
0.1%
OPTIONAL
SIP
PULL-UP/
PULL-DOWN
RESISTORS
(NOT
INSTALLED)
+5VD
R2
200Ω
TP7
TESTPOINT RED
TP2
TESTPOINT WHT
2.5VREF
1
RN5
6
5
VIN VOUT
4
2
3
JP1
1
2
6
LT1460DCS8-2.5
TP6
TESTPOINT RED
C19
0.1µF
3
4
+5VD
1
2
AMP
102159-9
C2
0.1µF
5V
C1
0.1µF
TP10
TESTPOINT BLK
C12
22pF
JP6
C8
0.1µF
JP5
R9
50Ω
0.1%
JP7
JP4
R10
50Ω
0.1%
C12
22pF
C9
0.1µF
J5
IOUT B
JP8
TP4
TESTPOINT
WHT
J2
IOUT A
C4
1666/7/8 F11
C18
0.1µF
R7
110Ω
R6
R5
JP3
R4
5V
TP3
TESTPOINT
WHT
JP2
6
T1 4
R16
0Ω
R15
0Ω
R14
0Ω
R13
0Ω
MINICIRCUITS
T1–1T
1
2
3
R8
C5
J4
VOUT
U U
W
TP1
APPLICATIO S I FOR ATIO
U
R1
10Ω
+
J1
EXTREF
LTC1666/LTC1667/LTC1668
17
LTC1666/LTC1667/LTC1668
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Figure 11. Suggested Evaluation Circuit Board—Silkscreen
18
LTC1666/LTC1667/LTC1668
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Figure 12. Suggested Evaluation Circuit Board—Component Side
19
LTC1666/LTC1667/LTC1668
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Figure 13. Suggested Evaluation Circuit Board—GND Plane
20
LTC1666/LTC1667/LTC1668
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Figure 14. Suggested Evaluation Circuit Board—Power Plane
21
LTC1666/LTC1667/LTC1668
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Figure 15. Suggested Evaluation Circuit Board—Solder Side
22
LTC1666/LTC1667/LTC1668
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
10.07 – 10.33*
(.397 – .407)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 – 7.90
(.301 – .311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5.20 – 5.38**
(.205 – .212)
1.73 – 1.99
(.068 – .078)
0° – 8°
.13 – .22
(.005 – .009)
.55 – .95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
.65
(.0256)
BSC
.25 – .38
(.010 – .015)
.05 – .21
(.002 – .008)
G28 SSOP 0501
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1666/LTC1667/LTC1668
U
TYPICAL APPLICATIO
5V
1k
VDD
REFOUT
0.1µF
LADCOM
RSET
2k
0.1µF
52.3Ω
–
IOUT A
100pF
LTC1668
IREFIN
0.1µF
52.3Ω
VOUT
±10V
LT1227
+
IOUT B
COMP1
COMP2
VSS AGND DGND CLK DB15-DB0
1k
1666/7/8 F17
CLOCK 18-BIT
INPUT DATA
INPUT
– 5V
Figure 16. Arbitrary Waveform Generator Has ±10V Output Swing, 50Msps DAC Update Rate
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
8-Bit, 20Msps ADC
Undersampling Capability Up to 70MHz Input
ADCs
LTC1406
LTC1411
14-Bit, 2.5Msps ADC
LTC1420
12-Bit, 10Msps ADC
72dB SINAD at 5MHz fIN
LTC1604/LTC1608
16-Bit, 333ksps/500ksps ADCs
16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
DACs
LTC1591/LTC1597
Parallel 14/16-Bit Current Output DACs
On-Chip 4-Quadrant Resistors
LTC1595/LTC1596
Serial 16-Bit Current Output DACs
Low Glitch, ±1LSB Maximum INL, DNL
LTC1650
Serial 16-Bit Voltage Output DAC
Low Power, Deglitched, 4-Quadrant Multiplying VOUT DAC,
±4.5V Output Swing, 4µs Settling Time
LTC1655(L)
Single 16-Bit VOUT DAC with Serial Interface in SO-8
5V (3V) Single Supply, Rail-to-Rail Output Swing
LTC1657(L)
16-Bit Parallel Voltage Output DAC
5V (3V) Low Power, 16-Bit Monotonic Over Temp., Multiplying Capability
LT1809/LT1810
Single/Dual 180MHz, 350V/µs Op Amp
Rail-to-Rail Input and Output, Low Distortion
LT1812/LT1813
Single/Dual 100MHz, 750V/µs Op Amp
3.6mA Supply Current, 8nV/√Hz Input Noise Voltage
AMPLIFIERs
24
Linear Technology Corporation
166678f LT/TP 0701 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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