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LTC1741CFW#TRPBF

LTC1741CFW#TRPBF

  • 厂商:

    LINEAR(凌力尔特)

  • 封装:

    TFSOP48

  • 描述:

    IC ADC 12BIT 65MSPS 48-TSSOP

  • 数据手册
  • 价格&库存
LTC1741CFW#TRPBF 数据手册
LTC1741 12-Bit, 65Msps Low Noise ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC ®1741 is an 65Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. Pin selectable input ranges of ±1V and ±1.6V along with a resistor programmable mode allow the LTC1741’s input range to be optimized for a wide variety of applications. Sample Rate: 65Msps 72dB SNR and 85dB SFDR (3.2V Range) 70.5dB SNR and 87dB SFDR (2V Range) No Missing Codes Single 5V Supply Power Dissipation: 1.275W Selectable Input Ranges: ±1V or ±1.6V 240MHz Full Power Bandwidth S/H Pin Compatible Family 25Msps: LTC1746 (14-Bit), LTC1745(12-Bit) 50Msps: LTC1744 (14-Bit), LTC1743(12-Bit) 65Msps: LTC1742 (14-Bit), LTC1741(12-Bit) 80Msps: LTC1748 (14-Bit), LTC1747(12-Bit) 48-Pin TSSOP Package The LTC1741 is perfect for demanding communications applications with AC performance that includes 72dB SNR and 85dB spurious free dynamic range. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies of up to 70MHz with excellent noise performance. DC specs include ±1 LSB INL and ±0.8LSB DNL over temperature. The digital interface is compatible with 5V, 3V, 2V and LVDS logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate output power supply can be operated from 0.5V to 5V, making it easy to connect directly to any low voltage DSPs or FIFOs. U APPLICATIO S ■ ■ ■ ■ ■ Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. The TSSOP package with a flow-through pinout simplifies the board layout. W BLOCK DIAGRA 65Msps, 12-Bit ADC with a ±1V Differential Input Range OVDD 0.5V TO 5V 0.1µF 0.1µF AIN+ ±1V DIFFERENTIAL ANALOG INPUT S/H AMP AIN– CORRECTION LOGIC AND SHIFT REGISTER 12-BIT PIPELINED ADC 12 OUTPUT LATCHES • • • OF D11 D0 CLKOUT OGND SENSE BUFFER RANGE SELECT VDD 5V 1µF 1µF DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1741 BD REFLB REFHA 4.7µF REFLA 0.1µF 1µF REFHB ENC 0.1µF 1µF ENC MSBINV OE DIFFERENTIAL ENCODE INPUT 1741f 1 LTC1741 W U PACKAGE/ORDER INFORMATION U W W W OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ............................................. 5.5V Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Except OE) (Note 3) .................................. – 0.3V to (VDD + 0.3V) OE Input Voltage (Note 4) ............ –0.3V to (VDD + 0.3V) Digital Output Voltage ................. – 0.3V to (VDD + 0.3V) OGND Voltage ..............................................– 0.3V to 1V Power Dissipation ............................................ 2000mW Operating Temperature Range LTC1741C ............................................... 0°C to 70°C LTC1741I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U ABSOLUTE MAXIMUM RATINGS ORDER PART NUMBER TOP VIEW SENSE VCM GND AIN+ AIN– GND VDD VDD GND REFLB REFHA GND GND REFLA REFHB GND VDD VDD GND VDD GND MSBINV ENC ENC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OF OGND D11 D10 D9 OVDD D8 D7 D6 D5 OGND GND GND D4 D3 D2 OVDD D1 D0 NC NC OGND CLKOUT OE LTC1741CFW LTC1741IFW FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 35°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Full-Scale Drift Offset Drift Input Referred Noise (Transition Noise) CONDITIONS ● (Note 6) ● ● (Note 7) External Reference (SENSE = 1.6V) Internal Reference External Reference (Sense = 1.6V) MIN 12 –1 –0.8 – 35 – 3.5 Sense = 1.6V TYP MAX ±0.4 ±0.2 ±5 ±1 ±40 ±20 ±20 0.21 1 0.8 35 3.5 UNITS Bits LSB LSB mV %FS ppm/°C ppm/°C µV/°C LSBRMS U U A ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VIN IIN CIN PARAMETER Analog Input Range (Note 8) Analog Input Leakage Current Analog Input Capacitance tACQ tAP tJITTER CMRR Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio CONDITIONS 4.75V ≤ VDD ≤ 5.25V MIN ● ● Sample Mode ENC < ENC Hold Mode ENC > ENC ● 1.5V < (AIN– = AIN+) < 3V TYP ±1 to ±1.6 –1 MAX 1 8 4 5 0 0.15 80 7.3 UNITS V µA pF pF ns ns psRMS dB 1741f 2 LTC1741 W U DY A IC ACCURACY TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP SNR Signal-to-Noise Ratio 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) 71 70.5 72 dB dB 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) 71 70.5 72 dB dB 70 71.5 dB dB 87 85 92 dB dB dB 87 85 92 dB dB dB 80 75 90 dB dB dB 70.5 72 dB dB 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) 70.5 72 dB dB 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) 70 71.5 dB dB 5MHz Input Signal, First 5 Harmonics (2V Range) 5MHz Input Signal, First 5 Harmonics (3.2V Range) –85 –84 dB dB 30MHz Input Signal, First 5 Harmonics (2V Range) 30MHz Input Signal, First 5 Harmonics (3.2V Range) –85 –84 dB dB 70MHz Input Signal, First 5 Harmonics (2V Range) 70MHz Input Signal, First 5 Harmonics (3.2V Range) –81 –77 dB dB Intermodulation Distortion fIN1 = 2.52MHz, fIN2 = 5.2MHz (2V Range) fIN1 = 2.52MHz, fIN2 = 5.2MHz (3.2V Range) 87 85 dBc dBc Sample-and-Hold Bandwidth RSOURCE = 50Ω 240 MHz 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) SFDR Spurious Free Dynamic Range 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) (2nd and 3rd) 5MHz Input Signal (3.2V Range) (Other) 30MHz Input Signal (2V Range) 30MHz Input Signal (3.2V Range) (2nd and 3rd) 30MHz Input Signal (3.2V Range) (Other) 77 84 70MHz Input Signal (2V Range) 70MHz Input Signal (3.2V Range) (2nd and 3rd) 70MHz Input Signal (3.2V Range) (Other) S/(N + D) THD IMD Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion 5MHz Input Signal (2V Range) 5MHz Input Signal (3.2V Range) U U U I TER AL REFERE CE CHARACTERISTICS 71 MAX UNITS (Note 5) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 2.30 2.35 2.40 VCM Output Tempco IOUT = 0 ±30 UNITS V ppm/°C VCM Line Regulation 4.75V ≤ VDD ≤ 5.25V 3 mV/V VCM Output Resistance 1mA ≤ IOUT ≤ 1mA 4 Ω 1741f 3 LTC1741 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V IIN Digital Input Current VIN = 0V to VDD CIN Digital Input Capacitance MSBINV and OE Only VOH High Level Output Voltage OVDD = 4.75V VOL Low Level Output Voltage OVDD = 4.75V Hi-Z Output Leakage D11 to D0 COZ ISOURCE ISINK UNITS ● 0.8 V ● ±10 µA 2.4 ● V 1.5 pF 4.74 V 4 IO = 160µA IO = 1.6mA IOZ MAX IO = –10µA IO = – 200µA TYP V 0.05 0.1 ● V 0.4 V ±10 µA VOUT = 0V to VDD, OE = High ● Hi-Z Output Capacitance D11 to D0 OE = High (Note 8) ● Output Source Current VOUT = 0V – 50 mA Output Sink Current VOUT = 5V 50 mA 15 pF U W POWER REQUIRE E TS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP VDD Positive Supply Voltage 5.25 V IDD Positive Supply Current ● 255 275 mA PDIS Power Dissipation ● 1.275 1.375 W OVDD Digital Output Supply Voltage VDD V 4.75 0.5 MAX UNITS WU TI I G CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX t0 ENC Period (Note 9) ● 15.3 2000 ns t1 ENC High (Note 8) ● 7.3 1000 ns t2 ENC Low (Note 8) ● 7.3 1000 ns t3 Aperture Delay (Note 8) t4 ENC to CLKOUT Falling CL = 10pF (Note 8) ● 1 4 ns t5 ENC to CLKOUT Rising CL = 10pF (Note 8) 0 2.4 UNITS ns t1 + t4 ns For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.7 10.1 11.7 ns t6 ENC to DATA Delay CL = 10pF (Note 8) ● 2 4.9 7.2 ns t7 ENC to DATA Delay (Hold Time) (Note 8) ● 1.4 3.4 4.7 ns t8 ENC to DATA Delay (Setup Time) CL = 10pF (Note 8) For 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 8.2 t9 CLKOUT to DATA Delay (Hold Time), 65Msps 50% Duty Cycle (Note 8) ● 7 ns t10 CLKOUT to DATA Delay (Setup Time), 65Msps 50% Duty Cycle CL = 10pF (Note 8) ● 3 ns t11 DATA Access Time After OE CL = 10pF (Note 8) 10 25 t12 BUS Relinquish (Note 8) 10 25 Data Latency t0 – t6 10.5 5 ns 13.4 ns ns ns cycles 1741f 4 LTC1741 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When this pin voltage is taken below GND or above 0VDD, it will be clamped by internal diodes. This product can handle input currents of >100mA below GND or above 0VDD without latchup. Note 5: VDD = 5V, fSAMPLE = 65MHz, differential ENC/ENC = 2VP-P 65MHz sine wave, input range = ±1.6V differential, unless otherwise specified. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. U W TYPICAL PERFOR A CE CHARACTERISTICS INL, 3.2V Range DNL, 3.2V Range 1.0 0 0.8 0.8 –10 0.6 0.6 0.4 0.4 0.2 0 –0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 1024 3072 2048 OUTPUT CODE –30 0.2 –0.4 0 –20 AMPLITUDE (dBFS) ERROR (LSB) ERROR (LSB) 1.0 –50 –60 –70 –80 –90 –110 1024 0 4096 –40 –100 3072 2048 OUTPUT CODE –120 4096 Averaged 8192 Point FFT, Input Frequency = 5MHz, –10dB, 3.2V Range 0 –10 –20 –20 –20 –30 –30 –70 –80 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741 G01 30 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 –10 –60 10 15 20 25 FREQUENCY (MHz) Averaged 8192 Point FFT, Input Frequency = 20MHz, –1dB, 3.2V Range Averaged 8192 Point FFT, Input Frequency = 5MHz, – 20dB, 3.2V Range 0 –50 5 1741 G03 –10 –40 0 1741 G02 1741 G01 AMPLITUDE (dBFS) Averaged 8192 Point FFT, Input Frequency = 5MHz, –1dB, 3.2V Range 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741 G01 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741 G01 1741f 5 LTC1741 U W TYPICAL PERFOR A CE CHARACTERISTICS 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –50 –60 –70 –80 –30 AMPLITUDE (dBFS) –40 –40 –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –90 –100 –100 –110 –110 –110 –120 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 0 5 10 15 20 25 FREQUENCY (MHz) –120 30 0 –10 –20 –20 –20 –30 –30 –70 –80 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 0 5 10 15 20 25 FREQUENCY (MHz) 1741 G10 –120 30 0 –10 –20 –20 –20 –30 –30 –70 –80 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741 G13 6 30 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 –10 –60 10 15 20 25 FREQUENCY (MHz) Averaged 8192 Point 2-Tone FFT, 5.2MHz and 5.7MHz Inputs, –7dB, 3.2V Range Averaged 8192 Point FFT, Input Frequency = 70MHz, –20dB, 3.2V Range 0 –50 5 1741 G12 –10 –40 0 1741 G11 Averaged 8192 Point FFT, Input Frequency = 70MHz, –10dB, 3.2V Range 30 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 –10 –60 10 15 20 25 FREQUENCY (MHz) Averaged 8192 Point FFT, Input Frequency = 70MHz, –1dB, 3.2V Range Averaged 8192 Point FFT, Input Frequency = 50MHz, –20dB, 3.2V Range 0 –50 5 1741 G09 –10 –40 0 1741 G08 Averaged 8192 Point FFT, Input Frequency = 50MHz, –10dB, 3.2V Range AMPLITUDE (dBFS) –40 –100 1741 G07 AMPLITUDE (dBFS) Averaged 8192 Point FFT, Input Frequency = 50MHz, –1dB, 3.2V Range Averaged 8192 Point FFT, Input Frequency = 20MHz, –20dB, 3.2V Range AMPLITUDE (dBFS) AMPLITUDE (dBFS) Averaged 8192 Point FFT, Input Frequency = 20MHz, –10dB, 3.2V Range 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741 G14 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 1741f 1741 G15 LTC1741 U W TYPICAL PERFOR A CE CHARACTERISTICS Averaged 8192 Point 2-Tone FFT, 25.2MHz and 30.2MHz Inputs, –7dB, 3.2V Range 0 0 –10 –10 –20 –20 100 95 –30 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –100 –100 –110 –110 0 5 –120 30 10 15 20 25 FREQUENCY (MHz) SFDR (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 –120 0 5 –6dB 40000 10000 60 0 40 80 60 INPUT FREQUENCY (MHz) 72.0 0 197 2033 2034 2035 595 0 2036 2037 69.5 90 73.0 85 72.5 75 260 71.5 71.0 65 70.5 85 1741 G22 250 240 230 220 70.0 80 100 40 60 80 INPUT FREQUENCY (MHz) Supply Current vs Sample Rate 72.0 70 60 20 270 SUPPLY CURRENT (mA) 73.5 SNR (dBFS) 95 60 SAMPLE RATE (Msps) 0 1741 G21 SNR vs Sample Rate, 5MHz Input, –1dB, 3.2V Range 74.0 40 2V RANGE 70.0 1741 G20 100 20 71.0 70.5 1741 G19 0 3.2V RANGE CODE SFDR vs Sample Rate, 5MHz Input, –1dB, 3.2 Range 100 71.5 100 80 40 80 60 INPUT FREQUENCY (MHz) 72.5 64737 30000 65 20 20 1741 G18 20000 70 –1dB SNR vs Input Frequency, 3.2V Range and 2V Range 75 0 75 0 SNR (dBFS) 50000 COUNT SFDR (dBFS) –20dB –1dB –6dB 80 60 30 10 15 20 25 FREQUENCY (MHz) 60000 80 –10dB Shorted Input Histogram, 3.2V –10dB 85 85 65 70000 90 –20dB 1741 G17 100 95 90 70 1741 G16 SFDR vs Input Frequency and Amplitude, 2V Range, 2nd and 3rd Harmonic SFDR (dBFS) SFDR vs Input Frequency and Amplitude, 3.2V Range, 2nd and 3rd Harmonic Averaged 8192 Point 2-Tone FFT, 68.2MHz and 70.2MHz Inputs, –7dB, 3.2V Range 0 20 40 60 SAMPLE RATE (Msps) 80 85 1741 G23 210 0 20 40 60 SAMPLE RATE (Msps) 80 1741 G24 1741f 7 LTC1741 U U U PI FU CTIO S SENSE (Pin 1): Reference Sense Pin. Ground selects ±1V. VDD selects ±1.6V. Greater than 1V and less than 1.6V applied to the SENSE pin selects an input range of ±VSENSE, ±1.6V is the largest valid input range. VCM (Pin 2): 2.35V Output and Input Common Mode Bias. Bypass to ground with 4.7µF ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN– (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND with 1µF ceramic chip capacitors. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2’s complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. OE (Pin 25): Output Enable. Low enables outputs. Logic high makes outputs Hi-Z. OE should not exceed the voltage on 0VDD. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. NC (Pins 28, 29): Do not connect these pins. D0-D1 (Pins 30 to 31): Digital Outputs. OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. D2-D4 (Pins 33 to 35): Digital Outputs. D5-D8 (Pins 39 to 42): Digital Outputs. D9-D11 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. 1741f 8 LTC1741 W BLOCK DIAGRA AIN+ AIN– VCM FIRST PIPELINED ADC STAGE (5 BITS) INPUT S/H SECOND PIPELINED ADC STAGE (4 BITS) THIRD PIPELINED ADC STAGE (4 BITS) FOURTH PIPELINED ADC STAGE (2 BITS) 2.35V REFERENCE 4.7µF SHIFT REGISTER AND CORRECTION RANGE SELECT REFL SENSE REFH INTERNAL CLOCK SIGNALS OVDD 0.5V TO 5V OF REF BUF D11 DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER DIFF REF AMP CONTROL LOGIC AND CALIBRATION LOGIC OUTPUT DRIVERS D0 CLKOUT 1741 F01 REFLB REFHA REFLA REFHB ENC ENC MSBINV OE OGND 4.7µF 0.1µF 0.1µF 1µF 1µF Figure 1. Functional Block Diagram WU W TI I G DIAGRA N ANALOG INPUT • t3 t1 t2 t0 ENC t7 t8 DATA (N – 4) DB11 TO DB0 DATA (N – 5) DB11 TO DB0 DATA DATA (N – 3) t6 CLKOUT t4 t5 t10 t9 OE t11 DATA t12 DATA N DB11 TO DB0, OF AND CLKOUT 1741 TD 1741f 9 LTC1741 U W U U APPLICATIO S I FOR ATIO The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Ratio Spurious Free Dynamic Range (SFDR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log V22 + V32 + V 42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC equals the ENC voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π) • FIN • TJITTER 1741f 10 LTC1741 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION The LTC1741 is a CMOS pipelined multistep converter. The converter has four pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later, see the Timing Diagram section. The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC1741 has two phases of operation, determined by the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high and ENC less than ENC as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue that is sent to the fourth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC1741 CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through CMOS transmission gates. This direct capacitor sampling results in lowest possible noise for a given sampling capacitor size. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC/ENC is low, the transmission gate connects the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC/ENC transitions from low to high the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC/ENC is high the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC/ENC transitions from high to low the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this LTC1741 VDD CSAMPLE 4pF CPARASITIC AIN+ 4pF VDD CSAMPLE 4pF CPARASITIC AIN– 4pF 5V BIAS 2V 6k ENC ENC 6k 2V 1741 F02 Figure 2. Equivalent Input Circuit 1741f 11 LTC1741 U W U U APPLICATIO S I FOR ATIO time. If the change between the last sample and the new sample is small the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing ±0.8V for the 3.2V range or ±0.5V for the 2V range, around a common mode voltage of 2.35V. The VCM output pin (Pin␣ 2) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 4.7µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC1741 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of encode the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when encode rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recomended to have a source impedence of 100Ω or less for each input. The S/H circuit is optimized for a 50Ω source impedance. If the source impedance is less than 50Ω, a series resistor should be added to increase this impedance to 50Ω. The source impedence should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC1741 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedence seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 4.7µF 0.1µF 1:1 ANALOG INPUT 100Ω 25Ω 100Ω 25Ω 12pF 12pF 25Ω AIN+ LTC1741 25Ω AIN– 12pF 1741 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer Figure 4 demonstrates the use of operational amplifiers to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. The 25Ω resistors and 12pF capacitors on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitors may need to be decreased to prevent excessive signal loss. 1741f 12 LTC1741 U W U U APPLICATIO S I FOR ATIO VCM LTC1741 4.7µF 5V SINGLE-ENDED INPUT 2.35V ±1/2 RANGE VCM 2.35V 25Ω 1/2 LT1810 1.6V RANGE DETECT AND CONTROL LTC1741 12pF + 25Ω 1/2 LT1810 – 500Ω 1V 25Ω AIN+ – 100Ω 2.35V BANDGAP REFERENCE 4.7µF 12pF + 4Ω TIE TO VDD FOR 3.2V RANGE; TIE TO GND FOR 2V RANGE; RANGE = 2 • VSENSE FOR 1V < VSENSE < 1.6V 25Ω AIN– 12pF 1µF 500Ω SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE 1741 F04 4.7µF DIFF AMP Figure 4. Differential Drive with Op Amps 1µF REFLA Reference Operation Figure 5 shows the LTC1741 reference circuitry consisting of a 2.35V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V(±1V differential) or 3.2V(±1.6V differential). Tying the SENSE pin to ground selects the 2V range; tying the SENSE pin to VDD selects the 3.2V range. The 2.35V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 2.35V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference. It will not be stable without this capacitor. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins: REFHA and REFHB for the high reference and REFLA and REFLB for the low reference. The doubled output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 5. 0.1µF REFHB INTERNAL ADC LOW REFERENCE 1741 F05 Figure 5. Equivalent Reference Circuit Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 6a. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device since the logic threshold is close to ground and VDD. The SENSE pin should be tied high or low as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. Input Range The input range can be set based on the application. For oversampled signal processing in which the input frequency is low ( 40MHz), the 2V range will have the best SFDR performance for the 2nd and 3rd harmonics, but the SNR will degrade by 1.5dB. See the Typical Performance Characteristics section. 1741f 13 LTC1741 U W U U APPLICATIO S I FOR ATIO 2.35V VCM VCM 2.35V 4.7µF 4.7µF 12.5k 1.1V 11k SENSE LTC1741 5V 1µF 4 LT1790-1.25 0.1µF 6 1.25V SENSE LTC1741 1µF 1, 2 1741 F06a 1741 F06b Figure 6a. 2.2V Range ADC Figure 6b. 2.5V Range ADC with External Reference LTC1741 5V BIAS VDD ANALOG INPUT TO INTERNAL ADC CIRCUITS 2V BIAS 6k ENC 0.1µF 1:4 CLOCK INPUT 50Ω VDD 2V BIAS 6k ENC 1741 F07 Figure 7. Transformer Driven ENC/ENC 3.3V MC100LVELT22 ENC VTHRESHOLD = 2V 3.3V 130Ω Q0 ENC D0 2V ENC 130Ω LTC1741 0.1µF ENC Q0 83Ω LTC1741 83Ω 1741 F08a 1741 F08b Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter Figure 8b. ENC Drive Using a CMOS-to-PECL Translator 1741f 14 LTC1741 U W U U APPLICATIO S I FOR ATIO Driving the Encode Inputs Maximum and Minimum Encode Rates The noise performance of the LTC1741 can depend on the encode signal quality as much as on the analog input. The ENC/ENC inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 2V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. The maximum encode rate for the LTC1741 is 65Msps. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 7.3ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: At sample rates slower than 65Msps the duty cycle can vary from 50% as long as each half cycle is at least 7.3ns. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. The lower limit of the LTC1741 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC1741 is 1Msps. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. DIGITAL OUTPUTS 1. Differential drive should be used. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.8V to VDD. Each input may be driven from ground to VDD for single-ended drive. Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation LTC1741 VDD OVDD VDD 0.5V TO VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OE OGND 1741 F09 Figure 9. Equivalent Circuit for a Digital Output Buffer 1741f 15 LTC1741 U W U U APPLICATIO S I FOR ATIO down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. example if the converter is driving a DSP powered by a 3V supply then OVDD should be tied to that same 3V supply. OVDD can be powered with any voltage up to 5V. The logic outputs will swing between OGND and OVDD. Output Loading Output Enable As with all high speed/high resolution converters the digital output loading can affect the performance. The digital outputs of the LTC1741 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43Ω on chip. The outputs may be disabled with the output enable pin, OE. OE low disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The voltage on OE can swing between GND and 0VDD. OE should not be driven above 0VDD. Lower OVDD voltages will also help reduce interference from the digital outputs. Format The LTC1741 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MSBINV pin; high selects offset binary. Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. When OF outputs a logic high the converter is either overranged or underranged. GROUNDING AND BYPASSING The LTC1741 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the LTC1741 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. Output Driver Power High quality ceramic bypass capacitors should be used at the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recomended. The large 4.7µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For The LTC1741 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Output Clock The ADC has a delayed version of the ENC input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated just after CLKOUT falls and can be latched on the rising edge of CLKOUT. 1741f 16 LTC1741 U W U U APPLICATIO S I FOR ATIO An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins labeled GND should connect to this plane. All ADC VDD bypass capacitors, reference bypass capacitors and input filter capacitors should connect to this analog plane. The LTC1741 has three output driver ground pins, labeled OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output driver supply, OVDD should be connected to the digital processing system supply. OVDD bypass capacitors should bypass to the digital system ground. The digital processing system ground should be connected to the analog plane at ADC OGND (Pin 38). HEAT TRANSFER Most of the heat generated by the LTC1741 is transferred from the die through the package leads onto the printed circuit board. In particular, ground pins 12, 13, 36 and 37 are fused to the die attach pad. These pins have the lowest thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using multiple vias near the ground pins. A ground plane of this size results in a thermal resistance from the die to ambient of 35°C/W. Smaller area ground planes or poorly connected ground pins will result in higher thermal resistance. 1741f 17 18 E3 GND 8 E4 GND Y1 11 E5 GND JP1 R6 200Ω C31 0.1µF C30 5V 0.1µF 14 • C29 1µF • C2 0.1µF • R1** 0Ω JP3 C5 12pF C15 0.1µF JP4 C14 4.7µF C27 0.1µF C9 0.1µF C26 0.1µF RY* RX* C3 10µF C18 R B 4.7µF 24.9Ω C13 0.1µF C8 4.7µF C7 0.1µF C24 12pF RA 24.9Ω INPUT TWOS RANGE COMPLEMENT SELECT SELECT C32 30pF 5V R22 100Ω C8 4.7µF C25 12pF R10** 0Ω R7 24.9Ω R4 100Ω R2 24.9Ω C11 1µF T2 MINICIRCUITS T1-1T • R21 100Ω JP5 OPTIONAL XTAL CLK R3 100Ω T1 MINICIRCUITS T1-1T *RX, RY = OPTIONAL INPUT RANGE SET **DO NOT INSTALL R1 AND R10 C17 0.1µF 7 4 1 J5 ENCODE INPUT J4 OPTIONAL – INPUT J3 ANALOG INPUT J1 OPTIONAL +INPUT R8 0Ω 5V 4 3 OUT 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C1 2µF SENSE ENC ENC MSBINV GND VDD GND VDD VDD GND REFHB REFLA GND GND REFHA REFLB GND VDD VDD GND AIN– AIN+ GND VCM 2 1 OF 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C4 4.7µF C16 10µF OE CLKOUT OGND NC NC D0 D1 OVDD D2 D3 D4 GND GND OGND D5 D6 D7 D8 OVDD D9 D10 D11 OGND U5 LTC1741 TAB GND IN U3 LT1521-3 E4 PGND E1 5V C10 0.1µF C12 0.1µF C23 0.1µF 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE C19 0.1µF 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C20 0.1µF 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE U4 P174VCX16373V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CLKOUT CLKOUT 3V JP2 C21 0.1µF RN8C 33Ω RN8B 33Ω RN8A 33Ω RN7D 33Ω RN7C 33Ω RN7B 33Ω RN7A 33Ω RN6D 33Ω RN6C 33Ω RN6B 33Ω RN6A 33Ω RN5D 33Ω RN5C 33Ω RN5B 33Ω RN5A 33Ω 1741 TA02 C22 0.1µF U2 10T74ALVC1G86 3V C28 0.1µF R9 33Ω 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J2 3201S-40G1 U U W R5 1Ω APPLICATIO S I FOR ATIO U Evaluation Circuit Schematic of the LTC1741 LTC1741 1741f LTC1741 U W U U APPLICATIO S I FOR ATIO 65 Silkscreen Top Layer 1 Component Side Layer 2 GND Plane Layer 3 Power Plane Layer 4 Solder Side 1741f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1741 U PACKAGE DESCRIPTIO FW Package 48-Lead Plastic TSSOP (6.1mm) (Reference LTC DWG # 05-08-1651) 12.4 – 12.6* (.488 – .496) 0.95 ±0.10 8.1 ±0.10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6.2 ±0.10 7.9 – 8.3 (.311 – .327) 0.32 ±0.05 0.50 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RECOMMENDED SOLDER PAD LAYOUT 1.20 (.0473) MAX 6.0 – 6.2** (.236 – .244) 0° – 8° -T.10 C -C0.09 – 0.20 (.0035 – .008) 0.45 – 0.75 (.018 – .029) 0.50 (.0197) BSC 0.17 – 0.27 (.0067 – .0106) 0.05 – 0.15 (.002 – .006) FW48 TSSOP 0502 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1405 12-Bit, 5Msps Sampling ADC with Parallel Output Pin Compatible with the LTC1420 LTC1406 8-Bit, 20Msps ADC Undersampling Capability up to 70MHz LTC1411 14-Bit, 2.5Msps ADC 5V, No Pipeline Delay, 80dB SINAD LTC1412 12-Bit, 3Msps, Sampling ADC ±5V, No Pipeline Delay, 72dB SINAD LTC1414 14-Bit, 2.2Msps ADC ±5V, 81dB SINAD and 95dB SFDR LTC1420 12-Bit, 10Msps ADC 71dB SINAD and 83dB SFDR at Nyquist LT1461 Micropower Precision Series Reference 0.04% Max Initial Accuracy, 3ppm/°C Drift LTC1666 12-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1667 LTC1667 14-Bit, 50Msps DAC Pin Compatible with the LTC1668, LTC1666 LTC1668 16-Bit, 50Msps DAC 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD LTC1742 12-Bit, 65Msps ADC Pin Compatible with the LTC1741 LTC1743 12-Bit, 50Msps ADC Pin Compatible with the LTC1741 LTC1744 14-Bit, 50Msps ADC Pin Compatible with the LTC1741 LTC1745 12-Bit, 25Msps ADC Pin Compatible with the LTC1741 LTC1746 14-Bit, 25Msps ADC Pin Compatible with the LTC1741 LTC1747 12-Bit, 80Msps ADC Pin Compatible with the LTC1741 LTC1748 14-Bit, 80Msps ADC Pin Compatible with the LTC1741 325MHz, Low Distortion Dual Op Amp Rail-to-Rail Input and Output ® LT 1807 1741f 20 Linear Technology Corporation LT/TP 0603 1K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2003
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