LTC1742
14-Bit, 65Msps Low Noise ADC
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FEATURES
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DESCRIPTIO
The LTC ®1742 is an 65Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1742’s input range to be optimized for a wide
variety of applications.
Sample Rate: 65Msps
76.5dB SNR and 90dB SFDR (3.2V Range)
72.8dB SNR and 90dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.275W
Selectable Input Ranges: ±1V or ±1.6V
240MHz Full Power Bandwidth S/H
Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
48-Pin TSSOP Package
The LTC1742 is perfect for demanding communications
applications with AC performance that includes 76.5dB
SNR and 90dB spurious free dynamic range. Ultralow jitter
of 0.15psRMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±3LSB INL
and ±1LSB DNL.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic levels. The ENC and ENC inputs may be driven
differentially from PECL, GTL and other low swing logic
families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to low voltage
DSPs or FIFOs.
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APPLICATIO S
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The TSSOP package with a flow-through pinout simplifies
the board layout.
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BLOCK DIAGRA
65Msps, 14-Bit ADC with a 2V Differential Input Range
OVDD
0.5V
TO 5V
0.1µF
0.1µF
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT
S/H
AMP
AIN–
CORRECTION
LOGIC AND
SHIFT
REGISTER
14-BIT
PIPELINED ADC
14
OUTPUT
LATCHES
•
•
•
OF
D13
D0
CLKOUT
OGND
SENSE
BUFFER
RANGE
SELECT
VDD
5V
1µF
1µF
DIFF AMP
1µF
VCM
GND
2.35VREF
CONTROL LOGIC
4.7µF
1742 BD
REFLB
REFHA
4.7µF
REFLA
0.1µF
1µF
REFHB ENC
0.1µF
1µF
ENC
MSBINV
OE
DIFFERENTIAL
ENCODE INPUT
1742f
1
LTC1742
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PACKAGE/ORDER INFORMATION
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OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ............................................. 5.5V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Except OE)
(Note 3) ...................................... – 0.3V to (VDD + 0.3V)
OE Input Voltage (Note 4) ........ – 0.3V to (OVDD + 0.3V)
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V)
OGND Voltage ..............................................– 0.3V to 1V
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC1742C ............................................... 0°C to 70°C
LTC1742I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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ABSOLUTE MAXIMUM RATINGS
ORDER PART
NUMBER
TOP VIEW
SENSE
VCM
GND
AIN+
AIN–
GND
VDD
VDD
GND
REFLB
REFHA
GND
GND
REFLA
REFHB
GND
VDD
VDD
GND
VDD
GND
MSBINV
ENC
ENC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OF
OGND
D13
D12
D11
OVDD
D10
D9
D8
D7
OGND
GND
GND
D6
D5
D4
OVDD
D3
D2
D1
D0
OGND
CLKOUT
OE
LTC1742CFW
LTC1742IFW
FW PACKAGE
48-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 35°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Full-Scale Drift
Full-Scale Drift
Offset Drift
Input Referred Noise (Transition Noise)
CONDITIONS
●
(Note 6)
●
(Note 7)
External Reference (SENSE = 1.6V)
Internal Reference
External Reference (SENSE = 1.6V)
Internal Reference
SENSE = 1.6V
MIN
14
–3
–1
– 35
– 3.5
TYP
MAX
±0.75
±0.5
±5
±1
±40
±20
±20
0.82
3
1
35
3.5
UNITS
Bits
LSB
LSB
mV
%FS
ppm/°C
ppm/°C
µV/°C
LSBRMS
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
VIN
IIN
CIN
PARAMETER
Analog Input Range (Note 8)
Analog Input Leakage Current
Analog Input Capacitance
tACQ
tAP
tJITTER
CMRR
Sample-and-Hold Acquisition Time
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
CONDITIONS
4.75V ≤ VDD ≤ 5.25V
0 < AIN+, AIN– < VDD
Sample Mode ENC < ENC
Hold Mode ENC > ENC
MIN
●
●
●
1.5V < (AIN– = AIN+) < 3V
TYP
±1 to ±1.6
–1
MAX
1
8
4
5
0
0.15
80
7.3
UNITS
V
µA
pF
pF
ns
ns
psRMS
dB
1742f
2
LTC1742
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DY A IC ACCURACY
TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
SNR
Signal-to-Noise Ratio
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
75
72.8
76.5
dB
dB
30MHz Input Signal (2V Range)
30MHz Input Signal (3.2V Range)
74
72.5
76.5
dB
dB
72.2
75.8
dB
dB
90
dB
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
SFDR
Spurious Free Dynamic Range
5MHz Input Signal (2V Range)
THD
IMD
UNITS
5MHz Input Signal (3.2V Range) (2nd and 3rd)
90
dB
5MHz Input Signal (3.2V Range) (Other)
95
dB
30MHz Input Signal (2V Range)
90
dB
30MHz Input Signal (3.2V Range) (2nd and 3rd)
80
88
dB
30MHz Input Signal (3.2V Range) (Other)
85
95
dB
83
dB
70MHz Input Signal (2V Range)
S/(N + D)
MAX
70MHz Input Signal (3.2V Range) (2nd and 3rd)
75
dB
70MHz Input Signal (3.2V Range) (Other)
95
dB
72.6
76.2
dB
dB
30MHz Input Signal (2V Range)
30MHz Input Signal (3.2V Range)
72.3
76.0
dB
dB
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
71
71
dB
dB
5MHz Input Signal, First 5 Harmonics (2V Range)
5MHz Input Signal, First 5 Harmonics (3.2V Range)
–90
–90
dB
dB
30MHz Input Signal, First 5 Harmonics (2V Range)
30MHz Input Signal, First 5 Harmonics (3.2V Range)
–90
–85
dB
dB
70MHz Input Signal, First 5 Harmonics (2V Range)
70MHz Input Signal, First 5 Harmonics (3.2V Range)
–78
–74
dB
dB
Intermodulation Distortion
fIN1 = 2.52MHz, fIN2 = 5.2MHz (2V Range)
fIN1 = 2.52MHz, fIN2 = 5.2MHz (3.2V Range)
97
93
dBc
dBc
Sample-and-Hold Bandwidth
RSOURCE = 50Ω
240
MHz
Signal-to-(Noise + Distortion) Ratio
Total Harmonic Distortion
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
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I TER AL REFERE CE CHARACTERISTICS
74.5
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCM Output Voltage
IOUT = 0
2.30
2.35
2.40
VCM Output Tempco
IOUT = 0
VCM Line Regulation
4.75V ≤ VDD ≤ 5.25V
3
mV/V
VCM Output Resistance
1mA ≤ IOUT ≤ 1mA
4
Ω
±30
UNITS
V
ppm/°C
1742f
3
LTC1742
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V, MSBINV and OE
●
VIL
Low Level Input Voltage
VDD = 4.75V, MSBINV and OE
IIN
Digital Input Current
VIN = 0V to VDD
CIN
Digital Input Capacitance
MSBINV and OE Only
VOH
High Level Output Voltage
OVDD = 4.75V
VOL
Low Level Output Voltage
OVDD = 4.75V
Hi-Z Output Leakage D13 to D0
COZ
ISOURCE
ISINK
UNITS
●
0.8
V
●
±10
µA
2.4
●
4
IO = 160µA
IO = 1.6mA
IOZ
MAX
IO = –10µA
IO = – 200µA
TYP
V
1.5
pF
4.74
V
4.74
V
0.05
0.1
●
V
0.4
V
±10
µA
VOUT = 0V to VDD, OE = High
●
Hi-Z Output Capacitance D13 to D0
OE = High (Note 8)
●
Output Source Current
VOUT = 0V
– 50
mA
Output Sink Current
VOUT = 5V
50
mA
15
pF
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POWER REQUIRE E TS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VDD
Positive Supply Voltage
5.25
V
IDD
Positive Supply Current
●
255
275
mA
PDIS
Power Dissipation
●
1.275
1.375
W
OVDD
Digital Output Supply Voltage
VDD
V
4.75
0.5
MAX
UNITS
WU
TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
t0
ENC Period
(Note 9)
●
t1
ENC High
(Note 8)
t2
ENC Low
(Note 8)
t3
Aperture Delay
(Note 8)
t4
ENC to CLKOUT Falling
CL = 10pF (Note 8)
t5
ENC to CLKOUT Rising
CL = 10pF (Note 8)
TYP
MAX
UNITS
15.3
2000
ns
●
7.3
1000
ns
●
7.3
1000
ns
0
●
1
2.4
ns
4
t1 + t 4
ns
ns
For 65Msps 50% Duty Cycle
CL = 10pF (Note 8)
●
8.7
10.1
11.7
ns
t6
ENC to DATA Delay
CL = 10pF (Note 8)
●
2
4.9
7.2
ns
t7
ENC to DATA Delay (Hold Time)
(Note 8)
●
1.4
3.4
4.7
ns
t8
ENC to DATA Delay (Setup Time)
CL = 10pF (Note 8)
For 65Msps 50% Duty Cycle
CL = 10pF (Note 8)
●
8.2
13.4
ns
t9
CLKOUT to DATA Delay (Hold Time),
65Msps 50% Duty Cycle
(Note 8)
●
7
ns
t10
CLKOUT to DATA Delay (Setup Time),
65Msps 50% Duty Cycle
CL = 10pF (Note 8)
●
3
ns
t11
DATA Access Time After OE
CL = 10pF (Note 8)
10
25
ns
t12
BUS Relinquish
(Note 8)
10
25
ns
Data Latency
t0 – t 6
10.5
5
ns
cycles
1742f
4
LTC1742
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When this pin voltage is taken below GND or above OVDD, it will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND or above OVDD without latchup.
Note 5: VDD = 5V, fSAMPLE = 65MHz, differential ENC/ENC = 2VP-P 65MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
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TYPICAL PERFOR A CE CHARACTERISTICS
INL, 3.2V Range
2.5
DNL, 3.2V Range
1.0
TA = 25°C
2.0
–20
0.6
0.5
0
–0.5
–30
–40
AMPLITUDE (dBFS)
0.4
ERROR (LSB)
1.0
ERROR (LSB)
0
TA = 25°C
–10
TA = 25°C
0.8
1.5
0.2
0
–0.2
–50
–60
–70
–80
–1.0
–0.4
–1.5
–0.6
–2.0
–0.8
–110
–2.5
–1.0
–120
0
4096
12288
8192
OUTPUT CODE
–90
–100
0
16384
4096
12288
8192
OUTPUT CODE
1742 G01
16384
0
TA = 25°C
–10
–20
–30
–40
AMPLITUDE (dBFS)
–20
–30
–40
AMPLITUDE (dBFS)
–20
–80
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0
5
20
25
10
15
FREQUENCY (MHz)
30
1742 G04
0
5
30
0
TA = 25°C
–10
–30
–40
–70
20
25
10
15
FREQUENCY (MHz)
8192 Point FFT,
Input Frequency = 30MHz,
–1dB, 3.2V Range
0
TA = 25°C
–10
–60
5
1742 G03
8192 Point FFT,
Input Frequency = 15MHz,
–20dB, 3.2V Range
–50
0
1742 G02
8192 Point FFT,
Input Frequency = 15MHz,
–10dB, 3.2V Range
AMPLITUDE (dBFS)
8192 Point FFT,
Input Frequency = 15MHz,
–1dB, 3.2V Range
20
25
10
15
FREQUENCY (MHz)
30
1742 G05
0
5
20
25
10
15
FREQUENCY (MHz)
30
1742 G06
1742f
5
LTC1742
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT,
Input Frequency = 30MHz,
–10dB, 3.2V Range
0
TA = 25°C
–10
0
TA = 25°C
–10
–20
–20
–30
–40
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–20
–30
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
TA = 25°C
–10
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0
5
20
25
10
15
FREQUENCY (MHz)
30
0
5
20
25
10
15
FREQUENCY (MHz)
1742 G07
30
0
TA = 25°C
–10
–20
–30
–40
AMPLITUDE (dBFS)
–20
–30
–40
AMPLITUDE (dBFS)
–20
–80
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0
5
20
25
10
15
FREQUENCY (MHz)
30
0
5
20
25
10
15
FREQUENCY (MHz)
1742 G10
0
–10
–20
–30
–40
–70
–80
AMPLITUDE (dBFS)
–20
–30
–40
AMPLITUDE (dBFS)
–20
–30
–40
–60
–50
–60
–70
–80
–80
–100
–100
–100
–110
–110
–110
–120
–120
–120
30
1742 G13
0
5
20
25
10
15
FREQUENCY (MHz)
30
1742 G14
TA = 25°C
–60
–90
20
25
10
15
FREQUENCY (MHz)
30
–70
–90
5
20
25
10
15
FREQUENCY (MHz)
–50
–90
0
5
8192 Point FFT,
Input Frequency = 70MHz,
–1dB, 3.2V Range
0
TA = 25°C
–10
–50
0
1742 G12
8192 Point FFT,
Input Frequency = 50MHz,
–20dB, 3.2V Range
0
TA = 25°C
–10
AMPLITUDE (dBFS)
30
1742 G11
8192 Point FFT,
Input Frequency = 50MHz,
–10dB, 3.2V Range
30
0
TA = 25°C
–10
–30
–40
–70
20
25
10
15
FREQUENCY (MHz)
8192 Point FFT,
Input Frequency = 50MHz,
–1dB, 3.2V Range
0
TA = 25°C
–10
–60
5
1742 G09
8192 Point FFT,
Input Frequency = 40MHz,
–20dB, 3.2V Range
–50
0
1742 G08
8192 Point FFT,
Input Frequency = 40MHz,
–10dB, 3.2V Range
AMPLITUDE (dBFS)
8192 Point FFT,
Input Frequency = 40MHz,
–1dB, 3.2V Range
8192 Point FFT,
Input Frequency = 30MHz,
–20dB, 3.2V Range
0
5
20
25
10
15
FREQUENCY (MHz)
30
1742 G15
1742f
6
LTC1742
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT,
Input Frequency = 70MHz,
–10dB, 3.2V Range
0
TA = 25°C
–10
0
TA = 25°C
–10
0
–10
–20
–20
–30
–40
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–20
–30
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
8192 Point 2-Tone FFT,
Input Frequency = 5MHz and
7MHz, –7dB, 3.2V Range
8192 Point FFT,
Input Frequency = 70MHz,
–20dB, 3.2V Range
–50
–60
–70
–80
–80
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
5
20
25
10
15
FREQUENCY (MHz)
30
0
5
20
25
10
15
FREQUENCY (MHz)
30
0
TA = 25°C
–10
0
–10
TA = 25°C
90
80
SFDR (dBc AND dBFS)
100
AMPLITUDE (dBFS)
–20
–30
–40
–80
–50
–60
–70
–80
40
30
–100
20
–110
–110
10
–120
30
0
5
20
25
10
15
FREQUENCY (MHz)
1742 G19
100
SFDR vs 50MHz Input Level
TA = 25°C
100
60
SFDR (dBc AND dBFS)
90
80
70
SFDR vs 70MHz Input Level
120
TA = 25°C
110
dBFS
dBc
50
40
30
90
80
120
110
100
dBFS
70
60
50
dBc
40
30
70
60
50
30
20
10
10
10
0
1742 G22
0
1742 G23
dBc
40
20
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
TA = 25°C
dBFS
90
80
20
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
1742 G21
1742 G20
SFDR vs 30MHz Input Level
120
110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
30
SFDR (dBc AND dBFS)
20
25
10
15
FREQUENCY (MHz)
dBc
50
–100
5
dBFS
60
–90
0
TA = 25°C
70
–90
–120
30
SFDR vs 15MHz Input Level
–20
–70
20
25
10
15
FREQUENCY (MHz)
120
110
–30
–40
–60
5
1742 G18
8192 Point 2-Tone FFT,
Input Frequency = 68MHz and
70MHz, –7dB, 3.2V Range
–50
0
1742 G17
8192 Point 2-Tone FFT,
Input Frequency = 25MHz and
30MHz, –7dB, 3.2V Range
AMPLITUDE (dBFS)
–60
–70
–90
1742 G16
SFDR (dBc AND dBFS)
–50
–90
0
TA = 25°C
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
1742 G24
1742f
7
LTC1742
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SFDR vs Input Frequency and
Amplitude, 2V Range,
2nd and 3rd Harmonic
SFDR vs Input Frequency and
Amplitude, 3.2V Range,
2nd and 3rd Harmonic
–20dB
95
TA = 25°C
SFDR (dBFS)
–1dB
85
–1dB
80
75
70
70
65
65
0
20
40
80
60
INPUT FREQUENCY (MHz)
60
100
15000
5000
20
80
60
INPUT FREQUENCY (MHz)
0
40
100
0
8140 8141 8142 8143 8144 8145 8146 8147
CODE
1742 G26
SNR vs Input Frequency
3.2V and 2V Range
77.0
1742 G27
SNR vs Sample Rate, 5MHz Input, –
1dB, 3.2V Range
78
TA = 25°C
3.2V RANGE
76.0
20000
10000
1742 G25
76.5
25000
–6dB
80
TA = 25°C
30000
–10dB
–6dB
85
60
TA = 25°C
–20dB
90
75
Shorted Input Histogram
35000
95
–10dB
90
SFDR (dBFS)
100
COUNT
100
TA = 25°C
77
76
75.0
SNR (dBFS)
SNR (dBFS)
75.5
74.5
74.0
73.5
75
74
73.0
2V RANGE
72.5
73
72.0
71.5
0
72
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
0
10
20
30 40 50 60 70
SAMPLE RATE (Msps)
1742 G28
Supply Current vs Sample Rate
270
TA = 25°C
95
SUPPLY CURRENT (mA)
SFDR (dBFS)
TA = 25°C
260
90
85
80
75
70
250
240
230
220
65
60
90
1742 G29
SFDR vs Sample Rate, 5MHz Input,
–1dB, 3.2V Range
100
80
210
0
10
20
30 40 50 60 70
SAMPLE RATE (Msps)
80
90
1742 G30
0
20
40
60
SAMPLE RATE (Msps)
80
1742 G31
1742f
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SENSE (Pin 1): Reference Sense Pin. Ground selects ±1V.
VDD selects ±1.6V. Greater than 1V and less than 1.6V
applied to the SENSE pin selects an input range of ±VSENSE,
±1.6V is the largest valid input range.
VCM (Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power
Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
with 1µF ceramic chip capacitors at Pin 8 and Pin 18.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic
capacitor and to ground with 1µF ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic capacitor and to ground with 1µF ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 11.
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on the
positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z. OE should not exceed the
voltage on OVDD.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs.
OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
1742f
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TI I G DIAGRA
N
ANALOG
INPUT
•
t3
t1
t2
t0
ENC
t7
t8
DATA (N – 4)
DB13 TO DB0
DATA (N – 5)
DB13 TO DB0
DATA
DATA (N – 3)
t6
CLKOUT
t4
t5
t10
t9
OE
t11
DATA N
DB13 TO DB0, OF AND CLKOUT
1742 TD
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DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log
V22 + V32 + V 42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
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Spurious Free Dynamic Range (SFDR)
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
SNRJITTER = –20log (2π) • FIN • TJITTER
CONVERTER OPERATION
The LTC1742 is a CMOS pipelined multistep converter.
The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
see the Timing Diagram section. The analog input is
differential for improved common mode noise immunity
and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the
sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
The LTC1742 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
AIN+
AIN–
VCM
FIRST PIPELINED
ADC STAGE
(5 BITS)
INPUT
S/H
SECOND PIPELINED
ADC STAGE
(4 BITS)
THIRD PIPELINED
ADC STAGE
(4 BITS)
FOURTH PIPELINED
ADC STAGE
(4 BITS)
2.35V
REFERENCE
4.7µF
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
REFL
SENSE
REFH
INTERNAL CLOCK SIGNALS
OVDD 0.5V TO
5V
OF
REF
BUF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
D13
CONTROL LOGIC
AND
CALIBRATION LOGIC
OUTPUT
DRIVERS
D0
CLKOUT
1742 F01
REFLB REFHA
4.7µF
0.1µF
1µF
REFLA REFHB
ENC
ENC
MSBINV
OE
OGND
0.1µF
1µF
Figure 1. Functional Block Diagram
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In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC1742
CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in lowest possible noise for a
given sampling capacitor size. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC/ENC transitions from low to
LTC1742
VDD
CSAMPLE
4pF
AIN+
CPARASITIC
4pF
VDD
CSAMPLE
4pF
AIN–
CPARASITIC
4pF
5V
BIAS
2V
6k
ENC
ENC
6k
2V
1742 F02
Figure 2. Equivalent Input Circuit
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8V for the 3.2V range or ±0.5V for the 2V range, around
a common mode voltage of 2.35V. The VCM output pin
(Pin␣ 2) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 4.7µF or greater capacitor.
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Input Drive Impedance
As with all high performance, high speed ADCs the dynamic performance of the LTC1742 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sampleand-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The S/H
circuit is optimized for a 50Ω source impedance. If the
source impedance is less than 50Ω, a series resistor
should be added to increase this impedance to 50Ω. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1742 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100Ω for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
The 25Ω resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 100MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
Reference Operation
Figure 5 shows the LTC1742 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges
of 2V(±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
VCM
4.7µF
5V
SINGLE-ENDED
INPUT
2.35V ±1/2
RANGE
VCM
0.1µF
1:1
100Ω
25Ω
100Ω
25Ω
12pF
12pF
25Ω
1/2 LT1810
4.7µF
ANALOG
INPUT
12pF
+
25Ω AIN+
–
LTC1742
12pF
25Ω AIN+
LTC1742
100Ω
25Ω AIN–
+
25Ω
1/2 LT1810
–
12pF
500Ω
25Ω AIN–
12pF
500Ω
1742 F04
1742 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4. Differential Drive with Op Amps
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mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry.
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1µF ceramic capacitor.
An external bypass capacitor is required for the 2.35V
reference output, VCM. This provides a high frequency low
impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the
reference. It will not be stable without this capacitor.
Input Range
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be connected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
The input range can be set based on the application. For
oversampled signal processing in which the input frequency is low ( 40MHz), the 2V range will have the best SFDR performance for the 2nd and 3rd harmonics, but the SNR will
degrade by 3.5dB. See the Typical Performance Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC1742 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
LTC1742
VCM
2.35V
4Ω
2.35V BANDGAP
REFERENCE
VCM
2.35V
4.7µF
1.6V
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 • VSENSE FOR
1V < VSENSE < 1.6V
1µF
4.7µF
1V
12.5k
1.1V
RANGE
DETECT
AND
CONTROL
LTC1742
SENSE
1µF
11k
SENSE
1742 F06a
REFLB
0.1µF
REFHA
BUFFER
INTERNAL ADC
HIGH REFERENCE
Figure 6a. 2.2V Range ADC
2.35V
4.7µF
4.7µF
DIFF AMP
1µF
REFLA
0.1µF
REFHB
VCM
5V
0.1µF
INTERNAL ADC
LOW REFERENCE
4
LT1790-1.25
1, 2
6
1.25V
SENSE
LTC1742
1µF
1742 F06b
1742 F05
Figure 5. Equivalent Reference Circuit
Figure 6b. 2.5V Range ADC with External Reference
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LTC1742
5V
BIAS
VDD
ANALOG INPUT
TO INTERNAL
ADC CIRCUITS
2V BIAS
6k
ENC
0.1µF
1:4
CLOCK
INPUT
50Ω
VDD
2V BIAS
6k
ENC
1742 F07
Figure 7. Transformer Driven ENC/ENC
3.3V
MC100LVELT22
ENC
VTHRESHOLD = 2V
3.3V
130Ω
Q0
ENC
D0
2V ENC
130Ω
LTC1742
0.1µF
ENC
Q0
83Ω
LTC1742
83Ω
1742 F08a
1742 F08b
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
In applications where jitter is critical (high input frequencies) take the following into consideration:
Maximum and Minimum Encode Rates
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The maximum encode rate for the LTC1742 is 65Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must have at least
7.3ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
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At sample rates slower than 65Msps the duty cycle can
vary from 50% as long as each half cycle is at least 7.3ns.
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
The lower limit of the LTC1742 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency for the LTC1742 is 1Msps.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Format
The LTC1742 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
DIGITAL OUTPUTS
Overflow Bit
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1742 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OVDD should be tied to that same 3V supply.
LTC1742
VDD
OVDD
VDD
0.5V TO
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
1742 F09
Figure 9. Equivalent Circuit for a Digital Output Buffer
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OVDD can be powered with any voltage up to 5V. The logic
outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE low disables all data outputs including OF and
CLKOUT. The data access and bus relinquish times are too
slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is
intended for use during long periods of inactivity. The
voltage on OE can swing between GND and OVDD. OE
should not be driven above OVDD.
GROUNDING AND BYPASSING
The LTC1742 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the
LTC1742 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as
shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7µF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1742 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1742 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypass capacitors should
bypass to the digital system ground. The digital processing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1742 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
1742f
17
18
E3
GND
8
E4
GND
Y1
11
E5
GND
JP1
R6
200Ω
C31
0.1µF
C30
5V 0.1µF
14
•
C29
1µF
•
C2
0.1µF
•
R1**
0Ω
JP3
C5
12pF
C15
0.1µF
JP4
C14
4.7µF
C27
0.1µF
C9
0.1µF
C26
0.1µF
RY*
RX*
C3
10µF
C18 R
B
4.7µF 24.9Ω
C13
0.1µF
C8
4.7µF
C7
0.1µF
C24
12pF
RA
24.9Ω
INPUT
TWOS
RANGE COMPLEMENT
SELECT
SELECT
C32
30pF
5V
R22
100Ω
C8
4.7µF
C25
12pF
R10**
0Ω
R7
24.9Ω
R4
100Ω
R2
24.9Ω
C11
1µF
T2
MINICIRCUITS T1-1T
•
R21
100Ω
JP5
OPTIONAL
XTAL CLK
R3
100Ω
T1
MINICIRCUITS T1-1T
*RX, RY = OPTIONAL INPUT RANGE SET
**DO NOT INSTALL R1 AND R10
C17
0.1µF
7
4
1
J5
ENCODE
INPUT
J4
OPTIONAL
– INPUT
J3
ANALOG
INPUT
J1
OPTIONAL
+INPUT
R8
0Ω
5V
4
3
OUT
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C1
2µF
SENSE
ENC
ENC
MSBINV
GND
VDD
GND
VDD
VDD
GND
REFHB
REFLA
GND
GND
REFHA
REFLB
GND
VDD
VDD
GND
AIN–
AIN+
GND
VCM
2
1
OF
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C4
4.7µF
C16
10µF
OE
CLKOUT
OGND
D0
D1
D2
D3
OVDD
D4
D5
D6
GND
GND
OGND
D7
D8
D9
D10
OVDD
D11
D12
D13
OGND
U5
LTC1742
TAB GND
IN
U3
LT1521-3
E4
PGND
E1
5V
C10 0.1µF
C12 0.1µF
C23
0.1µF
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
C19
0.1µF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C20
0.1µF
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
U4
P174VCX16373V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLKOUT
CLKOUT
3V
JP2
C21
0.1µF
RN8C 33Ω
RN8B 33Ω
RN8A 33Ω
RN7D 33Ω
RN7C 33Ω
RN7B 33Ω
RN7A 33Ω
RN6D 33Ω
RN6C 33Ω
RN6B 33Ω
RN6A 33Ω
RN5D 33Ω
RN5C 33Ω
RN5B 33Ω
RN5A 33Ω
1742 TA01
C22
0.1µF
U2
10T74ALVC1G86
3V
C28
0.1µF
R9
33Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J2
3201S-40G1
U U
W
R5
1Ω
APPLICATIO S I FOR ATIO
U
Evaluation Circuit Schematic of the LTC1742
LTC1742
1742f
LTC1742
U
W
U U
APPLICATIO S I FOR ATIO
Silkscreen Top
Layer 1 Component Side
Layer 2 GND Plane
Layer 3 Power Plane
Layer 4 Solder Side
1742f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1742
U
PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.4 – 12.6*
(.488 – .496)
0.95 ±0.10
8.1 ±0.10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
6.2 ±0.10
7.9 – 8.3
(.311 – .327)
0.32 ±0.05
0.50 TYP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.0473)
MAX
6.0 – 6.2**
(.236 – .244)
0° – 8°
-T.10 C
-C0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
0.50
(.0197)
BSC
0.17 – 0.27
(.0067 – .0106)
0.05 – 0.15
(.002 – .006)
FW48 TSSOP 0502
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1405
LTC1406
LTC1411
LTC1412
LTC1414
LTC1420
LT®1461
LTC1666
LTC1667
LTC1668
LTC1741
LTC1743
LTC1744
LTC1745
LTC1746
LTC1747
LTC1748
LT1807
12-Bit, 5Msps Sampling ADC with Parallel Output
8-Bit, 20Msps ADC
14-Bit, 2.5Msps ADC
12-Bit, 3Msps, Sampling ADC
14-Bit, 2.2Msps ADC
12-Bit, 10Msps ADC
Micropower Precision Series Reference
12-Bit, 50Msps DAC
14-Bit, 50Msps DAC
16-Bit, 50Msps DAC
12-Bit, 65Msps ADC
12-Bit, 50Msps ADC
14-Bit, 50Msps ADC
12-Bit, 25Msps ADC
14-Bit, 25Msps ADC
12-Bit, 80Msps ADC
14-Bit, 80Msps ADC
325MHz, Low Distortion Dual Op Amp
Pin Compatible with the LTC1420
Undersampling Capability up to 70MHz
5V, No Pipeline Delay, 80dB SINAD
±5V, No Pipeline Delay, 72dB SINAD
±5V, 81dB SINAD and 95dB SFDR
71dB SINAD and 83dB SFDR at Nyquist
0.04% Max Initial Accuracy, 3ppm/°C Drift
Pin Compatible with the LTC1668, LTC1667
Pin Compatible with the LTC1668, LTC1666
16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Pin Compatible with the LTC1742
Rail-to-Rail Input and Output
1742f
20
Linear Technology Corporation
LT/TP 0603 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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湘ICP备2023018690号
