LTC1745
Low Noise,12-Bit, 25Msps ADC
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DESCRIPTIO
FEATURES
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The LTC ®1745 is a 25Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1745’s input range to be optimized for a wide
variety of applications.
Sample Rate: 25Msps
72.5dB SNR and 91dB SFDR (3.2V Range)
71dB SNR and 96dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Low Power Dissipation: 380mW
Selectable Input Ranges: ±1V or ±1.6V
240MHz Full Power Bandwidth S/H
Pin Compatible Family
25 Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50 Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65 Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80 Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
The LTC1745 is perfect for demanding communications
applications with AC performance that includes 72.5dB
SNR and 91dB spurious free dynamic range. Ultralow jitter
of 0.3psRMS allows undersampling with excellent noise
performance. DC specs include ±1LSB INL maximum and
±0.75LSB DNL over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate digital
output power supply can be operated from 0.5V to 5V,
making it easy to connect directly to low voltage DSPs
or FIFOs.
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APPLICATIO S
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Telecommunications
Medical Imaging
Receivers
Base Stations
Spectrum Analysis
Imaging Systems
The TSSOP package with a flow-through pinout simplifies
the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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BLOCK DIAGRA
25Msps, 12-Bit ADC with a ±1V Differential Input Range
OVDD
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT
12
12-BIT
PIPELINED ADC
S/H
AMP
AIN–
OUTPUT
LATCHES
SENSE
•
•
•
OF
D11
0.1µF
0.5V TO 5V
0.1µF
D0
CLKOUT
OGND
BUFFER
VDD
RANGE
SELECT
VCM
5V
1µF
DIFF AMP
1µF
1µF
GND
2.35VREF
CONTROL LOGIC
4.7µF
1745 BD
REFLB
REFHA
REFLA
REFHB
ENC
ENC
MSBINV
OE
4.7µF
0.1µF
1µF
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
1745f
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LTC1745
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
OVDD = VDD (Notes 1, 2)
ORDER PART
NUMBER
TOP VIEW
Supply Voltage (VDD) ............................................. 5.5V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..... – 0.3V to (VDD + 0.3V)
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V)
OGND Voltage ..............................................– 0.3V to 1V
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC1745C ............................................... 0°C to 70°C
LTC1745I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SENSE
VCM
GND
AIN+
AIN–
GND
VDD
VDD
GND
REFLB
REFHA
GND
GND
REFLA
REFHB
GND
VDD
VDD
GND
VDD
GND
MSBINV
ENC
ENC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OF
OGND
D11
D10
D9
OVDD
D8
D7
D6
D5
OGND
GND
GND
D4
D3
D2
OVDD
D1
D0
NC
NC
OGND
CLKOUT
OE
LTC1745CFW
LTC1745IFW
FW PACKAGE
48-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 35°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CO VERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
Integral Linearity Error
(Note 6)
TYP
MAX
UNITS
●
12
Bits
●
–1
±0.4
1
LSB
●
–0.75
±0.2
0.75
LSB
Offset Error
(Note 7)
●
– 30
±5
30
mV
Gain Error
External Reference (SENSE = 1.6V)
●
– 2.5
±1
2.5
%FS
Full-Scale Tempco
IOUT(REF) = 0
Differential Linearity Error
±40
ppm/°C
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 8)
4.75V ≤ VDD ≤ 5.25V
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
●
–1
1
15
0
0.3
1.0V < (AIN = AIN
+) < 3.5V
80
UNITS
V
8
4
●
–
MAX
±1 to ±1.6
●
Sample Mode ENC < ENC
Hold Mode ENC > ENC
TYP
µA
pF
pF
18
ns
ns
psRMS
dB
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LTC1745
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DY A IC ACCURACY
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
SFDR
S/(N + D)
THD
IMD
Spurious Free Dynamic Range
Signal-to-(Noise + Distortion) Ratio
Total Harmonic Distortion
MIN
TYP
71
71
72.5
dBFS
dBFS
30MHz Input Signal (2V Range)
30MHz Input Signal (3.2V Range)
71
72
dBFS
dBFS
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
70
71.5
dBFS
dBFS
●
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
MAX
UNITS
96
91
dB
dB
30MHz Input Signal (2V Range)
30MHz Input Signal (3.2V Range)
93.5
87
dB
dB
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
79
70.5
dB
dB
71
72.5
dBFS
dBFS
30MHz Input Signal (2V Range)
30MHz Input Signal (3.2V Range)
71
72
dBFS
dBFS
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
69.5
68.5
dBFS
dBFS
5MHz Input Signal, First 5 Harmonics (2V Range)
5MHz Input Signal, First 5 Harmonics (3.2V Range)
– 92
– 90
dB
dB
30MHz Input Signal, First 5 Harmonics (2V Range)
30MHz Input Signal, First 5 Harmonics (3.2V Range)
– 91.5
– 86.5
dB
dB
70MHz Input Signal, First 5 Harmonics (2V Range)
70MHz Input Signal, First 5 Harmonics (3.2V Range)
–77.5
–70
dB
dB
●
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
●
78
71
Intermodulation Distortion
fIN1 = 4MHz, fIN2 = 5.1MHz (2V Range)
fIN1 = 4MHz, fIN2 = 5.1MHz (3.2V Range)
85
84
dBc
dBc
Sample-and-Hold Bandwidth
RSOURCE = 50Ω
240
MHz
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I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCM Output Voltage
IOUT = 0
2.29
2.35
2.41
VCM Output Tempco
IOUT = 0
VCM Line Regulation
4.75V ≤ VDD ≤ 5.25V
3
mV/V
VCM Output Resistance
1mA ≤ IOUT ≤ 1mA
4
Ω
±30
UNITS
V
ppm/°C
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LTC1745
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
MIN
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
MSBINV and OE Only
VOH
High Level Output Voltage
OVDD = 4.75V
IO = –10µA
IO = – 200µA
VOL
Low Level Output Voltage
OVDD = 4.75V
Hi-Z Output Leakage D11 to D0
COZ
ISOURCE
ISINK
MAX
UNITS
V
1.5
pF
4.74
V
4
IO = 160µA
IO = 1.6mA
IOZ
●
TYP
2.4
V
0.05
0.1
●
V
0.4
V
±10
µA
VOUT = 0V to VDD, OE = High
●
Hi-Z Output Capacitance D11 to D0
OE = High (Note 8)
●
Output Source Current
VOUT = 0V
– 50
mA
Output Sink Current
VOUT = 5V
50
mA
15
pF
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POWER REQUIRE E TS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VDD
Positive Supply Voltage
IDD
Positive Supply Current
2V Range, Full-Scale Input
●
76
91
mA
PDIS
Power Dissipation
2V Range, Full-Scale Input
●
380
455
mW
OVDD
Digital Output Supply Voltage
VDD
V
4.75
MAX
UNITS
5.25
0.5
V
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
fSAMPLE
Sampling Frequency
(Note 9)
●
1
t1
ENC Low Time
(Note 9)
●
19
20
1000
ns
t2
ENC High Time
(Note 9)
●
t3
Aperture Delay of Sample-and-Hold
19
20
1000
ns
t4
ENC to Data Delay
CL = 10pF (Note 8)
●
1.4
4
10
ns
t5
ENC to CLKOUT Delay
CL = 10pF (Note 8)
●
t6
CLKOUT to Data Delay
CL = 10pF (Note 8)
●
0.5
2
5
ns
0
2
t7
DATA Access Time After OE ↓
CL = 10pF (Note 8)
10
25
t8
BUS Relinquish Time
(Note 8)
10
25
25
0
Data Latency
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to VDD.
5
UNITS
MHz
ns
ns
ns
ns
cycles
Note 5: VDD = 5V, fSAMPLE = 25MHz, differential ENC/ENC = 2VP-P 25MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
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LTC1745
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TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL
Nonaveraged, 32768 Point FFT,
Input Frequency = 5MHz,
3.2V Range
Typical DNL
1.0
1.0
0
–10
–20
0.5
0
–30
AMPLITUDE (dB)
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
–0.5
–0.5
–40
–50
–60
–70
–80
–90
–100
–110
–1.0
–1.0
0
1000
2000
CODE
3000
0
4000
1000
2000
CODE
3000
Nonaveraged, 32768 Point FFT,
Input Frequency = 5MHz,
2V Range
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–70
–80
AMPLITUDE (dB)
0
–60
–50
–60
–70
–80
–70
–80
–90
–90
–100
–100
–110
–110
–110
–120
–120
4
8
6
FREQUENCY (MHz)
10
12
–120
0
2
4
8
6
FREQUENCY (MHz)
10
1745 G04
12
0
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–70
–50
–60
–70
–80
–60
–70
–80
–90
–90
–90
–100
–100
–110
–110
–110
–120
–120
2
4
8
6
FREQUENCY (MHz)
10
12
1745 G07
12
–50
–100
0
10
Nonaveraged, 32768 Point
2-Tone FFT, Input Frequency =
4MHz and 5.1MHz, 2V Range
–10
–60
4
8
6
FREQUENCY (MHz)
1745 G06
Nonaveraged, 32768 Point
2-Tone FFT, Input Frequency =
4MHz and 5.1MHz, 3.2V Range
–50
2
1745 G05
Nonaveraged, 32768 Point FFT,
Input Frequency = 70MHz,
2V Range
12
–60
–90
2
10
–50
–100
0
4
8
6
FREQUENCY (MHz)
Nonaveraged, 32768 Point FFT,
Input Frequency = 30MHz,
2V Range
–10
–50
2
1745 G03
Nonaveraged, 32768 Point FFT,
Input Frequency = 30MHz,
3.2V Range
AMPLITUDE (dB)
AMPLITUDE (dB)
0
1745 G02
1745 G01
AMPLITUDE (dB)
–120
4000
–120
0
2
4
8
6
FREQUENCY (MHz)
10
12
1745 G08
0
2
4
8
6
FREQUENCY (MHz)
10
12
1745 G09
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LTC1745
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TYPICAL PERFOR A CE CHARACTERISTICS
SNR vs Sample Rate,
Input Frequency = 5MHz, –1dB
Grounded Input Histogram
35000
73
30000
72
25000
71
SFDR vs Sample Rate,
Input Frequency = 5MHz, –1dB
110
3.2V RANGE
3.2V RANGE
20000
15000
2V RANGE
70
69
10000
68
5000
67
66
0
2042
CODE
2041
SFDR (dB)
SNR (dBFS)
COUNT
100
2043
80
70
60
0
10
20
30
40
SAMPLE RATE (Msps)
50
60
0
10
SNR vs Input Frequency and
Amplitude 3.2V Range
60
1745 G12
80
75
75
–1dBFS
70
–1dBFS
70
SNR (dB)
–6dBFS
65
60
–6dBFS
65
60
55
55
–20dBFS
–20dBFS
50
0
50
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
1745 G13
1745 G14
SFDR vs Input Frequency
and Amplitude, 3.2V Range
SFDR vs Input Frequency
and Amplitude, 2V Range
110
110
–20dBFS
100
–20dBFS
100
90
–6dBFS
SFDR (dBFS)
SFDR (dBFS)
50
SNR vs Input Frequency and
Amplitude 2V Range
80
90
20
30
40
SAMPLE RATE (Msps)
1745 G11
1745 G10
SNR (dB)
2V RANGE
90
80
–1dBFS
70
–6dBFS
80
–1dBFS
70
60
60
50
50
40
0 10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
1746 G15
40
0
50
150
100
INPUT FREQUENCY (MHz)
200
1745 G16
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LTC1745
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TYPICAL PERFOR A CE CHARACTERISTICS
2nd and 3rd Harmonic vs Input
Frequency, 3.2V Range, –1dB
2nd and 3rd Harmonic vs Input
Frequency, 2V Range, –1dB
–30
–30
–50
–50
Worst Harmonic 4th or Higher vs
Input Frequency, 3.2V Range, –1dB
–60
–70
–70
3RD HARMONIC
–90
2ND HARMONIC
–110
–130
DISTORTION (dB)
DISTORTION (dB)
DISTORTION (dB)
2ND HARMONIC
–70
3ND HARMONIC
–90
–130
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
–90
–100
–110
0
–80
–110
0
30
30
40
INPUT FREQUENCY (MHz)
1745 G17
50
0
10 20 30 40 50 60 70 80 90 100
INPUT FREQUENCY (MHz)
1746 G19
1745 G18
Worst Harmonic 4th or Higher vs
Input Frequency, 2V Range, –1dB
SFDR vs Input Amplitude,
2V Range, 5MHz Input Frequency
–60
110
–70
100
Power vs Sample Rate,
Input Frequency = 5MHz
500
–80
–90
–100
460
440
SFDR dBFS
POWER (mW)
SFDR (dBc AND dBFS)
DISTORTION (dB)
480
90
80
SFDR dBc
420
3.2V RANGE
400
2V RANGE
380
360
340
70
320
–110
0
50
150
100
INPUT FREQUENCY (MHz)
200
1745 G20
60
–60
300
–20
–40
INPUT AMPLITUDE (dBFS)
0
1745 G21
0
10
30
40
20
SAMPLE RATE (Msps)
50
60
1745 G22
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LTC1745
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PI FU CTIO S
SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V. VDD selects ±1.6V. Greater than 1V and less than
1.6V applied to the SENSE pin selects an input range of
±VSENSE, ±1.6V is the largest valid input range.
VCM (Pin 2): 2.35V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC
Power Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN – (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to GND
with 1µF ceramic chip capacitor.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10
with 0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15
with 0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF
ceramic capacitor and to ground with 1µF ceramic
capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14
with 0.1µF ceramic chip capacitor. Do not connect to
Pin␣ 11.
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on
the positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
NC (Pins 28, 29): Do Not Connect These Pins.
D0-D1 (Pins 30, 31): Digital Outputs. D0 is the LSB.
OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
D2-D4 (Pins 33 to 35): Digital Outputs.
D5-D8 (Pins 39 to 42): Digital Outputs.
D9-D11 (Pins 44 to 46): Digital Outputs. D11 is the MSB.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
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LTC1745
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TI I G DIAGRA
N
ANALOG
INPUT
t3
t2
t1
ENCODE
t6
t4
DATA
t5
DATA (N – 3)
D11 TO D0
DATA (N – 4)
D11 TO D0
DATA (N – 5)
D11 TO D0
t5
CLKOUT
t7
t8
OE
DATA N
D11 TO D0, OF AND CLKOUT
DATA
1745 TD
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OVDD
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT
AIN–
12
12-BIT
PIPELINED ADC
S/H
AMP
OUTPUT
LATCHES
SENSE
•
•
•
OF
D11
0.1µF
0.5V TO 5V
0.1µF
D0
CLKOUT
OGND
BUFFER
VDD
RANGE
SELECT
VCM
5V
1µF
DIFF AMP
1µF
1µF
GND
2.35VREF
CONTROL LOGIC
4.7µF
1745 BD
REFLB
REFHA
REFLA
REFHB
ENC
ENC
MSBINV
OE
4.7µF
0.1µF
1µF
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
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LTC1745
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APPLICATIO S I FOR ATIO
The signal-to-noise plus distortion ratio [S / (N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Ratio
Spurious Free Dynamic Range (SFDR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log
V22 + V32 + V 42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = – 20log (2π) • FIN • TJITTER
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CONVERTER OPERATION
brevity, the text will refer to ENC greater than ENC as ENC
high and ENC less than ENC as ENC low.
As shown in Figure 1, the LTC1745 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The encode input is also differential for improved common mode
noise immunity.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
The LTC1745 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For
AIN+
–
AIN
VCM
INPUT
S/H
FIRST STAGE
SECOND STAGE
THIRD STAGE
FOURTH STAGE
5-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
FLASH
ADC
2.35V
REFERENCE
4.7µF
SHIFT REGISTER AND CORRECTION
RANGE
SELECT
INTERNAL
REFERENCES TO ADC
SENSE
INTERNAL
CLOCK SIGNALS
OVDD
0.5V TO
5V
REF
BUF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
OF
CONTROL
LOGIC
OUTPUT
DRIVERS
D11
•
•
•
D0
CLKOUT
1745 F01
REFLB
REFHA
REFLA
REFHB
ENC
ENC
MSBINV
OE
OGND
4.7µF
0.1µF
1µF
0.1µF
1µF
Figure 1. Functional Block Diagram
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When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8V for the 3.2V range or ±0.5V for the 2V range, around
a common mode voltage of 2.35V. The VCM output pin
(Pin␣ 2) may be used to provide the common mode bias
level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to
an op amp differential driver circuit. The VCM pin must be
bypassed to ground close to the ADC with 4.7µF or greater
capacitor.
LTC1745
SAMPLE/HOLD OPERATION AND INPUT DRIVE
VDD
CSAMPLE
4pF
Sample Hold Operation
Figure 2 shows an equivalent circuit for the LTC1745
CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in the lowest possible noise for
a given sampling capacitor size. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sampling capacitors, and they charge to and track the differential input voltage. When ENC/ENC transitions from low to
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
AIN+
CPARASITIC
4pF
VDD
AIN–
CSAMPLE
4pF
CPARASITIC
4pF
5V
BIAS
2V
6k
ENC
ENC
6k
2V
1745 F02
Figure 2. Equivalent Input Circuit
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Input Drive Impedance
Input Drive Circuits
As with all high performance, high speed ADCs the dynamic performance of the LTC1745 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sampleand-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
Figure 3 shows the LTC1745 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100Ω for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequencies below 1MHz.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The S/H
circuit is optimized for a 50Ω source impedance. If the
source impedance is less than 50Ω, a series resistor
should be added to increase this impedance to 50Ω. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
The 25Ω resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 50MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
VCM
4.7µF
5V
SINGLE-ENDED
INPUT
2.35V ±1/2
RANGE
VCM
4.7µF
12pF
+
25Ω
1/2 LT1810
25Ω A +
IN
LTC1745
–
12pF
0.1µF
1:1
ANALOG
INPUT
100Ω
100Ω
25Ω
12pF
25Ω AIN+
25Ω
12pF
25Ω AIN
LTC1745
100Ω
+
25Ω
–
1/2 LT1810
–
12pF
1745 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
500Ω
25Ω AIN–
12pF
500Ω
1745 F04
Figure 4. Differential Drive with Op Amps
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Reference Operation
Figure 5 shows the LTC1745 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges
of 2V(±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry.
An external bypass capacitor of 4.7µF or larger is required
for the 2.35V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry. This is also the compensation capacitor
for the reference. It will not be stable without this
capacitor.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be connected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1µF ceramic capacitor.
LTC1745
VCM
2.35V
4Ω
VCM
2.35V
2.35V BANDGAP
REFERENCE
4.7µF
4.7µF
1.6V
12.5k
1V
1.1V
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 • VSENSE FOR
1V < VSENSE < 1.6V
1µF
RANGE
DETECT
AND
CONTROL
SENSE
1µF
11k
SENSE
1745 F06a
REFLB
0.1µF
REFHA
BUFFER
Figure 6a. 2.2V Range ADC
INTERNAL ADC
HIGH REFERENCE
2.35V
4.7µF
DIFF AMP
REFLA
REFHB
VCM
4.7µF
1µF
0.1µF
LTC1745
5V
0.1µF
INTERNAL ADC
LOW REFERENCE
4
LT1790-1.25
1, 2
6
1.25V
SENSE
LTC1745
1µF
1745 F06b
1745 F05
Figure 5. Equivalent Reference Circuit
Figure 6b. 2.5V Range ADC with an External Reference
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Input Range
Driving the Encode Inputs
The input range can be set based on the application. For
oversampled signal processing in which the input frequency is low (10MHz), the 2V range will have the best SFDR performance but the SNR will degrade by 1.5dB. See the Typical
Performance Characteristics section.
The noise performance of the LTC1745 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
LTC1745
5V
BIAS
VDD
TO INTERNAL
ADC CIRCUITS
2V BIAS
6k
ANALOG INPUT
ENC
0.1µF
1:4
CLOCK
INPUT
50Ω
VDD
2V BIAS
6k
ENC
1745 F07
Figure 7. Transformer Driven ENC/ENC with Equivalent Encode Input Circuit
3.3V
MC100LVELT22
ENC
VTHRESHOLD = 2V
2V ENC
3.3V
130Ω
Q0
ENC
D0
LTC1745
ENC
Q0
0.1µF
83Ω
1745 F08a
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
130Ω
LTC1745
83Ω
1745 F08b
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
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Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
At sample rates slower than 25Msps the duty cycle can
vary from 50% as long as each half cycle is at least 19ns.
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1745 is 25Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must have at least
19ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
The lower limit of the LTC1745 sample rate is determined
by the droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals
on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating
frequency for the LTC1745 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
LTC1745
VDD
OVDD
VDD
0.5V TO
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
1745 F09
Figure 9. Equivalent Circuit for a Digital Output Buffer
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Output Loading
Output Driver Power
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1745 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OVDD should be tied to that same 3V supply.
OVDD can be powered with any voltage up to 5V. The logic
outputs will swing between OGND and OVDD.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF and
CLKOUT. The data access and bus relinquish times are too
slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is
intended for use during long periods of inactivity.
Format
The LTC1745 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
Output Enable
GROUNDING AND BYPASSING
The LTC1745 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the
LTC1745 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
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High quality ceramic bypass capacitors should be used at
the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as
shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7µF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1745 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1745 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypass capacitors should
bypass to the digital system ground. The digital processing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1745 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
1745f
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LTC1745
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PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.4 – 12.6*
(.488 – .496)
0.95 ±0.10
8.1 ±0.10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
6.2 ±0.10
7.9 – 8.3
(.311 – .327)
0.32 ±0.05
0.50 TYP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.0473)
MAX
6.0 – 6.2**
(.236 – .244)
0° – 8°
-T.10 C
-C0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
0.50
(.0197)
BSC
0.17 – 0.27
(.0067 – .0106)
0.05 – 0.15
(.002 – .006)
FW48 TSSOP 0502
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1745f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1745
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference
0.05% Max Initial Accuracy, 5ppm/°C Max Drift
LTC1196
8-Bit, 1Msps Serial ADC
3V to 5V, SO-8
LTC1405
12-Bit, 5Msps, Sampling ADC
5V or ±5V Pin Compatible with the LTC1420
LTC1406
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Undersampling Capability Up to 70MHz Input
LTC1410
12-Bit, 1.25Msps ADC
±5V, 71dB SINAD
LTC1411
14-Bit, 2.5Msps ADC
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LTC1412
12-Bit, 3Msps, Sampling ADC
±5V, No Pipeline Delay, 72dB SINAD
LTC1414
14-Bit, 2.2Msps ADC
±5V, 81dB SINAD and 95dB SFDR
LTC1415
Single 5V, 12-Bit, 1.25Msps
55mW Power Dissipation, 72dB SINAD
LTC1419
14-Bit, 800ksps ADC
±5V, 95dB SFDR
LTC1420
12-Bit, 10Msps ADC
71dB SINAD and 83dB SFDR at Nyquist
LT1460
Micropower Precision Series Reference
0.075% Accuracy, 10ppm/°C Drift
LTC1604/LTC1608
16-Bit, 333ksps/500ksps ADCs
16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
LTC1668
16-Bit, 50Msps DAC
87dB SFDR at 1MHz fOUT, Low Power, Low Cost
LTC1740
14-Bit, 6Msps ADC
Low Power, 79dB SINAD, 91dB SFDR
LTC1741
12-Bit, 65Msps ADC
Pin Compatible with the LTC1745
LTC1742
14-Bit, 65Msps ADC
Pin Compatible with the LTC1745
LTC1743
12-Bit, 50Msps ADC
Pin Compatible with the LTC1745
LTC1744
14-Bit, 50Msps ADC
Pin Compatible with the LTC1745
LTC1746
14-Bit, 25Msps ADC
Pin Compatible with the LTC1745
LTC1747
12-Bit, 80Msps ADC
Pin Compatible with the LTC1745
LTC1748
14-Bit, 80Msps ADC
Pin Compatible with the LTC1745
1745f
20
Linear Technology Corporation
LT/TP 0903 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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