LTC1775
High Power
No RSENSE Current Mode
Synchronous Step-Down
Switching Regulator
TM
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DESCRIPTIO
FEATURES
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The LTC®1775 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using few external components. Current mode
control with MOSFET VDS sensing eliminates the need for
a sense resistor and improves efficiency. Largely similar
to the LTC1625, the LTC1775 has twice the maximum
sense voltage for high current applications. The frequency
of a nominal 150kHz internal oscillator can be synchronized to an external clock over a 1.5:1 frequency range.
Highest Efficiency Current Mode Controller
No Sense Resistor Required
300mV Maximum Current Sense Voltage
Stable High Current Operation
Dual N-Channel MOSFET Synchronous Drive
Wide VIN Range: 4V to 36V
Wide VOUT Range: 1.19V to VIN
±1% 1.19V Reference
Programmable Fixed Frequency with Injection Lock
Very Low Drop Out Operation: 99% Duty Cycle
Forced Continuous Mode Control Pin
Optional Programmable Soft Start
Pin Selectable Output Voltage
Foldback Current Limit
Output Overvoltage Protection
Logic Controlled Micropower Shutdown: IQ < 30µA
Available in 16-Lead Narrow SSOP and SO Packages
Burst ModeTM operation at low load currents reduces
switching losses and low dropout operation extends operating time in battery-powered systems. A forced continuous mode control pin can assist secondary winding
regulation by disabling Burst Mode operation when the
main output is lightly loaded.
Fault protection is provided by foldback current limiting
and an output overvoltage comparator. An external capacitor attached to the RUN/SS pin provides soft start
capability for supply sequencing. A wide supply range
allows operation from 4V (4.3V for LTC1775I) to 36V at the
input and 1.19V to VIN at the output.
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APPLICATIO S
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Notebook Computers
Automotive Electronics
Battery Chargers
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE and Burst Mode are trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Efficiency vs Load Current
SYNC
CSS 0.1µF
+
TK
RUN/SS
TG
VPROG
SW
M1
SUD50N03-10
ITH
SGND
DB
CMDSH-3
INTVCC
BG
VOSENSE PGND
L1
6µH
CB 0.33µF
BOOST
RC
10k
CC
2.2nF
VIN
+
CVCC
4.7µF
D1
MBRS340
CIN
22µF
30V
×4
+
M2
SUD50N03-10
VOUT
3.3V
COUT 10A
680µF
6.3V
95
VIN = 10V
f = 150kHz
FCB = INTVCC
90
VOUT = 5V
VOUT = 3.3V
85
80
75
1775 F01
Figure 1. High Efficiency Step-Down Converter
100
VIN
5V TO
28V
EFFICIENCY (%)
LTC1775
70
0.01
0.1
1
LOAD CURRENT (A)
10
1775 F01b
1
LTC1775
W W
W
AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VIN, TK) ................. 36V to – 0.3V
Boosted Supply Voltage (BOOST) ............. 42V to – 0.3V
Boosted Driver Voltage (BOOST – SW) ...... 7V to – 0.3V
Switch Voltage (SW) ....................................36V to – 5V
EXTVCC Voltage ...........................................7V to – 0.3V
ITH Voltage ................................................2.7V to – 0.3V
FCB, RUN/SS, SYNC Voltages .....................7V to – 0.3V
VOSENSE, VPROG Voltages ........(INTVCC + 0.3V) to – 0.3V
Peak Driver Output Current < 10µs (TG, BG) ............ 2A
INTVCC Output Current ........................................ 50mA
Operating Ambient Temperature Range
LTC1775C .............................................. 0°C to 70°C
LTC1775I (Note 5) .............................. – 40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
EXTVCC 1
16 VIN
SYNC 2
15 TK
RUN/SS 3
14 SW
FCB 4
13 TG
ITH 5
12 BOOST
SGND 6
11 INTVCC
10 BG
VOSENSE 7
9
VPROG 8
GN PACKAGE
16-LEAD NARROW
PLASTIC SSOP
LTC1775CGN
LTC1775CS
LTC1775IGN
LTC1775IS
GN PART MARKING
PGND
1775
1775I
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 130°C/W (GN)
TJMAX = 125°C, θJA = 110°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
10
50
nA
1.190
3.300
5.000
1.202
3.380
5.100
V
V
V
0.001
0.01
%/V
– 0.020
0.035
– 0.2
0.2
%
%
1.16
1.19
1.22
V
–1
–2
µA
1.24
1.28
1.32
V
Main Control Loop
IINVOSENSE
Feedback Current
VPROG Pin Open, ITH = 1.19V (Note 3)
VOUT
Regulated Output Voltage
1.19V (Adjustable) Selected
3.3V Selected
5V Selected
ITH = 1.19V (Note 3)
VPROG Pin Open
VPROG = 0V
VPROG = INTVCC
VLINEREG
Reference Voltage Line Regulation
VIN = 4V to 20V, ITH = 1.19V (Note 3),
VPROG Pin Open
VLOADREG
Output Voltage Load Regulation
ITH = 2V (Note 3)
ITH = 0.5V (Note 3)
●
●
VFCB
Forced Continuous Threshold
VFCB Ramping Negative
●
IFCB
Forced Continuous Bias Current
VFCB = 1.19V
VOVL
Output Overvoltage Lockout
VPROG Pin Open
IPROG
VPROG Input Current
3.3V VOUT
5V VOUT
VPROG = 0V
VPROG = 5V
– 3.5
3.5
–7
7
µA
µA
Input DC Supply Current
Normal Mode
Shutdown
EXTVCC = 5V (Note 4)
VRUN/SS = 0V, 4V < VIN < 15V
500
15
30
µA
µA
0.8
1.4
2
V
VRUN/SS = 0V
–1.2
–2.5
–4
µA
VOSENSE = 1V, VPROG Pin Open
260
300
340
mV
IQ
VRUN/SS
RUN/SS Pin Threshold
IRUN/SS
Soft Start Current Source
∆VSENSE(MAX) Maximum Current Sense Threshold
2
●
●
●
●
1.178
3.220
4.900
LTC1775
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
TG tR
TG tF
TG Transition Time
Rise Time
Fall Time
BG tR
BG tF
BG Transition Time
Rise Time
Fall Time
MIN
TYP
MAX
UNITS
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
50
50
150
150
ns
ns
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
50
50
150
150
ns
ns
5.2
5.4
V
– 0.2
–1
%
180
300
mV
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 30V, VEXTVCC = 4V
VLDOINT
INTVCC Load Regulation
ICC = 20mA, VEXTVCC = 4V
VLDOEXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 5V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 20mA, VEXTVCC Ramping Positive
fOSC
Oscillator Freqency
SYNC = 0V
fH/fOSC
Maximum Synchronized Frequency Ratio
VSYNC
SYNC Pin Threshold (Figure 4)
RSYNC
SYNC Pin Input Resistance
●
●
5.0
4.5
4.7
135
150
V
Oscillator
165
kHz
1.2
V
1.5
Ramping Positive
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC1775CGN/LTC1775IGN: TJ = TA + (PD • 130°C/W)
LTC1775CS/LTC1775IS: TJ = TA + (PD • 110°C/W)
Note 3: The LTC1775 is tested in a feedback loop that adjusts VOSENSE to
achieve a specified error amplifier output voltage (ITH).
0.9
50
kΩ
Note 4: Typical in application circuit with EXTVCC tied to VOUT = 5V,
IOUT = 0A and FCB = INTVCC. Dynamic supply current is higher due
to the gate charge being delivered at the switching frequency. See
Applications Information.
Note 5: Minimum input supply voltage is 4.3V at – 40°C for industrial
grade parts.
Note 6: Rise and fall times are measured at 10% to 90% levels.
3
LTC1775
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Input Voltage
100
100
ILOAD = 5A
95
90
95
ILOAD = 5A
70
CONTINUOUS
MODE
60
ILOAD = 500mA
85
80
VIN = 10V
VOUT = 5V
EXTVCC = VOUT
50
0.001
75
90
ILOAD = 500mA
85
80
75
VOUT = 5V
FIGURE 1 CIRCUIT
70
0.1
0.01
1.0
LOAD CURRENT (A)
EFFICIENCY (%)
80
BURST
MODE
90
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Input Voltage
100
10
0
10
15
20
INPUT VOLTAGE (V)
5
25
VOUT = 3.3V
FIGURE 1 CIRCUIT
70
30
0
10
15
20
INPUT VOLTAGE (V)
5
25
1775 • G02
1775 • G01
Load Regulation
1775 • G03
VIN – VOUT Dropout Voltage
vs Load Current
ITH Pin Voltage vs Load Current
3.0
0
400
FIGURE 1 CIRCUIT
VIN = 20V
VOUT = 5V
FIGURE 1 CIRCUIT
2.5
– 0.1
30
FIGURE 1 CIRCUIT
VOUT = 5V, 5% DROP
300
VITH (V)
∆VOUT (%)
– 0.2
– 0.3
VIN – VOUT (mV)
2.0
1.5
CONTINUOUS
MODE
1.0
100
– 0.4
BURST
MODE
0.5
– 0.5
0
2
0
6
4
LOAD CURRENT (A)
8
10
0
8
6
10
4
LOAD CURRENT (A)
2
12
Input and Shutdown Current
vs Input Voltage
400
20
EXTVCC = 5V
400
EXTVCC – INTVCC (mV)
30
0
– 0.5
5
20
15
25
10
INPUT VOLTAGE (V)
30
0
35
1775 • G07
300
200
100
10
0
10
VIN = 15V
EXTVCC = 5V
0.5
∆INTVCC (%)
600
SHUTDOWN CURRENT (µA)
40
SHUTDOWN
200
8
500
50
800
4
6
CURRENT LOAD (A)
EXTVCC Switch Drop
vs INTVCC Load Current
VIN = 15V
EXTVCC OPEN
2
1775 • G06
1.0
60
1000
INPUT CURRENT (µA)
0
INTVCC Load Regulation
1200
4
0
14
1775 • G05
1775 • G04
0
200
–1.0
0
20
10
30
40
INTVCC LOAD CURRENT (mA)
50
1775 • G08
0
0
10
30
40
20
INTVCC LOAD CURRENT (mA)
50
1775 • G09
LTC1775
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense Voltage
vs Temperature
300
250
200
150
100
50
0
0
0.2
0.4
0.6
DUTY CYCLE
0.8
320
300
250
300
200
SYNC = 0V
150
100
290
50
60
35
85
10
TEMPERATURE (°C)
110
135
0
–40 –15
60
35
85
10
TEMPERATURE (°C)
1775 • G11
1775 • G10
0
110
135
1775 • G12
RUN/SS Pin Current vs
Temperature
FCB Pin Current vs Temperature
Soft Start
0
RUN/SS CURRENT (µA)
– 0.5
FCB CURRENT (µA)
SYNC = 1.5V
310
280
–40 –15
1.0
Oscillator Frequency
vs Temperature
FREQUENCY (kHz)
350
MAXIMUM CURRENT SENSE VOLTAGE (mV)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Maximum Current Sense Voltage
vs Duty Cycle
– 1.0
– 1.5
–1
RUN/SS
5V/DIV
–2
VOUT
5V/DIV
–3
IL
5A/DIV
–4
– 2.0
–40 –15
60
35
85
10
TEMPERATURE (°C)
110
135
–5
–40 –15
60
35
85
10
TEMPERATURE (°C)
1775 • G13
110
VIN = 20V
20ms/DIV
VOUT = 5V
RLOAD = 0.5Ω
FIGURE 1 CIRCUIT
135
1775 • G14
Transient Response
(Burst Mode Operation)
Transient Response
VOUT
100mV
/DIV
1530 G16
Burst Mode Operation
VOUT
50mV
/DIV
VOUT
100mV
/DIV
ITH
100mV
/DIV
IL
5A/DIV
IL
5A/DIV
100µs/DIV
VIN = 20V
VOUT = 5V
ILOAD = 2A TO 8A
FIGURE 1 CIRCUIT
1530 G18
IL
2A/DIV
VIN = 20V
200µs/DIV
VOUT = 5V
ILOAD = 100mA TO 2A
FIGURE 1 CIRCUIT
1530 G17
VIN = 20V
20µs/DIV
VOUT = 5V
ILOAD = 100mA
FIGURE 1 CIRCUIT
1530 G15
5
LTC1775
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PI FU CTIO S
EXTVCC (Pin 1): INTVCC Switch Input. When the EXTVCC
voltage is above 4.7V, the switch closes and supplies
INTVCC power from EXTVCC. Do not exceed 7V at this pin.
Leaving VPROG open allows the output voltage to be set by
an external resistive divider between the output and
VOSENSE.
SYNC (Pin 2): Synchronization Input for Internal Oscillator. The oscillator will nominally run at 150kHz when open,
225kHz when tied above 1.2V, and will lock over a 1.5:1
clock frequency range.
PGND (Pin 9): Driver Power Ground. Connects to the
source of the bottom N-channel MOSFET, the (–) terminal
of CVCC and the (–) terminal of CIN.
RUN/SS (Pin 3): Run Control and Soft Start Input. A
capacitor to ground at this pin sets the ramp time to full
current output (approximately 1s/µF). Forcing this pin
below 1.4V shuts down the device.
FCB (Pin 4): Forced Continuous Input. Tie this pin to
ground to force synchronous operation at low load
currents, to a resistive divider from the secondary output
when using a secondary winding, or to INTVCC to enable
Burst Mode operation at low load currents.
ITH (Pin 5): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage, forcing inductor current to be roughly proportional to VITH. Nominal voltage range for this pin is 0V to
2.4V.
SGND (Pin 6): Signal Ground. Connect to the (–) terminal
of COUT.
VOSENSE (Pin 7): Output Voltage Sense. Feedback input
from the remotely sensed output voltage or from an
external resistive divider across the output.
VPROG (Pin 8): Output Voltage Programming. When
VOSENSE is connected to the output, VPROG < 0.8V selects
a 3.3V output and VPROG > 3.5V selects a 5V output.
6
BG (Pin 10): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
INTVCC (Pin 11): Internal 5.2V Regulator Output. The
driver and control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7µF tantalum or other low ESR capacitor.
BOOST (Pin 12): Topside Floating Driver Supply. The (+)
terminal of the bootstrap capacitor connects here. This pin
swings from a Schottky diode drop below INTVCC to VIN +
INTVCC.
TG (Pin 13): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage.
SW (Pin 14): Switch Node. The (–) terminal of the bootstrap capacitor connects here. This pin swings from a
diode drop below ground up to VIN.
TK (Pin 15): Top MOSFET Kelvin Sense. MOSFET VDS
sensing requires this pin to be routed to the drain of the top
MOSFET separately from VIN.
VIN (Pin 16): Main Supply Input. Decouple this pin to
ground with an RC filter (1Ω, 0.1µF) for applications
above 3A.
LTC1775
W
FU CTIO AL DIAGRA
U
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TK
+
2 SYNC
VIN
15
TA
× 5.5
INTVCC
+
–
INTVCC
CIN
–
BA
× 5.5
0.95V
+
ITH
+–
5
OSC
0.7V
RC
–
1.19V
–
+
gm = 1m
BOOST
+
–
CL
–
TOP
R
0.5V
VFB
12
B
SLEEP
CB
TG
SWITCH
LOGIC/
DROPOUT
COUNTER
Ω
EA
14
INTVCC
11
OVERVOLTAGE
+–
0.6V
–
DB
+
CVCC
BG
FCNT
10
3µA
M2
PGND
+
3
M1
13
SW
SHUTDOWN
VIN
CSS
I1
–
+
RUN/SS
S
Q
ITHB
0.6V
I2
+
CC1
+
REV
9
6V
1.28V
1.19V
REF
–
+
VIN
16
OV
1.19V
5.2V
LDO REG
+
SGND
+
F
6
–
INTVCC
4.7V
–
1µA
L1
8 VPROG
7 VOSENSE
4 FCB
1 EXTVCC
+
VOUT
COUT
1775 BD
7
LTC1775
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OPERATIO
Main Control Loop
The LTC1775 is a constant frequency, current mode
controller for DC/DC step-down converters. In normal
operation, the top MOSFET is turned on when the RS latch
is set by the on-chip oscillator and is turned off when the
current comparator I1 resets the latch. While the top
MOSFET is turned off, the bottom MOSFET is turned on
until either the inductor current reverses, as determined
by the current reversal comparator I2, or the next cycle
begins. Inductor current is measured by sensing the VDS
potential across the conducting MOSFET. The output of
the appropriate sense amplifier (TA or BA) is selected by
the switch logic and applied to the current comparator.
The voltage on the ITH pin sets the comparator threshold
corresponding to peak inductor current. The error amplifier EA adjusts this voltage by comparing the feedback
signal VFB from the output voltage with the internal 1.19V
reference. The VPROG pin selects whether the feedback
voltage is taken directly from the VOSENSE pin or is derived
from an on-chip resistive divider. When the load current
increases, it causes a drop in the feedback voltage relative
to the reference. The ITH voltage then rises until the
average inductor current again matches the load current.
The internal oscillator can be synchronized to an external
clock applied to the SYNC pin and can lock to a frequency
between 100% and 150% of its nominal 150kHz rate.
When the SYNC pin is left open, it is pulled low internally
and the oscillator runs at its normal rate. If this pin is taken
above 1.2V, the oscillator will run at its maximum 225kHz
rate.
Pulling the RUN/SS pin low forces the controller into its
shutdown state and turns off both MOSFETs. Releasing
the RUN/SS pin allows an internal 3µA current source to
charge up an external soft start capacitor CSS. When this
voltage reaches 1.4V, the controller begins switching, but
with the ITH voltage clamped at approximately 0.8V. As
CSS continues to charge, the clamp is raised until full range
operation is restored.
The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged
from INTVCC through a diode DB when the top MOSFET is
turned off. As VIN decreases towards VOUT, the converter
8
will attempt to turn on the top MOSFET continuously
(‘’dropout’’). A dropout counter detects this condition and
forces the top MOSFET to turn off for about 500ns every
tenth cycle to recharge the bootstrap capacitor.
An overvoltage comparator OV guards against transient
overshoots and other conditions that may overvoltage the
output. In this case, the top MOSFET is turned off and the
bottom MOSFET is turned on until the overvoltage condition is cleared.
Foldback current limiting for an output shorted to ground
is provided by a transconductance amplifer CL. As VFB
drops below 0.6V, the buffered ITH input to the current
comparator is gradually pulled down to a 0.95V clamp.
This reduces peak inductor current to about one fifth of its
maximum value.
Low Current Operation
The LTC1775 is capable of Burst Mode operation at low
load currents. If the error amplifier drives the ITH voltage
below 0.95V, the buffered ITH input to the current comparator will remain clamped at 0.95V. The inductor current
peak is then held at approximately 60mV/RDS(ON)(TOP). If
ITH then drops below 0.5V, the Burst Mode comparator B
will turn off both MOSFETs. The load current will be
supplied solely by the output capacitor until ITH rises
above the 50mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 1.19V.
This forces continuous operation and can assist secondary winding regulation.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1775 is derived from the
INTVCC pin. When the EXTVCC pin is left open, an internal
5.2V low dropout regulator supplies the INTVCC power
from VIN. If EXTVCC is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTVCC to INTVCC. This allows a high efficiency source,
such as the primary or a secondary output of the converter
itself, to provide the INTVCC power.
LTC1775
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APPLICATIO S I FOR ATIO
The LTC1775 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS,
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current ID(MAX).
The gate drive voltage is set by the 5.2V INTVCC supply.
Consequently, logic level threshold MOSFETs must be
used in LTC1775 applications. If low input voltage operation is expected (VIN < 5V), then sub-logic level threshold
MOSFETs should be used. Pay close attention to the
V(BR)DSS specification for the MOSFETs as well; many of
the logic level MOSFETs are limited to 30V or less.
The MOSFET on-resistance is chosen based on the
required load current. The maximum average output current IO(MAX) is equal to the peak inductor current less half
the peak-to-peak ripple current ∆IL. The peak inductor
current is inherently limited in a current mode controller
by the current threshold ITH range. The corresponding
maximum VDS sense voltage is about 300mV under normal conditions. The LTC1775 will not allow peak inductor
current to exceed 300mV/RDS(ON)(TOP). The following
equation is a good guide for determining the required
RDS(ON)(MAX) at 25°C (manufacturer’s specification), allowing some margin for ripple current, current limit and
variations in the LTC1775 and external component values:
RDS(ON)(MAX) ≅
240mV
IO(MAX) (ρT )
(
)
2.0
ρT NORMALIZED ON RESISTANCE
Power MOSFET Selection
The ρT is a normalized term accounting for the significant
variation in RDS(ON) with temperature, typically about
0.4%/°C as shown in Figure 2. Junction to ambient temperature TJA is around 20°C in most applications. For a
maximum ambient temperature of 70°C, using ρ90°C ≅ 1.3
in the above equation is a reasonable choice. This equation
is plotted in Figure 3 to illustrate the dependence of
maximum output current on RDS(ON). Some popular
MOSFETs are shown as data points.
1.5
1.0
0.5
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
1775 F02
Figure 2. RDS(ON) vs Temperature
25
MAXIMUM OUTPUT CURRENT (A)
The basic LTC1775 application circuit is shown in Figure 1.
External component selection is primarily determined by
the maximum load current and begins with the selection of
the sense resistance for the desired current level. Since the
LTC1775 senses current using the on-resistance of the
power MOSFET, the maximum application current primarily determines the choice of MOSFET. The operating
frequency and the inductor are chosen based largely on
the desired amount of ripple current. Finally, CIN is selected for its ability to handle the RMS current into the
converter and COUT is chosen with low enough ESR to
meet the output voltage ripple specification.
IRL3803
20
15
SUD50N03-10
10
FDS8936A
5
Si9936
0
0
0.02
0.06
0.04
RDS(ON) (Ω)
0.08
0.10
1775 F03
Figure 3. Maximum Output Current vs RDS(ON) at VGS = 4.5V
The 300mV maximum sense voltage of the LTC1775
allows a large current to be obtained from power MOSFET
switches. It also causes a significant amount of power
dissipation in those switches and careful attention must be
9
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paid to the resulting thermal issues. Under DC conditions,
the maximum power that can be dissipated by a MOSFET
switch limits the current through it:
IDS(MAX)=
P
RDS(ON)
=
TJ(MAX) – TA
θ JA RDS(ON) ρTJ(MAX)
For example, the SUD50N03-10 with TJ(MAX) = 175°C,
TA =70°, θJA = 30° C/W, RDS(ON) = 0.019Ω, ρTJ(MAX) = 1.8
can operate with a maximum DC current of 10A. In a
switching application, the actual power dissipation is
increased by the transition losses and is reduced by the
switch duty cycle. When the LTC1775 is operating in
continuous mode, the duty cycles for the MOSFETs are:
VOUT
VIN
V –V
Bottom Duty Cycle = IN OUT
VIN
Top Duty Cycle =
Operating Frequency and Synchronization
The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
The internal oscillator runs at a nominal 150kHz frequency
when the SYNC pin is left open or connected to ground.
Pulling the SYNC pin above 1.2V will increase the frequency by 50%. The oscillator will injection lock to a clock
signal applied to the SYNC pin with a frequency between
165kHz and 200kHz. The clock high level must exceed
1.2V for at least 1µs and no longer than 4µs as shown in
Figure 4. The top MOSFET turn-on will synchronize with
the rising edge of the clock.
1µs < tON < 4µs
7V
The MOSFET power dissipations at maximum output
current are:
1.2V
PTOP
V
2
= OUT (IO(MAX) )(ρT (TOP) )(RDS(ON) )
VIN
2
+ (k)(VIN )(IO(MAX) )(C RSS )(f)
1775 F04
0
5µs < t < 6µs
V –V
2
PBOT = IN OUT (IO(MAX) )(ρT (BOT ) )(RDS(ON) )
VIN
Both MOSFETs have I2R losses and the PTOP equation
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7 can be
used to estimate the amount of transition loss. The bottom
MOSFET losses are greatest at high input voltage or during
a short circuit when the duty cycle is nearly 100%. The
temperature rise of the MOSFETs depends on the effective
thermal resistance θJA of the heat sink used in the application. Check the temperature of the MOSFET when testing
applications and use appropriate heat sinking such as
board power planes to spread the heat.
10
Figure 4. SYNC Clock Waveform
Inductor Value Selection
Given the desired input and output voltages, the inductor
value and operating frequency directly determine the
ripple current:
V
V
∆IL = OUT 1 – OUT
VIN
( f)(L)
Lower ripple current reduces losses in the inductor, ESR
losses in the output capacitors and output voltage ripple.
Thus, highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this, however, requires a large inductor.
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A reasonable starting point is to choose a ripple current
that is about 40% of IO(MAX). Note that the largest ripple
current occurs at the highest VIN. To guarantee that ripple
current does not exceed a specified maximum, the inductor should be chosen according to:
VOUT
V
L≥
1 – OUT
VIN(MAX)
( f)(∆IL(MAX) )
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC1775 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
IBURST(PEAK)
60mV
=
RDS(ON)
The corresponding average current depends on the amount
of ripple current. Lower inductor values (higher ∆IL) will
reduce the load current at which Burst Mode operation
begins.
The output voltage ripple can increase during Burst Mode
operation if ∆IL is substantially less than IBURST. This will
primarily occur when the duty cycle is very close to unity
(VIN is close to VOUT) or if very large value inductors are
chosen. This is generally only a concern in applications
with VOUT ≥ 5V. At high duty cycles, a skipped cycle
causes the inductor current to quickly descend to zero.
However, it takes multiple cycles to ramp the current back
up to IBURST(PEAK). During this interval, the output capacitor must supply the load current and enough charge may
be lost to cause significant droop in the output voltage. It
is a good idea to keep ∆IL comparable to IBURST(PEAK).
Otherwise, one might need to increase the output capacitance in order to reduce the voltage ripple or else disable
Burst Mode operation by forcing continuous operation
with the FCB pin.
Fault Conditions: Current Limit and Output Shorts
The LTC1775 current comparator can accommodate a
maximum sense voltage of 300mV. This voltage and the
sense resistance determine the maximum allowed peak
inductor current. The corresponding output current limit
is:
ILIMIT =
(
300mV
1
– ∆IL
RDS(ON) ( ρT) 2
)
The current limit value should be checked to ensure that
ILIMIT(MIN) > IO(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions which cause the highest power
dissipation in the top MOSFET. Note that it is important to
check for self-consistency between the assumed junction
temperature of the top MOSFET and the resulting value of
ILIMIT which heats the junction.
Caution should be used when setting the current limit
based upon RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable, but perhaps overly conservative, assumption
is that the minimum RDS(ON) lies the same amount below
the typical value as the maximum RDS(ON) lies above it.
Consult the MOSFET manufacturer for further guidelines.
The LTC1775 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 300mV to
about 80mV. Under short-circuit conditions with very low
duty cycle, the LTC1775 will begin skipping cycles in order
to limit the short-circuit current. In this situation the
bottom MOSFET RDS(ON) will control the inductor current
valley rather than the top MOSFET controlling the inductor
current peak. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC1775
(approximately 0.5µs), the input voltage, and inductor
value:
∆IL(SC) = tON(MIN) VIN /L.
The resulting short-circuit current is:
ISC =
80mV
1
+ ∆ IL(SC)
( ρT ) 2
(RDS(ON)(BOT) )
11
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Normally, the top and bottom MOSFETs will be of the same
type. A bottom MOSFET with lower RDS(ON) than the top
may be chosen if the resulting increase in short-circuit
current is tolerable. However, the bottom MOSFET should
never be chosen to have a higher nominal RDS(ON) than the
top MOSFET.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses rapidly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
which do not increase the height significantly.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time, which could cost as much as 1% in efficiency.
A 1A Schottky diode is generally a good size for 3A to 5A
Kool Mµ is a registered trademark of Magnetics, Inc.
12
regulators. The diode may be omitted if the efficiency loss
can be tolerated.
Parasitic Lead Inductance Effects
Because the LTC1775 is designed to operate with relatively large currents through single (or multiple) MOSFET
switches, the lead inductance of these power switches can
become a significant concern. The table below shows
typical values of lead inductance for some common packages:
MOSFET Package
Lead Inductance
TO-220
4nH to 12nH
DDPAK
4nH
DPAK
1.5nH
SO-8
1nH
Of particular concern are switches in TO-220 packages
which can have a series inductance of between 4nH and
12nH depending upon the depth of insertion into the
circuit board. When the main (top) switch is turned on, the
lead inductance LP forms a voltage divider with the power
inductor L1. The voltage VLP across this parasitic adds to
the voltage from the switch on-resistance and increases
the current sense voltage.
VLP = (VIN – VOUT)LP/L1
The result is lower value of current limit than would have
been expected otherwise. For example, a 10nH lead inductance with a 5µH power inductor has 50mV across it when
VIN = 30V and VOUT = 5V. Thus, the 300mV current limit
will be reached when the switch voltage due to onresistance is only 250mV, a 17% reduction. This effect is
most noticeable at higher input voltages.
Lead inductance also reduces the benefit of the Schottky
diode D1 by delaying commutation of the inductor current
from the diode over to the synchronous (bottom) switch.
With the diode forward biased when the synchronous
switch turns on, there is only about 500mV applied across
the lead and trace inductance between the switch and the
diode. It takes about 400ns to commutate a 20A current in
this case. This delay reduces efficiency and can also
increase the foldback current limit of the LTC1775. The
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Schottky diode must be placed next to the synchronous
switch to minimize this effect. One also might consider
using a power switch with an integrated Schottky diode, or
omitting the diode altogether in high current applications.
CIN and COUT Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT / VIN. To
prevent large input voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS current is given by:
V
V
IRMS ≅ IO(MAX) OUT IN − 1
VIN VOUT
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS
= IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
placed in parallel to meet size or height requirements in the
design.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
∆VOUT is approximately bounded by:
1
∆VOUT ≤ ∆IL ESR +
(8 )(f )(COUT )
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied the capacitance is adequate for
filtering and has the required RMS current rating.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON (organic semiconductor
dielectric) capacitor available from Sanyo has the lowest
product of ESR and size of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor in
parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-driven applications providing
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include Nichicon
PL, NEC Neocap, Panasonic SP and Sprague 595D series.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5.2V supply which powers the drivers and internal circuitry within the LTC1775. The INTVCC pin can supply a
maximum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum or low ESR
electrolytic capacitance. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the LTC1775
to exceed its maximum junction temperature rating. Most
of the supply current drives the MOSFET gates unless an
external EXTVCC source is used. The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1775CGN
is limited to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in continuous mode at high VIN. Relief can be
provided by using the EXTVCC pin to provide the gate drive
current.
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VPUMP ≈ 2(VOUT – VD) < 7V
EXTVCC Connection
+
The LTC1775 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up, short circuit) power is supplied from the internal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC ≤ VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current supplying
the driver and control currents will be scaled by a factor of
Duty Cycle/Efficiency. For 5V regulators this simply means
connecting the EXTVCC pin directly to VOUT. However, for
3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5.2V regulator resulting
in a low current efficiency penalty of up to 10% at high
input voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
1µF
VIN
+
CIN
VIN
BAT85
BAT85
0.22µF
TK
TG
LTC1775
BAT85
VN2222LL
SW
L1
EXTVCC
VOUT
+
COUT
BG
PGND
1775 F05b
Figure 5b: Capacitive Charge Pump for EXTVCC
3. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage which has been boosted to
greater than 4.7V. This can be done with either an
inductive boost winding as shown in Figure 5a or a
capacitive charge pump as shown in Figure 5b.
4. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range (EXTVCC < VIN),
it may be used to power EXTVCC.
Figure 6 shows how one can easily generate a suitable
EXTVCC voltage from VIN. This circuit still derives the gate
drive current from VIN, but it removes the power dissipation from the LTC1775 internal regulator and increases the
gate drive voltage.
VIN
VIN
+
CIN
VIN
TK
OPTIONAL
EXTVCC
CONNECTION
5V < VSEC < 7V
TG
LTC1775
SW
EXTVCC
R4
1N4148
•
+
T1
1:N
FCB
R3
VSEC
• +
CSEC
1µF
VOUT
EXTVCC
1775 F06
Figure 6. EXTVCC Power Supplied from VIN
COUT
PGND
1775 F05a
Figure 5a: Secondary Output Loop and EXTVCC Connection
14
Q1
D1
6.8V
BG
SGND
R1
Note that RDS(ON) also varies with the gate drive level. If
gate drives other than the 5.2V INTVCC are used, this must
be accounted for when selecting the MOSFET RDS(ON).
Particular care should be taken with applications where
EXTVCC is connected to the output. When the output
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voltage is between 4.7V and 5.2V, INTVCC will be connected to the output and the gate drive is reduced. The
resulting increase in RDS(ON) will also lower the current
limit. Even applications with VOUT > 5.2V will traverse this
region during start-up and must take into account the
reduced current limit.
An external bootstrap capacitor (CB in the functional diagram) connected to the BOOST pin supplies the gate drive
voltage for the topside MOSFET. This capacitor is charged
through diode DB from INTVCC when the SW node is low.
Note that the voltage across CB is about a diode drop below
INTVCC. When the top MOSFET turns on, the switch node
voltage rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. During dropout operation, CB supplies the top driver for as long as ten cycles between refreshes. Thus, the boost capacitance needs to store about
100 times the gate charge required by the top MOSFET. In
many applications 0.1µF to 0.47µF is adequate.
When adjusting the gate drive level , the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
The LTC1775 drivers are adequate for driving up to about
30nC into MOSFET switches. When using large single, or
multiple, MOSFET switches, external buffers may be required to provide additional gate drive capability. Special
purpose gate driver circuits such as the LTC1693 are ideal
in such cases. Alternately, the external buffer circuit shown
in Figure 7 can be used. Note that the bipolar devices
INTVCC
BOOST
Q1
FMMT619
VOUT
0V
3.3V
INTVCC
5V
Open
Adjustable
Remote sensing of the output voltage is provided by the
VOSENSE pin. For fixed 3.3V and 5V output applications an
internal resistive divider is used and the VOSENSE pin is
connected directly to the output voltage as shown in
Figure 8a. When using an external resistive divider, the
VPROG pin is left open and the VOSENSE pin is connected to
feedback resistors as shown in Figure 8b. The output
voltage is set by the divider as:
R2
VOUT = 1.19 V 1 +
R1
VOUT
COUT
SGND
1775 F08a
Figure 8a. Fixed 3.3V or 5V VOUT
LTC1775
OPEN
Q4
FMMT720
PGND
VOSENSE
+
VOUT
GATE
OF M2
BG
LTC1775
VPROG INTVCC
CONNECT FOR
VOUT = 3.3V
Q3
FMMT619
GATE
OF M1
SW
VPROG
CONNECT FOR
VOUT = 5V
External Gate Drive Buffer
Q2
FMMT720
Output Voltage Programming
The LTC1775 has a pin selectable output voltage determined by the VPROG pin as follows:
Topside MOSFET Driver Supply (CB, DB)
TG
reduce the signal swing at the gate by a diode drop. Thus,
the LTC1775 requires an increased EXTVCC voltage of
about 6V (such as provided by the Figure 6 circuit) when
using this driver.
VPROG
R2
+
COUT
VOSENSE
R1
SGND
1775 F07
1775 F08b
Figure 7. Optional External Gate Driver
Figure 8b. Adjustable VOUT
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Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides a soft
start function and a means to shut down the LTC1775. Soft
start reduces surge currents from VIN by gradually increasing the controller’s current limit ITH(MAX). This pin
can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.4V puts the LTC1775 into
a low quiescent current shutdown (IQ < 30µA). This pin can
be driven directly from logic as shown in Figure 9. Releasing the RUN/SS pin allows an internal 3µA current source
to charge up the soft-start capacitor CSS. If RUN/SS has
been pulled all the way to ground there is a delay before
starting of approximately:
When the voltage on RUN/SS reaches 1.4V the LTC1775
begins operating with a clamp on ITH at 0.8V. As the
voltage on RUN/SS increases to approximately 3.1V, the
clamp on ITH is raised until its full 2.4V range is restored.
This takes an additional 0.5s/µF. During this time the load
current will be folded back to approximately 80mV/RDS(ON)
until the output reaches half of its final value.
Diode D1 in Figure 9 reduces the start delay while allowing
CSS to charge up slowly for the soft start function. This
diode and CSS can be deleted if soft start is not needed. The
RUN/SS pin has an internal 6V zener clamp (See Functional Diagram).
RUN/SS
RUN/SS
D1
CSS
CSS
1775 F09
Figure 9. RUN/SS Pin Interfacing
FCB Pin Operation
When the FCB pin drops below its 1.19V threshold,
continuous synchronous operation is forced. In this case,
the top and bottom MOSFETs continue to be driven
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal under light
loads is allowed in the inductor.
16
The secondary output voltage VSEC is normally set as
shown in Figure 5a by the turns ratio N of the transformer:
VSEC ≅ (N + 1)VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light main load current, then
VSEC will droop. An external resistor divider from VSEC to
the FCB pin sets a minimum voltage VSEC(MIN):
R4
VSEC(MIN) ≅ 1.19 V 1 +
R3
1.4V
tDELAY =
CSS = (0.5s / µF ) CSS
3µA
3.3V
OR 5V
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to regulate a
flyback winding output. It can force continuous synchronous operation when needed by the flyback winding,
regardless of the main output load.
If VSEC drops below this level, the FCB voltage forces
continuous operation until VSEC is again above its
minimum.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1775 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
tON(MIN) <
VOUT
( VIN)( f)
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1775 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
The minimum on-time for the LTC1775 is generally about
0.5µs. However, as the peak sense voltage (IL(PEAK) •
RDS(ON)) decreases, the minimum on-time gradually
increases up to about 0.7µs. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of
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cycle skipping can occur with correspondingly larger
current and voltage ripple.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (×100%). Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
losses ranging from 2% to 8% as the output current
increases from 0.5A to 2A for a 5V output. I2R losses
cause the efficiency to drop at high output currents.
3. Transition losses apply only to the topside MOSFET,
and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from:
Transition Loss = (1.7)(VIN2)(IO(MAX))(CRSS)(f)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze individual
losses to determine what is limiting the efficiency and
which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1775 circuits:
4. LTC1775 VIN supply current. The VIN current is the DC
supply current to the controller excluding MOSFET gate
drive current. Total supply current is typically about
850µA. If EXTVCC is connected to 5V, the LTC1775 will
draw only 330µA from VIN and the remaining 520µA will
come from EXTVCC. VIN current results in a small
(< 1%) loss which increases with VIN.
1. INTVCC current. This is the sum of the MOSFET driver
and control currents. The driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched on and then off,
a packet of gate charge Qg moves from INTVCC to
ground. The resulting current out of INTVCC is typically
much larger than the control circuit current. In continuous mode, IGATECHG = f(Qg(TOP) + Qg(BOT)).
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead time and
inductor core losses, generally account for less than 2%
total additional loss.
By powering EXTVCC from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by a factor of Duty Cycle/
Efficiency. For example, in a 20V to 5V application at
400mA load, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the loss
from 10% (if the driver was powered directly from VIN)
to about 3%.
2. DC I2R Losses. Since there is no separate sense resistor, DC I2R losses arise only from the resistances of the
MOSFETs and inductor. In continuous mode the average output current flows through L, but is “chopped”
between the top MOSFET and the bottom MOSFET. If
the two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistance of L to obtain the DC I2R
loss. For example, if each RDS(ON) = 0.05Ω and RL =
0.15Ω, then the total resistance is 0.2Ω. This results in
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT, and COUT begins to charge or discharge. The regulator loop acts on the resulting feedback
error signal to return VOUT to its steady-state value. During
this recovery time VOUT can be monitored for overshoot or
ringing which would indicate a stability problem. The ITH
pin external components shown in Figure 1 will provide
adequate compensation for most applications.
A second, more severe transient is caused by connecting
loads with large (> 1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive in order
to limit the inrush current to the load.
17
LTC1775
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APPLICATIO S I FOR ATIO
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse and double
battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1775 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET V(BR)DSS.
Design Example
As a design example, take a supply with the following
specifications: VIN = 6V to 22V (15V nominal), VOUT = 5V,
IO(MAX) = 10A. The required RDS(ON) can immediately be
estimated:
RDS(ON) =
240mV
= 0.018Ω
(10 A)(1.3)
A 0.019Ω Siliconix SUD50N03-10 MOSFET (θJA =
30°C/W) is close to this value.
For 40% ripple current at maximum VIN the inductor
should be:
L≥
5V
5V
1–
= 6.4µH
(150kHz)(0.4)(10 A) 22V
Choosing a Magnetics 55380-A2 core with 8 turns of 15
gauge wire yields a 6µH inductor. The resulting maximum
ripple current will be:
∆IL(MAX) =
5V
5V
1–
= 4.3A
(150kHz)(6µH) 22V
Next, check that the minimum value of the current limit is
acceptable. Assume a junction temperature about 20°C
above the 70°C ambient with ρ90°C = 1.3.
ILIMIT ≥
300mV
1
– 4. 3A = 10 A
(0.019 Ω)(1.3) 2
Now double-check the assumed TJ:
50A IPK
RATING
12V
PTOP =
VIN
LTC1775
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
( ) (1.3)(0.019Ω) +
2
(1.7)(22V) (10A)(170pF)(150kHz)
5V
10 A
22V
2
= 0.56W + 0.21W = 0.77mW
PGND
1775 F10
TJ = 70°C + (0.77W)(30°C/W) = 93°C
Figure 10. Automotive Application Protection
18
Since ρ(93°C) ≅ ρ(90°C), the solution is self-consistent.
LTC1775
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APPLICATIO S I FOR ATIO
A short circuit to ground will result in a folded back
current of:
ISC =
CIN is chosen for an RMS current rating of at least 5A at
temperature. COUT is chosen with an ESR of 0.013Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage and is
approximately:
80mV
1 (15V)(0.5µs)
+
= 6.2A
(0.013Ω)(1.1) 2
6µH
∆VO = (∆IL(MAX))(ESR) = (4.3A)(0.013Ω) = 56mV
with a typical value of RDS(ON) and ρ(50°C) = 1.1. The
resulting power dissipated in the bottom MOSFET is:
PBOT =
The complete circuit is shown in Figure 11.
15V – 5 V
(6 .2A)2 (1.1)(0.013Ω) = 0. 37W
15V
which is less than under full load conditions.
RF
1Ω
VOUT
1
2
3
LTC1775
EXTVCC
VIN
SYNC
TK
RUN/SS
4
CC1 CSS
FCB
2.2nF 0.1µF RC INTVCC
10k
5
ITH
CC2
220pF
6
SGND
7
8
VOSENSE
VPROG
SW
TG
BOOST
INTVCC
BG
PGND
16
+
VIN
6V TO 22V
+
CF
0.1µF
15
M1
SUD50N03-10
L1
6µH
14
13
CIN
22µF
30V
×4
VOUT
5V
10A
12
DB
CMDSH-3
11
10
9
+
CVCC
4.7µF
CB
0.33µF
D1
MBRS340
+
M2
SUD50N03-10
COUT
680µF
6.3V
1775 F11
CIN: SANYO 30SC22M
COUT: SANYO 6SP680M
L1: MAGENTICS 55380-A2, 8 TURNS, 15 GAUGE
Figure 11. 5V/10A Fixed Output from Design Example
19
LTC1775
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APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1775. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1) Connect the TK lead directly to the drain of the topside
MOSFET. Then connect the drain to the (+) plate of CIN.
This capacitor provides the AC current to the top
MOSFET.
2) The power ground pin connects directly to the source of
the bottom N-channel MOSFET. Then connect the source
to the anode of the Schottky diode (if used) and (–) plate
of CIN, which should have as short lead lengths as
possible.
3) The LTC1775 signal ground pin should connect to the
(–) plate of COUT. Connect the (–) plate of COUT to power
ground at the source of the bottom MOSFET. All smallsignal components (R2, CSS, CC, etc.) should return
directly to SGND.
4) Keep the switch node SW away from sensitive smallsignal nodes. Ideally the switch node should be placed
on the opposite side of the power MOSFETs from the
LTC1775.
5) Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC pin and the power ground pin. This
capacitor carries the MOSFET gate drive current.
6) Does the VOSENSE pin connect as close as possible to
the load? In adjustable applications, the resistive divider (R1, R2) must be connected between the load and
signal ground. Place the divider near the LTC1775 in
order to keep the high impedance VOSENSE node short.
7) For applications with multiple switching power converters connected to the same VIN, ensure that the input
filter capacitance for the LTC1775 is not shared with the
other converters. AC input current from another converter will cause substantial input voltage ripple that
may interfere with proper operation of the LTC1775. A
few inches of PC trace or wire (LTRACE ≈ 100nH)
between CIN and the VIN supply is sufficient to prevent
sharing.
LTRACE
OPTIONAL 5V EXTVCC
CONNECTION
CSS
CC1
EXT
CLK
INTVCC
RC
1
2
3
4
5
LTC1775
EXTVCC
VIN
SYNC
TK
RUN/SS
SW
FCB
TG
ITH
BOOST
SGND
INTVCC
15
M1
14
L1
13
CB
R2
R1
7
OPEN
8
VOSENSE
VPROG
BG
PGND
VIN
12
DB
6
+
16
CVCC
11
+
+
10
M2
9
D1
CIN
–
–
OUTPUT DIVIDER
REQUIRED
WITH VPROG OPEN
+
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 12. LTC1775 Layout Diagram
20
VOUT
COUT
1775 F12
+
LTC1775
U
TYPICAL APPLICATIO S
3.3V/5A Fixed Output
VIN
5V TO 28V
RF
1Ω
LTC1775
16
VIN
EXTVCC
2
15
SYNC
TK
3
14
SW
RUN/SS
CC1
2.2nF
4
CSS RC
INTVCC
0.1µF 10k
5
CC2
220pF
6
7
8
TG
FCB
BOOST
ITH
INTVCC
SGND
VOSENSE
VPROG
BG
PGND
CIN
22µF
30V
×2
+
CF
0.1µF
1
M1
Si4412DY
L1
10µH
13
VOUT
3.3V
5A
12
DB
CMDSH-3
11
CB
0.1µF
10
+
9
D1
MBRS140T3
+
M2
Si4412DY
CVCC
4.7µF
COUT
100µF
10V
0.065Ω
×4
1775 TA01
CIN: SANYO 30SC22M
COUT: AVX TPSD107M010R0065
L1: SUMIDA CDRH-125
5V/20A Fixed Output
RF
1Ω
6V
1
2
3
CSS
0.1µF
CC1
2.2nF
INTVCC
RC
10k
CC2
220pF
4
5
6
7
8
LTC1775
EXTVCC
VIN
SYNC
TK
RUN/SS
FCB
ITH
SGND
VOSENSE
VPROG
SW
TG
BOOST
INTVCC
BG
PGND
CF
0.1µF
16
+
15
M1
IRL3803
14
Q2
FMMT720
13
Q1
FMMT619
12
11
+
10
CVCC
4.7µF
9
L1
3.7µH
CB
0.47µF
DB
CMDSH-3
Q3
FMMT619
Q4
FMMT720
VIN
6V TO 28V
CIN
22µF
30V
×8
VOUT
5V
20A
D1
MBRD835L
+
M2
IRL3803
COUT
680µF
6.3V
×2
1775 TA02
CIN: SANYO 30SC22M
COUT: SANYO 6SP680M
L1: MAGNETICS 55206-A2, 3.7µH, 6 TURNS, 13 GAUGE
21
LTC1775
U
TYPICAL APPLICATIO S
–5V/2.5A Positive to Negative Converter
RF
1Ω
VIN
5V TO 10V
CF
0.1µF
1
2
EXTVCC
VIN
SYNC
TK
16
M1
Si4412DY
15
3
CC1
2.2nF
CSS
RC
10k 0.1µF
CC2
220pF
14
SW
RUN/SS
LTC1775
4
13
TG
FCB
5
12
BOOST
ITH
6
7
8
INTVCC
SGND
VOSENSE
VPROG
BG
DB
CMDSH-3
D1
MBR140T3
10
+
COUT
680µF
6.3V
M2
Si4412DY
+
PGND
CIN
220µF
16V
L1
12µH
CB
0.22µF
11
+
CVCC
4.7µF
VOUT
–5V
2.5A
9
1775 TA04
CIN: SANYO 16SV220M
COUT: SANYO 6SP680M
L1: 12µH, 5A
12V Output, Single Inductor, Buck/Boost Converter
RF
1Ω
1
CSS
0.1µF
2
EXTVCC
VIN
15
SYNC
TK
14
RUN/SS
SW
LTC1775
13
RC OPEN 4 FCB
TG
20k
12
5
ITH
BOOST
CC2
220pF
6
11
SGND
INTVCC
M1
Si4410DY
L1
13µH
3
CC1
2.2nF
7
R1
11k
8
R2
100k
VOSENSE
VPROG
BG
PGND
DB
CMDSH-3
10
9
CIN: UNITED CHEMICON THCR70E1H226ZT-CBU
COUT: SANYO 165A-150M
L1: 13µH/11A
22
VIN
6V TO 18V
CF
0.1µF
16
CVCC
CB 4.7µF
0.33µF
+
D2
MBRD835L
M3
Si4410DY
+
M2
Si4410DY
D1
MBRS340
CIN
22µF
50V
×2
VOUT
12V
+
COUT
150µF
16V
×2
VIN
6.0
12
18
IOUT
2.6
4.0
4.8
1775 TA05
LTC1775
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
2 3
4
5 6
7
0.053 – 0.068
(1.351 – 1.727)
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
8
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
7
0.050
(1.270)
BSC
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1775
U
TYPICAL APPLICATIO S
2.5V/5A Adjustable Output
RF
1Ω
LTC1775
16
VIN
EXTVCC
15
2
SYNC
TK
14
3
SW
RUN/SS
CC2
220pF
4
5
6
7
OPEN
8
TG
FCB
ITH
SGND
BOOST
INTVCC
VOSENSE
VPROG
BG
PGND
M1
1/2 FDS8936A
L1
6.1µH
13
12
D1
MBRS140
R2
11k
1%
M2
1/2 FDS8936A
R1
10k
1%
DB
CB
CMDSH-3 0.22µF
11
10
9
CIN
15µF
35V
×3
+
CF
0.1µF
1
CC1
2.2nF CSS RC INTVCC
0.1µF 10k
VIN
5V TO 25V
+
CVCC
4.7µF
VOUT
2.5V
5A
+
COUT
680µF
4V
×2
1775 TA03
CIN: KEMET T495X156M035AS
COUT: KEMET T510X687K004AS
L1: SUMIDA CDRH127-6R1
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PolyPhase is a trademark of Linear Technology Corporation.
24
Linear Technology Corporation
1775f LT/TP 0500 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1999
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