LTC1853CFW#PBF

LTC1852/LTC1853 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs FEATURES DESCRIPTION n The 10-bit LTC®1852 and 12-bit LTC1853 are complete 8-channel data acquisition systems. They include a flexible 8-channel multiplexer, a 400ksps successive approximation analog-to-digital converter, an internal reference and a parallel output interface. The multiplexer can be configured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation. The ADCs have a scan mode that will repeatedly cycle through all 8 multiplexer channels and can also be programmed to sequence through up to 16 addresses and configurations. The sequence can also be read back from internal memory. n n n n n n n Flexible 8-Channel Multiplexer Single-Ended or Differential Inputs Two Gain Ranges Unipolar or Bipolar Operation Scan Mode and Programmable Sequencer Eliminate Configuration Software Overhead Low Power: 3mW at 250ksps 2.7V to 5.5V Supply Range Internal or External Reference Operation Parallel Output Includes MUX Address Nap and Sleep Shutdown Modes Pin Compatible up-grade 1.25Msps 10-Bit LTC1850 and 12-Bit LTC1851 APPLICATIONS n n n n n n High Speed Data Acquisition Test and Measurement Imaging Systems Telecommunications Industrial Process Control Spectrum Analysis The reference and buffer amplifier provide pin strappable ranges of 4.096V, 2.5V and 2.048V. The parallel output includes the 10-bit or 12-bit conversion result plus the 4-bit multiplexer address. The digital outputs are powered from a separate supply allowing for easy interface to 3V digital logic. Typical power consumption is 10mW at 400ksps from a single 5V supply and 3mW at 250ksps from a single 3V supply. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. BLOCK DIAGRAM CH1 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER CH2 CH3 CH4 8-CHANNEL MULTIPLEXER INTERNAL CLOCK CH5 M1 SHDN CS CONVST RD WR DIFF A2 A1 A0 UNI/BIP PGA M0 OVDD CH6 CH7 COM REFOUT REFIN REFCOMP 2.5V REFERENCE REF AMP + – 12-BIT SAMPLING ADC DATA LATCHES OUTPUT DRIVERS BUSY DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D11/S2 D10/S1 D9/S0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Integral Linearity 1.0 0.5 INL ERROR (LSBs) LTC1853 CH0 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1852 F01 OGND 18523 BD 18523fa 1 LTC1852/LTC1853 ABSOLUTE MAXIMUM RATINGS OVDD = VDD (Note 1, 2) Supply Voltage (VDD) ..................................................6V Analog Input Voltage (Note 3) ..... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................... –0.3V to 10V Digital Output Voltage ..................–0.3V to (VDD + 0.3V) Power Dissipation ...............................................500mW Ambient Operating Temperature Range LTC1852C/LTC1853C .............................. 0°C to 70°C LTC1852I/LTC1853I............................. –40°C to 85°C Storage Temperature Range...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ................. 300°C PIN CONFIGURATION LTC1852 LTC1853 TOP VIEW TOP VIEW CH0 1 48 M1 CH0 1 48 M1 CH1 2 47 SHDN CH1 2 47 SHDN CH2 3 46 CS CH2 3 46 CS CH3 4 45 CONVST CH3 4 45 CONVST CH4 5 44 RD CH4 5 44 RD CH5 6 43 WR CH5 6 43 WR CH6 7 42 DIFF CH6 7 42 DIFF CH7 8 41 A2 CH7 8 41 A2 COM 9 40 A1 COM 9 40 A1 REFOUT 10 39 A0 REFOUT 10 39 A0 REFIN 11 REFCOMP 12 38 UNI/BIP REFIN 11 REFCOMP 12 37 PGA 38 UNI/BIP 37 PGA GND 13 36 M0 GND 13 36 M0 VDD 14 35 OVDD VDD 14 35 OVDD VDD 15 34 OGND VDD 15 34 OGND GND 16 33 BUSY GND 16 33 BUSY DIFFOUT/S6 17 32 NC DIFFOUT/S6 17 32 D0 A2OUT/S5 18 31 NC A2OUT/S5 18 31 D1 A1OUT/S4 19 30 D0 A1OUT/S4 19 30 D2 A0OUT/S3 20 29 D1 A0OUT/S3 20 29 D3 D9/S2 21 28 D2 D11/S2 21 28 D4 D8/S1 22 27 D3 D10/S1 22 27 D5 D7/S0 23 26 D4 D9/S0 23 26 D6 D6 24 25 D5 D8 24 25 D7 FW PACKAGE 48-LEAD PLASTIC TSSOP FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 110°C/W TJMAX = 150°C, θJA = 110°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1852CFW#PBF LTC1852CFW#TRPBF LTC1852CFW 48-Lead Plastic TSSOP (6.1mm) 0°C to 70°C LTC1852IFW#PBF LTC1852IFW#TRPBF LTC1852IFW 48-Lead Plastic TSSOP (6.1mm) –40°C to 85°C LTC1853CFW#PBF LTC1853CFW#TRPBF LTC1853CFW 48-Lead Plastic TSSOP (6.1mm) 0°C to 70°C LTC1853IFW#PBF LTC1853IFW#TRPBF LTC1853IFW 48-Lead Plastic TSSOP (6.1mm) –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 18523fa 2 LTC1852/LTC1853 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, REFCOMP < VDD (Notes 5,6) PARAMETER CONDITIONS MIN l Resolution (No Missing Codes) Integral Linearity Error (Note 7) Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) (Note 8) REFCOMP ≥ 2V LTC1852 TYP 10 MAX UNITS Bits l ±0.25 ±1 ±0.35 ±1 LSB l ±0.25 ±1 ±0.25 ±1 LSB l l ±0.5 ±1 ±2 ±4 ±1 ±2 ±6 ±12 LSB LSB ±0.5 ±1 LSB ±2 ±4 ±4 ±8 LSB LSB ±0.5 ±1 LSB ±2 ±4 ±4 ±8 LSB LSB ±0.5 ±1 LSB With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS ≤ 400kHz Unipolar Gain Error Match Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) LTC1853 TYP MIN 12 Offset Error Match (Bipolar and Unipolar) Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) MAX With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS ≤ 400kHz Bipolar Gain Error Match Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS ≤ 250kHz l l ±1 ±2 ±3 ±6 ±1.5 ±3 ±8 ±16 LSB LSB Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS ≤ 250kHz l l ±1 ±2 ±3 ±6 ±1.5 ±3 ±8 ±16 LSB LSB Full-Scale Error Temperature Coefficient 15 15 ppm/°C ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 9) Unipolar, Gain = 1 (PGA = 1) Unipolar, Gain = 2 (PGA = 0) Bipolar, Gain = 1 (PGA = 1) Bipolar, Gain = 2 (PGA = 0) 2.7V ≤ VDD ≤ 5.5V, REFCOMP ≤ VDD MIN TYP MAX 0 – REFCOMP 0 – REFCOMP/2 ± REFCOMP/2 ±REFCOMP/4 l UNITS V V V V IIN Analog Input Leakage Current CIN Analog Input Capacitance tACQ Sample-and-Hold Acquisition Time tS(MUX) Multiplexer Settling Time (Includes tACQ) tAP Sample-and-Hold Aperture Delay Time VDD = 5V – 0.5 tjitter Sample-and-Hold Aperture Delay Time Jitter VDD = 5V 2 psRMS CMRR Analog Input Common Mode Rejection Ratio 60 dB DYNAMIC ACCURACY ±1 Between Conversions (Gain = 1) Between Conversions (Gain = 2) During Conversions 15 25 5 μA pF pF pF 50 150 ns 50 150 ns ns TA = 25°C. (Notes 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N + D) Signal-to-Noise Plus Distortion Ratio 40kHz Input Signal 72.5 dB THD Total Harmonic Distortion 40kHz Input Signal, First 5 Harmonics –80 dB SFDR Spurious Free Dynamic Range 40kHz Input Signal –85 dB 18523fa 3 LTC1852/LTC1853 INTERNAL REFERENCE TA = 25°C. (Notes 5, 6) PARAMETER CONDITIONS MIN TYP MAX UNITS REFOUT Output Voltage IOUT = 0 2.48 2.50 2.52 V REFOUT Output Temperature Coefficient IOUT = 0 ±15 ppm/°C REFOUT Line Regulation 2.7 ≤ VDD ≤ 5.5, IOUT = 0 0.01 LSB/V Reference Buffer Gain REFCOMP Output Voltage External 2.5V Reference (VDD = 5V) Internal 2.5V Reference (VDD = 5V) REFCOMP Impedance Impedance to GND, REFIN = VDD 1.6368 1.6384 1.6400 V/V 4.092 4.060 4.096 4.096 4.100 4.132 V V 19.2 kΩ DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VDD = 5.25V ● TYP MAX 2.4 UNITS V VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±5 μA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage VDD = 4.75V, IO = –10μA VDD = 4.75V, IO = – 200μA ● VDD = 4.75V, IO = 160μA VDD = 4.75V, IO = 1.6mA ● IOZ Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High 1.5 pF 4.5 V V 4 0.5 0.10 ● 0.4 V V ±10 μA COZ Hi-Z Capacitance D11 to D0 CS High (Note 9) ISOURCE Output Source Current VOUT = 0V –20 mA ISINK Output Sink Current VOUT = VDD 30 mA ● 15 pF DIGITAL INPUTS AND DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage VDD = 3.3V ● TYP MAX 1.9 UNITS V VIL Low Level Input Voltage VDD = 2.7V ● 0.45 V IIN Digital Input Current VIN = 0V to VDD ● ±5 μA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage VDD = 2.7V, IO = –10μA VDD = 2.7V, IO = – 200μA ● VDD = 2.7V, IO = 160μA VDD = 2.7V, IO = 1.6mA ● IOZ Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High 1.5 pF 2.5 V V 2 0.05 0.10 ● 0.4 V V ±10 μA COZ Hi-Z Capacitance D11 to D0 CS High (Note 9) ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 15 mA ● 15 pF 18523fa 4 LTC1852/LTC1853 POWER REQUIREMENTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Positive Supply Voltage (Note 10) ● 2.7 5.5 V OVDD Output Positive Supply Voltage (Note 10) ● 2.7 5.5 V IDD Positive Supply Current VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz ● ● 2 0.83 3 1.33 mA mA PDISS Power Dissipation VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz ● ● 10 2.25 15 4 mW mW IDDPD Power Down Positive Supply Current Nap Mode Sleep Mode SHDN = Low, CS = Low SHDN = Low, CS = High 0.5 20 mA μA Power Down Power Dissipation Nap Mode Sleep Mode VDD = VDD = OVDD = 5V, fS = 400kHz SHDN = Low, CS = Low SHDN = Low, CS = High 2.5 0.1 mW mW Power Down Power Dissipation Nap Mode Sleep Mode VDD = VDD = OVDD = 3V, fS = 250kHz SHDN = Low, CS = Low SHDN = Low, CS = High 1.5 0.06 mW mW TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX fSAMPLE(MAX) Maximum Sampling Frequency VDD = 5.5V VDD = 2.7V ● ● Acquisition + Conversion VDD = 5.5V VDD = 2.7V ● ● 2.5 4.0 μs μs tCONV Conversion Time VDD = 5.5V VDD = 2.7V ● ● 2.0 3.5 μs μs tACQ Acquisition Time (Note 13) ● 150 ns t1 CS to RD Setup Time (Notes 9, 10) ● 0 ● 10 400 250 UNITS kHz kHz ns t2 CS to CONVST Setup Time (Notes 9, 10) t3 CS to SHDN Setup Time (Notes 9, 10) 200 ns t4 SHDN to CONVST Wake-Up Time Nap Mode (Note 10) Sleep Mode (Note 10) 200 10 ns ms t5 CONVST Low Time (Notes 10, 11) t6 CONVST to BUSY Delay CL = 25pF t7 Data Ready Before BUSY t8 Delay Between Conversions t9 Wait Time RD After BUSY t10 Data Access Time After RD (Note 10) CL = 25pF CL = 100pF t11 50 RD Low Time ns 10 ● 60 35 ns ns ● 20 15 ● 50 ns ● –5 ns 35 45 ns ns 25 45 60 ns ns 10 30 35 40 ns ns ns ● ● ● ● t10 ns ns 20 ● BUS Relinquish Time 0°C to 70°C – 40°C to 85°C t12 ● ns ns 18523fa 5 LTC1852/LTC1853 TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t13 CONVST High Time (Note 10) ● 50 ns t14 Latch Setup Time (Note 10) ● 10 ns t15 Latch Hold Time (Notes 9, 10) ● 10 ns t16 WR Low Time (Note 10) ● 50 ns t17 WR High Time (Note 10) ● 50 ns t18 M1 to M0 Setup Time (Notes 9, 10) ● 10 ns t19 M0 to BUSY Delay M1 High t20 M0 to WR (or RD) Setup Time (Notes 9, 10) ● t19 ns t21 M0 High Pulse Width (Note 10) ● 50 ns t22 RD High Time Between Readback Reads (Note 10) ● 50 ns t23 Last WR (or RD) to M0 (Note 10) ● 10 ns t24 M0 to RD Setup Time (Notes 9, 10) ● t19 ns t25 M0 to CONVST (Note 10) ● t19 ns t26 Aperture Delay t27 Aperture Jitter 20 ns – 0.5 ns 2 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with OGND and GND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 400kHz, tr = tf = 2ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input on any channel with COM grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a psRMS straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 1111 1111 1111 and 0000 0000 0000. For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the LTC1852. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. Note 12: The analog input range is determined by the voltage on REFCOMP. The gain error specification is tested with an external 4.096V but is valid for any value of REFCOMP greater than 2V and less than (VDD – 0.5V.) Note 13: MUX address is updated immediately after BUSY falls. TYPICAL PERFORMANCE CHARACTERISTICS Differential Linearity 0 1.0 8192 Point FFT with fIN = 39.599kHz –20 AMPLITUDE (dB) DNL ERROR (LBS) 0.5 0 –40 –60 –80 –0.5 –100 –1.0 –120 0 4096 CODE 1852 F02 0 200 FREQUENCY (kHz) 1852 F03 18523fa 6 LTC1852/LTC1853 PIN FUNCTIONS CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the “–” analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass to analog ground plane with 1μF. REFIN (Pin 11): Reference Mode Select/Reference Buffer Input. REFIN selects the reference mode and acts as the reference buffer input. REFIN tied to ground (Logic 0) will produce 2.048V on the REFCOMP pin. REFIN tied to the positive supply (Logic 1) disables the reference buffer to allow REFCOMP to be driven externally. For voltages between 1V and 2.6V, the reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on REFIN (4.096V on REFCOMP for a 2.5V input on REFIN). REFCOMP (Pin 12): Reference Buffer Output. REFCOMP sets the full-scale input span. The reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on the REFIN pin (4.096V on REFCOMP for a 2.5V input on REFIN). REFIN tied to ground will produce 2.048V on the REFCOMP pin. REFCOMP can be driven externally if REFIN is tied to the positive supply. Bypass to analog ground plane with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. GND (Pins 13, 16): Ground. Tie to analog ground plane. VDD (Pins 14, 15): Positive Supply. Bypass to analog ground plane with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. DIFFOUT/S6 (Pin 17): Three-State Digital Data Output. Active when RD is low. Following a conversion, the single-ended/differential bit of the present conversion is available on this pin concurrent with the conversion result. In Readback mode, the single-ended/differential bit of the current sequencer location (S6) is available on this pin. The output swings between OVDD and OGND. A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): ThreeState Digital MUX Address Outputs. Active when RD is low. Following a conversion, the MUX address of the present conversion is available on these pins concurrent with the conversion result. In Readback mode, the MUX address of the current sequencer location (S5-S3) is available on these pins. The outputs swing between OVDD and OGND. D9/S2 (Pin 21, LTC1852): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D11/S2 (Pin 21, LTC1853): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 11 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D8/S1 (Pin 22, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 8 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D10/S1 (Pin 22, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 10 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 7 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. 18523fa 7 LTC1852/LTC1853 PIN FUNCTIONS D9/S0 (Pin 23, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. NC (Pins 31 to 32, LTC1852): No Connect. There is no internal connection to these pins. BUSY (Pin 33): Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will go low and remain low until the conversion is completed. The rising edge may be used to latch the output data. BUSY will also go low while the part is in Program/Readback mode (M1 high, M0 low) and remain low until M0 is brought back high. The output swings between OVDD and OGND. OGND (Pin 34): Digital Data Output Ground. Tie to analog ground plane. May be tied to logic ground if desired. OVDD (Pin 35): Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass to OGND with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low selects a unipolar input span, a high logic level selects a bipolar input span. A0 to A2 (Pins 39 to 41): MUX Address Input Pins. DIFF (Pin 42): Single-Ended/Differential Select Input. A low logic level selects single ended, a high logic level selects differential. WR (Pin 43): Write Input. In Direct Address mode, WR low enables the MUX address and configuration input pins (Pins 37 to 42). WR can be tied low or the rising edge of WR can be used to latch the data. In Program mode, WR is used to program the sequencer. WR low enables the MUX address and configuration input pins (Pins 37 to 42). The rising edge of WR latches the data and increments the counter to the next sequencer location. RD (Pin 44): Read Input. During normal operation, RD enables the output drivers when CS is low. In Readback mode (M1 high, M0 low), RD going low reads the current sequencer location, RD high advances to the next sequencer location. CONVST (Pin 45): Conversion Start Input. This active low signal starts a conversion on its falling edge. CS (Pin 46): Chip Select Input. The chip select input must be low for the ADC to recognize the CONVST and RD inputs. If SHDN is low, a low logic level on CS selects Nap mode; a high logic level on CS selects Sleep mode. M0 (Pin 36): Mode Select Pin 0. Used in conjunction with M1 to select operating mode. See Table 5. SHDN (Pin 47): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the CS pin. CS low selects Nap mode, CS high selects Sleep mode. Tie high if unused. PGA (Pin 37): Gain Select Input. A high logic level selects gain = 1, a low logic level selects gain = 2. M1 (Pin 48): Mode Select Pin 1. Used in conjunction with M0 to select operating mode. See Table 5. 18523fa 8 LTC1852/LTC1853 PIN FUNCTIONS NOMINAL (V) TYP PIN NAME MAX 1 to 8 9 10 REFOUT 2.5V Reference Output 11 REFIN Reference Buffer Input 12 REFCOMP Reference Buffer Output 13 GND Ground 14 VDD Positive Supply 2.7 5 5.5 15 VDD Positive Supply 2.7 5 16 GND Ground 17 DIFFOUT/S6 Single-Ended/Differential Output 18 A2OUT/S5 19 20 ABSOLUTE MAXIMUM (M) MIN MAX DESCRIPTION MIN CH0 to CH7 Analog Inputs 0 VDD –0.3 VDD + 0.3 COM Analog Input Common Pin 0 VDD –0.3 VDD + 0.3 –0.3 VDD + 0.3 VDD –0.3 VDD + 0.3 –0.3 VDD + 0.3 –0.3 VDD + 0.3 –0.3 6 5.5 –0.3 6 –0.3 VDD + 0.3 OGND 0VDD –0.3 VDD + 0.3 MUX Address Output OGND 0VDD –0.3 VDD + 0.3 A1OUT/S4 MUX Address Output OGND 0VDD –0.3 VDD + 0.3 A0OUT/S3 MUX Address Output OGND 0VDD –0.3 VDD + 0.3 21 D9/S2 (LTC1852) Data Output OGND 0VDD –0.3 VDD + 0.3 21 D11/S2 (LTC1853) Data Output OGND 0VDD –0.3 VDD + 0.3 22 D8/S1 (LTC1852) Data Output OGND 0VDD –0.3 VDD + 0.3 22 D10/S1 (LTC1853) Data Output OGND 0VDD –0.3 VDD + 0.3 23 D7/S0 (LTC1852) Data Output OGND 0VDD –0.3 VDD + 0.3 23 D9/S0 (LTC1853) Data Output OGND 0VDD –0.3 VDD + 0.3 24 to 30 D6 to D0 (LTC1852) Data Outputs OGND 0VDD –0.3 VDD + 0.3 24 to 32 D8 to D0 (LTC1853) Data Outputs OGND 0VDD –0.3 VDD + 0.3 31 to 32 NC (LTC1852) No Connect 33 BUSY Converter Busy Output 0VDD –0.3 VDD + 0.3 34 OGND Output Ground –0.3 VDD + 0.3 35 OVDD Output Supply 5.5 –0.3 6 2.5 0 2.5 4.096 0 0 OGND 0 2.7 5 36 M0 Mode Select Pin 0 0 VDD –0.3 6 37 PGA Gain Select Input 0 VDD –0.3 6 38 UNI/BIP Unipolar/Bipolar Input 0 VDD –0.3 6 39 to 41 A0 to A2 MUX Address Inputs 0 VDD –0.3 6 42 DIFF Single-Ended/Differential Input 0 VDD –0.3 6 43 WR Write Input, Active Low 0 VDD –0.3 6 44 RD Read Input, Active Low 0 VDD –0.3 6 45 CONVST Conversion Start Input, Active Low 0 VDD –0.3 6 46 CS Chip Select Input, Active Low 0 VDD –0.3 6 47 SHDN Shutdown Input, Active Low 0 VDD –0.3 6 48 M1 Mode Select Pin 1 0 VDD –0.3 6 18523fa 9 LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D converter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic, including a programmable sequencer. CONVERSION DETAILS The core analog-to-digital converter in the LTC1852/ LTC1853 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 10-bit/12-bit parallel output. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle is begun, it cannot be restarted. During the conversion, the internal differential capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The outputs of the analog input multiplexer are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches are open, putting the comparator into compare mode. The input switches connect CSAMPLE to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of the conversion, the differential DAC output balances the input charges. The SAR contents (a 10-bit/12-bit data word), which represents the difference of the analog input multiplexer outputs, and the 4-bit address word are loaded into the 14-bit/16-bit output latches. DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where ENOB is the effective number of bits and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1852/LTC1853 maintain near ideal ENOBs up to and beyond the Nyquist input frequency of 200kHz. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD= 20Log V22 + V32 + V42 +...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The LTC1852/LTC1853 have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 18523fa 10 LTC1852/LTC1853 APPLICATIONS INFORMATION If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD ( fa ± fb) = 20Log Amplitude at ( fa ± fb) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB for the LTC1853 (11 effective bits) or 56dB for the LTC1852 (9 effective bits). The LTC1852/LTC1853 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. ANALOG INPUT MULTIPLEXER The analog input multiplexer is controlled using the single-ended/differential pin (DIFF), three MUX address pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain select pin (PGA). The single-ended/differential pin (DIFF) allows the user to configure the MUX as eight single-ended channels relative to the analog input common pin (COM) when DIFF is low or as four differential pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when DIFF is high. The channels (and polarity in the differential case) are selected using the MUX address inputs as shown in Table 1. Unused inputs (including the COM in the differential case) should be grounded to prevent noise coupling. Table 1. Multiplexer Address Table MUX ADDRESS DIFF A2 SINGLE-ENDED CHANNEL SELECTION A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 + + – + – + – + – + – + – + MUX ADDRESS DIFF A2 – – DIFFERENTIAL CHANNEL SELECTION A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 0 0 0 + – 1 0 0 1 – + 1 0 1 0 1 0 1 1 1 1 0 0 + – – + * * + – * – + * * * 1 1 0 1 1 1 1 0 + – * 1 1 1 1 – + * *Not used in differential mode. Connect to AGND. In addition to selecting the MUX channel, the LTC1852/ LTC1853 also allows the user to select between two gains and unipolar or bipolar inputs for a total of four input spans. PGA high selects a gain of 1 (the input span is equal to the voltage on REFCOMP). PGA low selects a gain of 2 where the input span is equal to half of the voltage on REFCOMP. UNI/BIP low selects a unipolar input span, UNI/BIP high selects a bipolar input span. Table 2 summarizes the possible input spans. Table 2. Input Span Table INPUT SPAN UNI/BIP PGA 0 0 0 – REFCOMP/2 0 – 2.048V 0 1 0 – REFCOMP 0 – 4.096V 1 0 ± REFCOMP/4 ±1.024V 1 1 ±REFCOMP/2 ±2.048V REFCOMP = 4.096V 18523fa 11 LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 have a unique differential sampleand-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of the “+” and “–” inputs independent of the common mode voltage. The common mode rejection holds up to high frequencies. The only requirement is that both inputs can not exceed the AVDD power supply voltage or ground. When a bipolar input span is selected the “+” input can swing ± full scale relative to the “–” input but neither input can exceed AVDD or go below ground. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar offset will vary. The change in bipolar offset is typically less than 0.1% of the common mode voltage. input(s) must settle after the small current spike before the next conversion starts (settling time must be less than 150ns for full throughput rate). Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (