LTC1864/LTC1865
µPower, 16-Bit, 250ksps
1- and 2-Channel
ADCs in MSOP
DESCRIPTION
FEATURES
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16-Bit 250ksps ADCs in MSOP Package
Single 5V Supply
Low Supply Current: 850μA (Typ)
Auto Shutdown Reduces Supply Current
to 2μA at 1ksps
True Differential Inputs
1-Channel (LTC1864) or 2-Channel (LTC1865)
Versions
SPI/MICROWIRE™ Compatible Serial I/O
16-Bit Upgrade to 12-Bit LTC1286/LTC1298
Pin Compatible with 12-Bit LTC1860/LTC1861
Guaranteed Operation to +125°C (MSOP Package)
APPLICATIONS
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High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
The LTC®1864/LTC1865 are 16-bit A/D converters that
are offered in MSOP and SO-8 packages and operate
on a single 5V supply. At 250ksps, the supply current is
only 850μA. The supply current drops at lower speeds
because the LTC1864/LTC1865 automatically power down
between conversions. These 16-bit switched capacitor
successive approximation ADCs include sample-andholds. The LTC1864 has a differential analog input with an
adjustable reference pin. The LTC1865 offers a softwareselectable 2-channel MUX and an adjustable reference pin
on the MSOP version.
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
These ADCs can be used in ratiometric applications or with
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to
1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
TYPICAL APPLICATION
Single 5V Supply, 250ksps, 16-Bit Sampling ADC
Supply Current vs Sampling Frequency
1000
1μF
5V
LTC1864
1
2
ANALOG INPUT
0V TO 5V
3
4
VREF
VCC
IN+
SCK
IN–
SDO
GND
CONV
8
7
6
5
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
SUPPLY CURRENT (μA)
100
10
1
0.1
18645 TA01
0.01
0.01
0.1
10
100
1
SAMPLING FREQUENCY (kHz)
1000
18645 TA02
18645fb
1
LTC1864/LTC1865
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) .................................................7V
Ground Voltage Difference
AGND, DGND LTC1865 MSOP Package ............ ±0.3V
Analog Input ................ (GND – 0.3V) to (VCC + 0.3V)
Digital Input ................................ (GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (VCC + 0.3V)
Power Dissipation .............................................. 400mW
Operating Temperature Range
LTC1864C/LTC1865C/
LTC1864AC/LTC1865AC...........................0°C to 70°C
LTC1864I/LTC1865I/
LTC1864AI/LTC1865AI ...................... – 40°C to 85°C
LTC1864H/LTC1865H
LTC1864AH/LTC1865AH ................. – 40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
PIN CONFIGURATION
LTC1864
LTC1865
TOP VIEW
VREF
IN+
IN¯
GND
8
7
6
5
1
2
3
4
TOP VIEW
VCC
SCK
SDO
CONV
MS8 PACKAGE
8-LEAD PLASTIC MSOP
VREF
VCC
SCK
SDO
SDI
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
LTC1864
10
9
8
7
6
1
2
3
4
5
CONV
CH0
CH1
AGND
DGND
TJMAX = 150°C, θJA = 210°C/W
LTC1865
TOP VIEW
TOP VIEW
8 VCC
CONV 1
8 VCC
IN+
2
7 SCK
CH0 2
7 SCK
IN–
3
6 SDO
CH1 3
6 SDO
5 CONV
GND 4
5 SDI
VREF 1
GND 4
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1864CMS8#PBF
LTC1864CMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
0°C to 70°C
LTC1864IMS8#PBF
LTC1864IMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
–40°C to 85°C
LTC1864HMS8#PBF
LTC1864HMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
–40°C to 125°C
LTC1864ACMS8#PBF
LTC1864ACMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
0°C to 70°C
LTC1864AIMS8#PBF
LTC1864AIMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
–40°C to 85°C
LTC1864AHMS8#PBF
LTC1864AHMS8#TRPBF
LTHQ
8-Lead Plastic MSOP
–40°C to 125°C
LTC1864CS8#PBF
LTC1864CS8#TRPBF
1864
8-Lead Plastic SO
0°C to 70°C
LTC1864IS8#PBF
LTC1864IS8#TRPBF
1864I
8-Lead Plastic SO
–40°C to 85°C
LTC1864ACS8#PBF
LTC1864ACS8#TRPBF
1864A
8-Lead Plastic SO
0°C to 70°C
LTC1684AIS8#PBF
LTC1684AIS8#TRPBF
1864AI
8-Lead Plastic SO
–40°C to 85°C
LTC1865CMS#PBF
LTC1865CMS#TRPBF
LTHS
10-Lead Plastic MSOP
0°C to 70°C
LTC1865IMS#PBF
LTC1865IMS#TRPBF
LTHS
10-Lead Plastic MSOP
–40°C to 85°C
18645fb
2
LTC1864/LTC1865
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1865HMS#PBF
LTC1865HMS#TRPBF
LTHS
10-Lead Plastic MSOP
–40°C to 125°C
LTC1865ACMS#PBF
LTC1865ACMS#TRPBF
LTHS
10-Lead Plastic MSOP
0°C to 70°C
LTC1865AIMS#PBF
LTC1865AIMS#TRPBF
LTHS
10-Lead Plastic MSOP
–40°C to 85°C
LTC1865AHMS#PBF
LTC1865AHMS#TRPBF
LTHS
10-Lead Plastic MSOP
–40°C to 125°C
LTC1865CS8#PBF
LTC1865CS8#TRPBF
1865
8-Lead Plastic SO
0°C to 70°C
LTC1865IS8#PBF
LTC1865IS8#TRPBF
1865I
8-Lead Plastic SO
–40°C to 85°C
LTC1865ACS8#PBF
LTC1865ACS8#TRPBF
1865A
8-Lead Plastic SO
0°C to 70°C
LTC1865AIS8#PBF
LTC1865AIS8#TRPBF
1865AI
8-Lead Plastic SO
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1864CMS8
LTC1864CMS8#TR
LTHQ
8-Lead Plastic MSOP
0°C to 70°C
LTC1864IMS8
LTC1864IMS8#TR
LTHQ
8-Lead Plastic MSOP
–40°C to 85°C
LTC1864HMS8
LTC1864HMS8#TR
LTHQ
8-Lead Plastic MSOP
–40°C to 125°C
LTC1864ACMS8
LTC1864ACMS8#TR
LTHQ
8-Lead Plastic MSOP
0°C to 70°C
LTC1864AIMS8
LTC1864AIMS8#TR
LTHQ
8-Lead Plastic MSOP
–40°C to 85°C
LTC1864AHMS8
LTC1864AHMS8#TR
LTHQ
8-Lead Plastic MSOP
–40°C to 125°C
LTC1864CS8
LTC1864CS8#TR
1864
8-Lead Plastic SO
0°C to 70°C
LTC1864IS8
LTC1864IS8#TR
1864I
8-Lead Plastic SO
–40°C to 85°C
LTC1864ACS8
LTC1864ACS8#TR
1864A
8-Lead Plastic SO
0°C to 70°C
LTC1684AIS8
LTC1684AIS8#TR
1864AI
8-Lead Plastic SO
–40°C to 85°C
LTC1865CMS
LTC1865CMS#TR
LTHS
10-Lead Plastic MSOP
0°C to 70°C
LTC1865IMS
LTC1865IMS#TR
LTHS
10-Lead Plastic MSOP
–40°C to 85°C
LTC1865HMS
LTC1865HMS#TR
LTHS
10-Lead Plastic MSOP
–40°C to 125°C
LTC1865ACMS
LTC1865ACMS#TR
LTHS
10-Lead Plastic MSOP
0°C to 70°C
LTC1865AIMS
LTC1865AIMS#TR
LTHS
10-Lead Plastic MSOP
–40°C to 85°C
LTC1865AHMS
LTC1865AHMS#TR
LTHS
10-Lead Plastic MSOP
–40°C to 125°C
LTC1865CS8
LTC1865CS8#TR
1865
8-Lead Plastic SO
0°C to 70°C
LTC1865IS8
LTC1865IS8#TR
1865I
8-Lead Plastic SO
–40°C to 85°C
LTC1865ACS8
LTC1865ACS8#TR
1865A
8-Lead Plastic SO
0°C to 70°C
LTC1865AIS8
LTC1865AIS8#TR
1865AI
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
18645fb
3
LTC1864/LTC1865
CONVERTER AND MULTIPILEXER CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865
PARAMETER
CONDITIONS
MIN
TYP
MAX
LTC1864A/LTC1865A
MIN
TYP
MAX
UNITS
Resolution
l
16
16
Bits
No Missing Codes Resolution
l
14
15
Bits
INL
l
l
(Note 3)
H-Grade (Note 3)
±8
±8.5
Transition Noise
±6
±6.5
1.1
l
Gain Error
Offset Error
LTC1864 SO-8 and MSOP, LTC1865 MSOP
LTC1865 SO-8
Input Differential Voltage Range VIN = IN+ – IN–
Absolute Input Range
IN+ Input
IN– Input
VREF Input Range
LTC1864 SO-8 and MSOP,
LTC1865 MSOP
Analog Input Leakage Current
(Note 4)
CIN Input Capacitance
In Sample Mode
During Conversion
l
l
l
1.1
±20
±2
±3
±5
±7
±2
±3
LSB
LSB
LSBRMS
±20
mV
±5
±7
mV
mV
0
VREF
0
VREF
V
–0.05
–0.05
VCC + 0.05
VCC/2
–0.05
–0.05
VCC + 0.05
VCC/2
V
V
1
VCC
1
VCC
V
±1
μA
l
±1
12
5
12
5
pF
pF
DYNAMIC ACCURACY
TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
SNR
Signal-to-Noise Ratio
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
THD
Total Harmonic Distortion Up to 5th Harmonic
CONDITIONS
TYP
MAX
UNITS
87
dB
10kHz Input Signal
100kHz Input Signal
83
76
dB
dB
10kHz Input Signal
100kHz Input Signal
88
77
dB
dB
20
MHz
125
kHz
Full Power Bandwidth
Full Linear Bandwidth
MIN
S/(N+D) ≥ 75dB
18645fb
4
LTC1864/LTC1865
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VIH
High Level Input Voltage
VCC = 5.25V
l
VIL
Low Level Input Voltage
VCC = 4.75V
l
0.8
V
2.5
μA
–2.5
μA
2.4
UNITS
V
IIH
High Level Input Current
VIN = VCC
l
IIL
Low Level Input Current
VIN = 0V
l
VOH
High Level Output Voltage
VCC = 4.75V, IO = 10μA
VCC = 4.75V, IO = 360μA
l
l
VOL
Low Level Output Voltage
VCC = 4.75V, IO = 1.6mA
●
0.4
V
IOZ
Hi-Z Output Leakage
CONV = VCC
●
±3
μA
ISOURCE
Output Source Current
VOUT = 0V
–25
mA
ISINK
Output Sink Current
VOUT = VCC
20
mA
IREF
Reference Current (LTC1864 SO-8 and MSOP,
LTC1865 MSOP)
CONV = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
0.05
3
0.1
μA
mA
ICC
Supply Current
CONV = VCC After Conversion
CONV = VCC After Conversion, H-Grade
fSMPL = fSMPL(MAX)
●
●
●
0.001
0.001
0.85
3
5
1.3
μA
μA
mA
PD
Power Dissipation
fSMPL = fSMPL(MAX)
4.5
2.4
4.74
4.72
4.25
V
V
mW
18645fb
5
LTC1864/LTC1865
RECOMMENDED OPERATING CONDITIONS
The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
LTC1864/LTC1865
SYMBOL
PARAMETER
VCC
Supply Voltage
fSCK
Clock Frequency
CONDITIONS
Total Cycle Time
tSMPL
Analog Input Sampling Time
tsuCONV
TYP
4.75
H-Grade
tCYC
MIN
●
●
16 • SCK + tCONV
MAX
UNITS
5.25
V
20
16.7
MHz
MHz
μs
LTC1864 (Note 5)
LTC1865 (Note 5)
16
14
SCK
SCK
Setup Time CONV↓ Before First SCK↑
(See Figure 1)
H-Grade
60
65
thDI
Hold Time SDI After SCK↑
LTC1865
15
tsuDI
Setup Time SSDI Stable Before SCK↑
LTC1865
tWHCLK
SCK High Time
fSCK = fSCK(MAX)
40%
1/fSCK
tWLCLK
SCK Low Time
fSCK = fSCK(MAX)
40%
1/fSCK
tWHCONV
CONV High Time Between Data Transfer
Cycles
(Note 5)
tCONV
μs
tWLCONV
CONV Low Time During Data Transfer
(Note 5)
16
thCONV
Hold Time CONV Low After Last SCK↑
30
30
ns
ns
ns
15
ns
SCK
13
ns
18645fb
6
LTC1864/LTC1865
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
tCONV
Conversion Time (See Figure 1)
fSMPL(MAX)
CONDITIONS
MIN
H-Grade
●
●
H-Grade
●
●
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF, H-Grade
●
●
H-Grade
CLOAD = 20pF
CLOAD = 20pF, H-Grade
Maximum Sampling Frequency
tdDO
Delay Time, SCK↓ to SDO Data Valid
tdis
Delay Time, CONV↑ to SDO Hi-Z
ten
Delay Time, CONV↓ to SDO Enabled
thDO
Time Output Data Remains Valid After SCK↓ CLOAD = 20pF
tr
SDO Rise Time
tf
SDO Fall Time
TYP
MAX
2.75
2.75
3.2
3.3
250
234
UNITS
μs
μs
kHz
kHz
15
20
25
30
ns
ns
ns
●
●
30
30
60
65
ns
ns
●
●
30
30
60
65
ns
ns
●
10
ns
CLOAD = 20pF
8
ns
CLOAD = 20pF
4
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
5
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Guaranteed by design, not subject to test.
18645fb
7
LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling
Frequency
VCC = 5V
TA = 25°C
CONV LOW = 800ns
800
10
1
0.1
0.1
10
100
1.0
SAMPLING FREQUENCY (kHz)
600
400
0
–50
1000
VCC = 5V
VREF = 5V
fSAMPLE = 250kHz
CONV HIGH = 3.2μS
50
25
0
75
TEMPERATURE (°C)
–25
Reference Current vs
Sampling Rate
500
400
300
200
100
0
–50
125
30
20
50
25
0
75
TEMPERATURE (°C)
100
10
125
Reference Current vs
Reference Voltage
60
VCC = 5V
54 VREF = 5V
f = 250kHz
53 S
VCC = 5V
TA = 25°C
fS = 250kHz
50
REFERENCE CURRENT (μA)
40
–25
18645 G03
55
REFERENCE CURRENT (μA)
REFERENCE CURRENT (μA)
600
Reference Current vs
Temperature
VCC = 5V
TA = 25°C
VREF = 5V
CONV LOW = 800ns
50
100
700
18645 G02
18645 G01
60
CONV = VCC = 5V
800
200
0.01
0.01
Sleep Current vs Temperature
1000
900
SUPPLY CURRENT (μA)
100
SUPPLY CURRENT (μA)
Supply Current vs Temperature
1000
SLEEP CURRENT (nA)
1000
52
51
50
49
48
47
40
30
20
10
46
0
0
50
100
150
200
SAMPLE RATE (kHz)
45
–50
250
0
50
25
0
75
TEMPERATURE (°C)
–25
18645 G04
2
100
ANALOG INPUT LEAKAGE (nA)
2
DNL ERROR (LSBs)
1
–2
0
–1
0
16384
32768
CODE
49152
65536
18645 G07
1
2
3
VREF (V)
–2
0
16384
32768
CODE
5
4
Analog Input Leakage Current vs
Temperature
VCC = 5V
TA = 25°C
VREF = 5V
VCC = 5V
TA = 25°C
VREF = 5V
0
0
18645 G06
Typical DNL Curve
4
INL ERROR (LSBs)
125
18645 G05
Typical INL Curve
–4
100
49152
65536
VCC = 5V
VREF = 5V
CONV = 0V
75
50
25
0
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
18645 G08
18645 G09
18645fb
8
LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs
Reference Voltage
20
5
VCC = 5V
TA = 25°C
VCC = 5V
4 VREF = 5V
50
25
0
VCC = 5V
15 TA = 25°C
CHANGE IN GAIN ERROR (LSB)
CHANGE IN OFFSET (LSB)
CHANGE IN OFFSET ERROR (LSB)
75
Change in Gain Error vs
Reference Voltage
Change in Offset vs Temperature
3
2
1
0
–1
–2
–3
1
0
3
4
2
REFERENCE VOLTAGE (V)
–5
–50
5
50
25
0
75
TEMPERATURE (°C)
1800
VCC = 5V
VREF = 5V
3
100
0
–1
1000
800
729
600
–2
–3
400
–4
200
516
0
4096 Point FFT Nonaveraged
0
–40
–60
–80
0
0
1
CODE
2
12
0
0
3
4
5
–140
0
100
90
–20
80
70
–30
70
–40
60
SINAD
THD (dB)
–50
–60
–70
30
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
20
10
0
SFDR (dB)
–10
SNR
40
1
10
100
1000
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
–80
–90
–100
1
10
100
1000
FIN (kHz)
FIN (kHz)
18645 G16
40
60
80
FREQUENCY (kHz)
100
120
SFDR vs Frequency
0
80
50
20
18645 G15
THD vs Frequency
60
fS = 203.125kHz
fIN = 99.72763kHz
VCC = 5V
VREF = 5V
TA = 25°C
–20
18645 G14
SINAD vs Frequency
5
–120
–4 –3 –2 –1
125
100
90
4
3
2
REFERENCE VOLTAGE(V)
–100
127
0
100
1
18645 G12
AMPLITUDE (dB)
1178
1200
1
18645 G13
SINAD (dB)
0
125
VCC = 5V
TA = 25°C
VREF = 5V
1534
1400
2
FREQUENCY
CHANGE IN GAIN ERROR (LSB)
1600
50
25
0
75
TEMPERATURE (°C)
–10
Histogram of 4096 Conversions of
a DC Input Voltage
5
–25
–5
18645 G11
Change in Gain Error vs
Temperature
–5
–50
0
–20
–25
18645 G10
4
5
–15
–4
–25
10
50
40
30
VCC = 5V
VREF = 5V
TA = 25°C
VIN = 0dB
20
10
0
1
10
100
1000
FIN (kHz)
18645 G17
18645 G18
18645fb
9
LTC1864/LTC1865
PIN FUNCTIONS
LTC1864
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN +,
IN–
(Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
LTC1865 (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied directly
to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied directly
to an analog ground plane.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to AGND.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
LTC1865 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane. VREF is tied internally to this pin.
18645fb
10
LTC1864/LTC1865
FUNCTIONAL BLOCK DIAGRAM
CONV (SDI) SCK
VCC
PIN NAMES IN
PARENTHESES
REFER TO LTC1865
CONVERT
CLK
SDO
SERIAL
PORT
BIAS AND
SHUTDOWN
DATA IN
16 BITS
IN+
(CH0)
+
IN–
(CH1)
–
16-BIT
SAMPLING
ADC
DATA OUT
18645 BD
GND
VREF
18645fb
11
LTC1864/LTC1865
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
VOH
SDO
VOL
VCC tdis WAVEFORM 2, ten
3k
SDO
tr
tdis WAVEFORM 1
20pF
tf
18645 TC04
18645 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
VIH
CONV
SDO
18645 TC03
SDO
WAVEFORM 1
(SEE NOTE 1)
ten
90%
tdis
Voltage Waveforms for SDO Delay Times,tdDO and thDO
SDO
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
VIL
tdDO
18645 TC05
thDO
VOH
SDO
VOL
18645 TC02
18645fb
12
LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1864 OPERATION
Analog Inputs
Operating Sequence
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN + ”
and “IN–” inputs. A zero code will occur when IN+ minus
IN– equals zero. Full scale occurs when IN+ minus IN–
equals VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
is grounded and VREF is tied to VCC, a rail-to-rail input
span will result on “IN+” as shown in Figure 3.
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t CONV, the conversion is
finished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Reference Input
The voltage on the reference input of the LTC1864 defines
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from VCC to 1V.
tsuCONV
CONV
tSMPL
SLEEP MODE
tCONV
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SCK
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
SDO
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F01
Figure 1. LTC1864 Operating Sequence
1111111111111111
1μF
1111111111111110
VCC
•
•
•
LTC1864
0000000000000001
0000000000000000
1
VIN*
VREF
VREF – 1LSB
Figure 2. LTC1864 Transfer Curve
VREF – 2LSB
1LSB
0V
*VIN = IN+ – IN–
VIN = 0V TO VCC
VREF
VCC
2
IN+
SCK
3
IN–
SDO
GND
CONV
4
18645 F02
8
7
6
5
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
18645 F03
Figure 3. LTC1864 with Rail-to-Rail Input Span
18645fb
13
LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1865 OPERATION
Operating Sequence
The LTC1865 conversion cycle begins with the rising edge
of CONV. After a period equal to t CONV, the conversion is
finished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input
on the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. The shift clock (SCK) synchronizes the data transfer
with each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefinitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
“+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF
minus 1LSB. See Figure 5. Both the “+” and “–” inputs
are sampled at the same time so common mode noise
is rejected. The input span in the SO-8 package is fixed
at VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference
input of the LTC1865 MSOP package defines the span
of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to VCC.
Table 1. Multiplexer Channel Selection
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
MUX ADDRESS
SGL/DIFF ODD/SIGN
0
1
1
1
0
0
1
0
CHANNEL #
0
1
+
+
+
–
–
+
GND
–
–
18645 TBL1
CONV
SDI
tSMPL
SLEEP MODE
tCONV
DON’T CARE
S/D O/S
1
2
DON’T CARE
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SCK
SDO
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F04
Figure 4. LTC1865 Operating Sequence
18645fb
14
LTC1864/LTC1865
APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864/LTC1865 should be used with an analog
ground plane and single point grounding techniques. Do not
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1865 MSOP package and GND for the LTC1864
and LTC1865 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864/LTC1865
have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810,
LT1630, LT1226 or LT1215). But if large source resistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
1111111111111111
1111111111111110
•
•
•
VIN*
0000000000000001
0000000000000000
VCC
VCC – 1LSB
VCC – 2LSB
1LSB
0V
*VIN = (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
18645 F05
Figure 5. LTC1865 Transfer Curve
18645fb
15
16
5VDIG
IN–
E9
E8
J1
E1
4
1
4
2
3
JP9
3
1
JP8
J2
2
AGND
IN+
15V
15V
5
6
5
6
R8
51Ω
0PT
IN–
R7
51Ω
0PT
IN+
–
+
VIN
2
JP3
1
1
1
2
3
4
5
6
7
8
JP2
JP1
RESET
CLK
P0
P1
P2
P3
ENP
GND
2
2
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U6
74HC163AD
5VDIG
U9A
74AC00
U9B
74AC00
C6
–15V 0.1μF
U2
OPT
1
16
15
14
13
12
11
10
9
R2
510Ω
R1
510Ω
6
VOUT
U1
GND
LT1021-5
4
C5
15V 0.1μF
C27
0.1μF
2
R3
2Ω
5VDIG
5VDIG
C11
390pF
C10
680pF
OPT
C23
0.1μF
1
2
3
4
5
6
7
8
C16
0.1μF
RESET
CLK
P0
P1
P2
P3
ENP
GND
U13B
74AC32
16
15
14
13
12
11
10
9
C17
0.1μF
CLK
1
2
3
4
RN1
330
1
R12
10k
5VDIG
1 +
V
2
GND
3
SET
U10
LTC1799
DIV
OUT
C18
0.1μF
U12B
74AC109 16
14
10
VCC
JP4
J
Q
13
9 1
K
Q
12
CLK
15
CLR
11
8
PRE
GND
R10
20k
5VDIG
C24
0.1μF
ANALOG GROUND PLANE
U3
LTC1864CMS8
8
VCC
7
SCK
6
SDO
5
CONV
C4
0.1μF
1
V
2 REF
IN+
3
IN–
4
GND
5VAN
C12
1000pF
OPT
5VDIG
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
U7
74HC163AD
5VDIG
C3
10μF
6.3V
1206
C8
1000pF
OPT
U12A
74AC109 16
6
2
VCC
J
Q
3
7
K
Q
4
CLK
1
CLR
5
8
PRE
GND
C9
180pF
C7
390pF
C1
0.1μF
C2
1μF
10V
0805
15V
4
5
2
8
7
6
5
VIN
3
2
R4
2Ω
1
C26
10μF
6.3V
1206
U8C
74AC14
U13C
74AC32
3
2
1
U8D
74AC14
JP7
U8B
74AC14
U8A
74AC14
5VDIG
C25
5VDIG 0.1μF
C22
47pF
R6
402Ω
1%
C21
47pF
R5
402Ω, 1%
3
JP6
VOUT
GND
2
5VAN
LTC1864 Evaluation Circuit Schematic
C13
0.1μF
U8E
74AC14
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C14
0.1μF
U13D
74AC32
1
2
JP5
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
R9
51Ω
CONV
J3
E5
E4
E6
CLKIN
CLKOUT
DOUT
DGND
E3 ENABLE
DATA
E7
DGND
E2
C15
5VDIG 0.1μF
U9D
74AC00
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
J4
3201S40G1
18645 AI1
NOTES: UNLESS OTHERWISE SPECIFIED
INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;
ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
U13A
74AC32
C19
5VDIG 0.1μF
U8F
74AC14
U5
74HC595ADT
U9C
74AC00
QB
VCC
QC
QA
QD
A
QE
OENB
QF
LCLK
QG
SCLK
RESET QH
GND
SQH
1
2
3
4
5
6
7
8
5VDIG
U4
5VDIG 74HC595ADT
16
QB
V
15 CC
QC
QA
14
QD
A
13
QE
OENB
12
QF
LCLK
11
QG
SCLK
10
RESET QH
9
GND
SQH
5VDIG
LTC1864/LTC1865
APPLICATIONS INFORMATION
18645fb
LTC1864/LTC1865
APPLICATIONS INFORMATION
Component Side Silk Screen for LTC1864 Evaluation Circuit
Component Side Showing Traces
(Note Sider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds
Supply Layer with 5V Digital Supply and
Analog Ground Repeated
18645fb
17
LTC1864/LTC1865
APPLICATIONS INFORMATION
U11
15V LT1121CST-5
1
VIN
5VAN
C3
10μF
6.3V
1206
1V to 5V REFERENCE
0V to VREF INPUT
5VAN
3
VOUT
GND
2
R4
2Ω
5VDIG
C26
10μF
6.3V
1206
C4
0.1μF
5VDIG
1
V
2 REF
IN+
3
IN–
4
GND
RN1
330
8
VCC
7
SCK
6
SDO
5
CONV
1
2
3
4
1
RO
2
RE
3
DE
4
DI
8
7
6
5
5VDIG
LTC1485
8
VCC
7
B
6
A
5
GND
15V
120Ω
U3
LTC1864CMS8
ANALOG GROUND PLANE
C23
0.1μF
5VDIG
5VDIG
U12B
74AC109 16
14
10
VCC
J
Q
13
9
K
Q
12
CLK
15
CLR
11
8
PRE
GND
v
U9B
74AC00
5VDIG
U9A
74AC00
4
1
2
5
3
500Ω
5V
MC74VHC1G66
v
U12A
74AC109 16
6
2
VCC
J
Q
7
3
K
Q
4
CLK
1
CLR
8
5
PRE
GND
4 CONDUCTOR
TELEPHONE WIRES
TO RECEIVER
C24
0.1μF
5VDIG
C16
0.1μF
C17
0.1μF
5VDIG
5VDIG
5VDIG
74AC74
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RESET
CLK
P0
P1
P2
P3
ENP
GND
VCC
RCO
Q0
Q1
Q2
Q3
ENT
LO
5VDIG
16
15
14
13
12
11
10
9
C18
0.1μF
PRE
D
CLK
CLR
74AC86
Q
v
1
2
3
4
5
6
7
8
U7
74HC163AD
U10
LTC1799
100k
1 +
V
2
GND
3
SET
OUT
DIV
5
Q
5VDIG
4
74AC74
U13C
74AC32
PRE
D
CLK
CLR
Q
v
U6
74HC163AD
Q
CLK
18645 AI2
U13B
74AC32
Figure 6. LTC1864 Manchester Transmitter
18645fb
18
LTC1864/LTC1865
APPLICATIONS INFORMATION
10
6
12
Q
CLK 11
13
PRE
D
CLK
CLR
Q
9
PRE
D
CLK
CLR
Q
Q
10
12
CLK 11
13
6
Q
8
Q
Q
9
8
4
2
CLK 3
1
VCC
IC4D
74AC08
IC4C
74AC08
PRE
D
CLK
CLR
Q
Q
5
6
IC3B
74AC74
10
12
CLK 11
13
PRE
D
CLK
CLR
Q 9
STROBE
Q
8
IC8
74AC595
RECEIVE CLOCK AT
8 X TRANSMIT
CLOCK FREQUENCY
14
11
VCC
1
RO
2
RE
3
DE
4
DI
VCC
8
VCC
7
B
6
A
5
GND
10
SCK
SCL
RCK
v
12
SER
13
OPTIONAL SERIAL TO
PARALLEL CONVERTER
VCC
15V SUPPLY TO
TRANSMITTER
11
10
IC7B
74AC109
DATA
11
14
12
13
15
PRE
J
CLK
K
CLR
Q 10
12
13
v
R1
120Ω
Q
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
15
1
2
3
4
5
6
7
9
D15
D14
D13
D12
D11
D10
D9
D8
15
1
2
3
4
5
6
7
9
D7
D6
D5
D4
D3
D2
D1
D0
IC9
74AC595
14
STROBE
8
SER
SCK
SCL
RCK
v
U1
LTC1485
4 CONDUCTOR
TELEPHONE WIRES
TO TRANSMITTER
IC3A
74AC74
IC6C
74LS32D
DATA
DATA
IC1B
74AC74
PRE
D
CLK
CLR
IC4B
74AC08
v
5
5
VCC
IC2B
74AC74
v
Q
4
2
CLK 3
1
v
PRE
D
CLK
CLR
IC4A
74AC08
IC2A
74AC74
v
4
DATA IN 2
CLK 3
1
IC5C
74AC86
VCC
IC1A
74AC74
v
VCC
IC6D
74AC32
VCC
v
VCC
8
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
9
18645 AI3
Figure 7. LTC1864 Manchester Receiver
18645fb
19
LTC1864/LTC1865
APPLICATIONS INFORMATION
Transmit LTC1864 Data Over Modular Telephone Wire
Using Simple Transmitter/Receiver
Figure 6 shows a simple Manchester encoder and differential transmitter suitable for use with the LTC1864.
This circuit allows transmission of data over inexpensive
telephone wire. This is useful for measuring a remote
sensor, particularly when the cost of preserving the analog
signal over a long distance is high.
Manchester encoding is a clock signal that is modulated
by exclusive ORing with the data signal. The resulting
signal contains both clock and data information and has
an average duty cycle of 50%, that also allows transformer
coupling. In practice, generating a Manchester encoded
signal with an XOR gate will often produce glitches due
to the skew between data and clock transitions. The D
flip-flops in this encoder retime the clock and data such
that the respective edges are closely aligned, effectively
suppressing glitches. The retimed data and clock are then
XORed to produce the Manchester encoded data, which
is interfaced to telephone wire with an LTC1485 RS485
transceiver.
In order to synchronize to incoming data, the receiver
needs a sequence to indicate the start of a data word. The
transmitter schematic shows logic that will produce 31
zeros, a start bit, followed by the 16 data bits (one sample
every 48 clock cycles) at a clock frequency of 1MHz set by
the LTC1799 oscillator. Sending at least 18 zeros before
each start bit ensures that if synchronization is lost, the
receiver can resynchronize to a start bit under all conditions. The serial to parallel converter shown in Figure 7
requires 18 zeros to avoid triggering on data bits.
The Manchester receiver shown in Figure 7 was adopted
from Xilinx application note 17-30 and would typically be
implemented in an FPGA. The decoder clock frequency is
nominally 8 times the transmit clock frequency and is very
tolerant of frequency errors. The outputs of the decoder
are data and a strobe that indicates a valid data bit. The
data can be deserialized using shift registers as shown.
The start bit resets the J-K/flip-flop on its way into the
first shift register. When it appears at the QHIN output of
the second shift register, it sets the flip-flop that loads the
parallel data into the output register.
With AC family CMOS logic at 5V the receiver clock frequency is limited to 20MHz; the corresponding transmitter
clock frequency is 2.5MHz. If the receiver is implemented
in an FPGA that can be clocked at 160MHz, the LTC1864
can be clocked at its rated clock frequency of 20MHz.
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20
LTC1864/LTC1865
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
0.42 ± 0.04
(.0165 ± .0015)
TYP
3.2 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
0.254
(.010)
8
7 6 5
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
DETAIL “A”
0.52
(.206)
REF
0° – 6° TYP
GAUGE PLANE
1
0.53 ± 0.015
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
1.10
(.043)
MAX
2 3
4
0.86
(.034)
REF
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
0.65
(.0256)
NOTE:
BCS
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.13 ± 0.05
(.005 ± .002)
MSOP (MS8) 1001
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21
LTC1864/LTC1865
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.10
(.192 ± .004)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.01
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.50
(.0197)
TYP
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 1001
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22
LTC1864/LTC1865
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1864/LTC1865
TYPICAL APPLICATION
Sample Two Channels Simultaneously with a Single Input ADC
4096 Point FFT of Output
+
4.096V
REF
5k
4.096V
REF
100Ω
1/2
LT1492
–
100pF
0.1μF
1μF
0.1μF
1μF
20k
8
VCC
28.7k
5pF
10k
10k
2
1μF
3
0.1μF
f2
(0V TO 2V)
IN–
5V
5k
IN+
+
8
0.1μF
1/2
LT1492
–
4
1
REF
7
SCK
6
LTC1864
SDO
5
CONV
GND
4
AMPLITUDE (dB)
5V
0.1μF
f1
(0V TO 0.66V)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
f1 = 7.507324kHz AT 530mVP-P
f2 = 45.007324kHz AT 1.7VP-P
fS = 100kHz
0
100Ω
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
18645 TA03b
100pF
18645 TA03a
RELATED PARTS
PART NUMBER
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
LTC1417
400ksps
20mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
LTC1418
200ksps
15mW
Serial/Parallel I/O, Internal Reference, 5V or ±5V
200ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
14-Bit Serial I/O ADCs
16-Bit Serial I/O ADCs
LTC1609
References
LT1460
Micropower Precision Series Reference
Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
LT1790
Micropower Low Dropout Reference
60μA Supply Current, 10ppm/°C, SOT-23
LT1468/LT1469
Single/Dual 90MHz, 16-Bit Accurate Op Amps
22V/μs Slew Rate, 75μV/125μV Offset
LT1806/LT1807
Single/Dual 325MHz Low Noise Op Amps
140V/μs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
LT1809/LT1810
Single/Dual 180MHz Low Distortion Op Amps
350V/μs Slew Rate, –90dBc Distortion at 5MHz
Op Amps
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24 Linear Technology Corporation
LT 1207 REV B • PRINTED IN USA
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(408) 432-1900 ● FAX: (408) 434-0507
●
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