LTC1863/LTC1867
12-/16-Bit, 8-Channel
200ksps ADCs
FEATURES
DESCRIPTION
AEC-Q100 Qualified for Automotive Applications
nn Sample Rate: 200ksps
nn 16-Bit No Missing Codes and ±2LSB Max INL
nn 8-Channel Multiplexer with:
nn Single-Ended or Differential Inputs and
nn Unipolar or Bipolar Conversion Modes
nn SPI/MICROWIRE Serial I/O
nn Signal-to-Noise Ratio: 89dB
nn Single 5V Operation
nn On-Chip or External Reference
nn Low Power: 1.3mA at 200ksps, 0.76mA at 100ksps
nn Sleep Mode
nn Automatic Nap Mode Between Conversions
nn 16-Pin Narrow SSOP Package
The LTC®1863/LTC1867 are pin-compatible, 8-channel
12-/16-bit A/D converters with serial I/O, and an internal
reference. The ADCs typically draw only 1.3mA from a
single 5V supply.
nn
The 8-channel input multiplexer can be configured for
either single-ended or differential inputs and unipolar
or bipolar conversions (or combinations thereof). The
automatic nap and sleep modes benefit power sensitive
applications.
The LTC1867’s DC performance is outstanding with a
±2LSB INL specification and no missing codes over temperature. The signal-to-noise ratio (SNR) for the LTC1867
is typically 89dB, with the internal reference.
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863/LTC1867 can be used in space-sensitive as well
as low-power applications.
APPLICATIONS
Industrial Process Control
High Speed Data Acquisition
nn Battery Operated Systems
nn Multiplexed Data Acquisition Systems
nn Imaging Systems
nn
All registered trademarks and trademarks are the property of their respective owners.
nn
BLOCK DIAGRAM
Integral Nonlinearity vs Output Code
(LTC1867)
2.0
1
2
3
4
5
6
7
8
ANALOG
INPUT
MUX
LTC1863/LTC1867 16
15
14
13
+ 12-/16-BIT
SERIAL
200ksps
12
PORT
–
ADC
11
10
INTERNAL
2.5V REF
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
1.5
1.0
INL (LSB)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
0.5
0
–0.5
–1.0
9
18637 BD
REFCOMP
–1.5
–2.0
0
16384
32768
49152
OUTPUT CODE
65536
18637 GO1
Rev. E
Document Feedback
For more information www.analog.com
1
LTC1863/LTC1867
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1, 2)
Supply Voltage (VDD).................................... –0.3V to 6V
Analog Input Voltage
CH0-CH7/COM (Note 3)............– 0.3V to (VDD + 0.3V)
VREF, REFCOMP (Note 4).......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (SDI, SCK, CS/CONV)
(Note 4).................................................. –0.3V to 10V
Digital Output Voltage (SDO)........ –0.3V to (VDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC1863C/LTC1867C/LTC1867AC............. 0°C to 70°C
LTC1863I/LTC1867I/LTC1867AI............–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
TOP VIEW
CH0 1
16 VDD
CH1 2
15 GND
CH2 3
14 SDI
CH3 4
13 SDO
CH4 5
12 SCK
CH5 6
11 CS/CONV
CH6 7
10 VREF
CH7/COM 8
9
REFCOMP
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 110°C, θJA = 95°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1863CGN#PBF
LTC1863CGN#TRPBF
1863
16-Lead Narrow Plastic SSOP
0°C to 70°C
LTC1863IGN#PBF
LTC1863IGN#TRPBF
1863
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC1867CGN#PBF
LTC1867CGN#TRPBF
1867
16-Lead Narrow Plastic SSOP
0°C to 70°C
LTC1867IGN#PBF
LTC1867IGN#TRPBF
1867
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC1867ACGN#PBF
LTC1867ACGN#TRPBF
1867
16-Lead Narrow Plastic SSOP
0°C to 70°C
LTC1867AIGN#PBF
LTC1867AIGN#TRPBF
1867
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC1863IGN#WTRPBF
1863
16-Lead Narrow Plastic SSOP
–40°C to 85°C
AUTOMOTIVE PRODUCTS**
LTC1863IGN#WPBF
LTC1867IGN#WPBF
LTC1867IGN#WTRPBF
1867
16-Lead Narrow Plastic SSOP
–40°C to 85°C
LTC1867AIGN#WPBF
LTC1867AIGN#WTRPBF
1867
16-Lead Narrow Plastic SSOP
–40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. E
2
For more information www.analog.com
LTC1863/LTC1867
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6)
LTC1863
PARAMETER
CONDITIONS
MIN
TYP
LTC1867
MAX
MIN
TYP
LTC1867A
MAX
MIN
TYP
MAX
UNITS
Resolution
l
12
16
16
Bits
No Missing Codes
l
12
15
16
Bits
Integral Linearity Error
Unipolar (Note 7)
Bipolar
±1
±1
l
l
Differential Linearity Error
±1
l
Transition Noise
±4
±4
–2
0.1
Offset Error
Unipolar (Note 8)
Bipolar
Offset Error Match
Unipolar
Bipolar
l
l
3
±2
±2.5
–1
1.75
0.74
0.74
LSB
LSB
LSB
LSBRMS
±3
±4
±32
±64
±32
±64
LSB
LSB
±1
±1
±2
±2
±2
±2
LSB
LSB
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6)
LTC1863
PARAMETER
CONDITIONS
MIN
Offset Error Drift
Gain Error
TYP
LTC1867
MAX
MIN
±0.5
Unipolar
Bipolar
Gain Error Match
Gain Error Tempco
Internal Reference
External Reference
Power Supply Sensitivity
VDD = 4.75V – 5.25V
DYNAMIC ACCURACY
TYP
LTC1867A
MAX
PARAMETER
TYP
MAX
±0.5
UNITS
ppm/°C
±6
±6
±96
±96
±64
±64
LSB
LSB
±1
±4
±2
LSB
±15
±2.7
±15
±2.7
±15
±2.7
±1
±5
±5
ppm/°C
ppm/°C
LSB
(Note 5)
LTC1863
SYMBOL
MIN
±0.5
CONDITIONS
MIN
TYP
LTC1867/LTC1867A
MAX
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
1kHz Input Signal
73.6
89
dB
S/(N+D)
Signal-to-(Noise + Distortion) Ratio
1kHz Input Signal
73.5
88
dB
THD
Total Harmonic Distortion
1kHz Input Signal, Up to 5th Harmonic
–94.5
–95
dB
Peak Harmonic or Spurious Noise
1kHz Input Signal
–94.5
–95
dB
Channel-to-Channel Isolation
100kHz Input Signal
–100
–117
dB
Full Power Bandwidth
–3dB Point
1.25
1.25
MHz
Rev. E
For more information www.analog.com
3
LTC1863/LTC1867
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL
PARAMETER
CONDITIONS
Analog Input Range
Unipolar Mode (Note 9)
Bipolar Mode
CIN
Analog Input Capacitance for CH0 to
CH7/COM
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
tACQ
Sample-and-Hold Acquisition Time
Input Leakage Current
MIN
l
l
l
On Channels, CHX = 0V or VDD
INTERNAL REFERENCE CHARACTERISTICS
1.5
TYP
MAX
UNITS
0-4.096
±2.048
V
V
32
4
pF
pF
1.1
µs
±1
l
µA
(Note 5)
LTC1863/LTC1867/LTC1867A
PARAMETER
CONDITIONS
MIN
2.48
TYP
MAX
2.5
2.52
UNITS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
±15
ppm/°C
V
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
0.43
mV/V
VREF Output Resistance
IOUT ≤0.1mA
REFCOMP Output Voltage
IOUT = 0
6
kΩ
4.096
V
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V
l
VIL
Low Level Input Voltage
VDD = 4.75V
l
VIN = 0V to VDD
l
TYP
MAX
2.4
UNITS
V
0.8
V
±10
µA
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage (SDO)
VOL
Low Level Output Voltage (SDO)
ISOURCE
Output Source Current
SDO = 0V
–32
mA
ISINK
Output Sink Current
SDO = VDD
19
mA
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or VDD
CS/CONV = High (Note 10)
Data Format
Unipolar
Bipolar
VDD = 4.75V, IO = –10µA
VDD = 4.75V, IO = –200µA
l
VDD = 4.75V, IO = 160µA
VDD = 4.75V, IO = 1.6mA
l
4
2
pF
4.75
4.74
V
V
0.05
0.1
0.4
±10
15
l
l
V
V
µA
pF
Straight Binary
Two’s Complement
Rev. E
4
For more information www.analog.com
LTC1863/LTC1867
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Supply Voltage
(Note 9)
4.75
IDD
Supply Current
fSAMPLE = 200ksps
NAP Mode
SLEEP Mode
PDISS
MAX
UNITS
5.25
V
1.8
l
1.3
150
0.2
3
mA
µA
µA
l
6.5
9
mW
l
Power Dissipation
TYP
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863/LTC1867/LTC1867A
SYMBOL
PARAMETER
fSAMPLE
Maximum Sampling Frequency
CONDITIONS
l
MIN
tCONV
Conversion Time
l
tACQ
Acquisition Time
l
fSCK
SCK Frequency
TYP
MAX
200
kHz
3
1.5
3.5
1.1
t1
CS/CONV High Time
Short CS/CONV Pulse Mode
l
SDO Valid After SCK↓
CL = 25pF (Note 11)
l
t3
SDO Valid Hold Time After SCK↓
CL = 25pF
l
t4
SDO Valid After CS/CONV↓
CL = 25pF
l
t5
SDI Setup Time Before SCK↑
t6
SDI Hold Time After SCK↑
t7
SLEEP Mode Wake-Up Time
CREFCOMP = 10µF, CVREF = 2.2µF
t8
Bus Relinquish Time After CS/CONV↑
CL = 25pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime
Note 2: All voltage values are with respect to GND (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
up to 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents up to
100mA below GND without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 200ksps at 25°C, t r = tf = 5ns and
VIN– = 2.5V for bipolar mode unless otherwise specified.
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
40
5
15
l
10
MHz
ns
22
11
10
l
l
100
13
µs
µs
40
t2
UNITS
ns
ns
30
–6
ns
ns
4
ns
60
ms
20
40
ns
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and
0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage measured
from –1/2LSB when output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111 for LTC1867, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863.
Note 9: Recommended operating conditions. The input range of ±2.048V
for bipolar mode is measured with respect to VIN– = 2.5V.
Note 10: Guaranteed by design, not subject to test.
Note 11: t2 of 25ns maximum allows fSCK up to 20MHz for rising capture
with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns
setup time for the receiving logic).
Rev. E
For more information www.analog.com
5
LTC1863/LTC1867
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1867)
Differential Nonlinearity vs
Output Code
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
– 0.5
–0.5
–1.0
– 1.5
–1.5
16384
32768
49152
OUTPUT CODE
–2.0
65536
0
16384
32768
49152
OUTPUT CODE
–60
–80
–100
65536
25
50
75
100
SNR = 90dB
SINAD = 88.5dB
THD = 94dB
fSAMPLE = 200ksps
VREF = 0V
REFCOMP = EXT 5V
–20
–40
–60
–80
–140
0
FREQUENCY (kHz)
25
50
100
75
NONADJACENT PAIR
–140
1
10
100
1000
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
18637 G06
Total Harmonic Distortion vs
Input Frequency
80
–40
AMPLITUDE (dB)
80
AMPLITUDE (dB)
–30
AMPLITUDE (dB)
4
–130
90
70
60
50
–50
–60
–70
40
40
–80
30
30
–90
18637 G07
0
3
–120
90
100
5
ADJACENT PAIR
–110
–20
10
INPUT FREQUENCY (kHz)
2
–100
100
1
1
–90
100
50
0
–80
Signal-to-(Noise + Distortion) vs
Input Frequency
60
–1
18637 G05
Signal-to-Noise Ratio vs
Frequency
70
–2
18637 GO3
FREQUENCY (kHz)
18637 G04
20
–4 –3
Crosstalk vs Input Frequency
–120
0
122
26
CODE
–100
–120
–140
0
AMPLITUDE (dB)
AMPLITUDE (dB)
–40
0
4096 Points FFT Plot (fIN = 1kHz,
REFCOMP = External 5V)
SNR = 88.8dB
SINAD = 87.9dB
THD = 95dB
fSAMPLE = 200ksps
INTERNAL REFERENCE
276
1
18637 GO2
4096 Points FFT Plot (fIN = 1kHz)
–20
935
1000
579
18637 GO1
0
1500
500
RESULTING AMPLITUDE ON
SELECTED CHANNEL (dB)
0
2152
2000
0
– 1.0
– 2.0
Histogram for 4096 Conversions
2500
COUNTS
2.0
DNL (LSB)
INL (LBS)
Integral Nonlinearity vs
Output Code
20
1
10
INPUT FREQUENCY (kHz)
100
18637 G08
–100
1
10
INPUT FREQUENCY (kHz)
100
18637 G09
Rev. E
6
For more information www.analog.com
LTC1863/LTC1867
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1863/LTC1867)
Supply Current vs Supply Voltage
Supply Current vs fSAMPLE
1.5
VDD = 5V
0.5
1.3
1.2
10
100
fSAMPLE (ksps)
1000
1.0
4.5
5.0
4.75
5.25
SUPPLY VOLTAGE (V)
18637 G10
5.5
1.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
18637 G12
Differential Nonlinearity vs
Output Code (LTC1863)
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
0
1.2
18637 G11
Integral Nonlinearity vs Output
Code (LTC1863)
–1.0
1.3
1.1
1.1
1
VDD = 5V
fSAMPLE = 200ksps
1.4
DNL (LBS)
0
VDD = 5V
fSAMPLE = 200ksps
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.0
Supply Current vs Temperature
1.5
1.4
1.5
INL (LBS)
SUPPLY CURRENT (mA)
2.0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
18637 G13
18637 G14
Rev. E
For more information www.analog.com
7
LTC1863/LTC1867
PIN FUNCTIONS
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with a 10µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor (4.096V Nominal). To overdrive
REFCOMP, tie VREF to GND.
VREF (Pin 10): 2.5V Reference Output. This pin can also
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with a 2.2µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion result
is shifted out of this output. Straight binary format for unipolar mode and two’s complement format for bipolar mode.
SDI (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
VDD (Pin 16): Analog and Digital Power Supply. Bypass
to GND with a 10µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor. When powering up the LTC1863/
LTC1867, or any time VDD falls below the minimum specified operating voltage, one dummy conversion must be
initiated by providing a rising edge on the CS/CONV pin.
The first conversion result may be invalid and should be
ignored. Once the CS/CONV pin is returned low, a DIN
word can be shifted into SDI to program the configuration for the next conversion. Wait at least t7, the SLEEP
mode wake-up time of 80ms, before initiating the second
conversion to obtain a valid conversion result.
TYPICAL CONNECTION DIAGRAM
±2.048V
DIFFERENTIAL
INPUTS
+
CH0
VDD
–
CH1
GND
SDI
CH2
4.096V
SINGLE-ENDED
INPUT
CH3
+
5V
LTC1863/
LTC1867
SDO
CH4
SCK
CH5
CH6
CS/CONV
VREF
CH7/COM
DIGITAL
I/O
4.096V
10µF
REFCOMP
18637 TCD
2.5V
2.2µF
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
3k
3k
DN
DN
DN
3k
CL
(A) Hi-Z TO VOH AND VOL TO VOH
DN
3k
CL
(B) Hi-Z TO VOL AND VOH TO VOL
18637 TC01
(A) VOH TO Hi-Z
CL
CL
(B) VOL TO Hi-Z
18637 TC02
Rev. E
8
For more information www.analog.com
LTC1863/LTC1867
TIMING DIAGRAMS
t1 (For Short Pulse Mode)
t2 (SDO Valid Before SCK↑),
t3 (SDO Valid Hold Time After SCK↓)
t1
t2
50%
50%
CS/CONV
SCK
0.4V
t3
2.4V
0.4V
SDO
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
t4 (SDO Valid After CONV↓)
t4
CS/CONV
SDO
2.4V
SCK
0.4V
Hi-Z
2.4V
0.4V
SDI
t7 (SLEEP Mode Wake-Up Time)
2.4V
0.4V
2.4V
0.4V
t8 (BUS Relinquish Time)
t7
SCK
t6
t5
t8
50%
CS/CONV
2.4V
SLEEP BIT (SLP = 0)
READ-IN
CS/CONV
50%
SDO
90%
10%
Hi-Z
1867 TD
APPLICATIONS INFORMATION
Overview
The LTC1863/LTC1867 are complete, low power multiplexed ADCs. They consist of a 12-/16-bit, 200ksps capacitive successive approximation A/D converter, a precision
internal reference, a configurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5µs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
Rev. E
For more information www.analog.com
9
LTC1863/LTC1867
APPLICATIONS INFORMATION
Analog Input Multiplexer
Changing the MUX Assignment “On the Fly”
1st Conversion
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defined as follows:
+
–{
+
–{
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
2nd Conversion
CH2
CH3
–
+
{
CH2
CH3
CH4
CH5
+
+
{
CH4
CH5
CH7/COM
(UNUSED)
CH7/COM (–)
S1 = ADDRESS SELECT BIT 1
18637 AI02
S0 = ADDRESS SELECT BIT 0
Tables 1 and 2 show the configurations when COM = 0,
and COM = 1.
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
Table 1. Channel Configuration (When COM = 0, CH7/COM Pin
Is Used as CH7)
SLP = SLEEP MODE BIT
SD
Examples of Multiplexer Options
4 Differential
+ (–)
– (+) {
+ (–)
– (+) {
CH0
CH1
+ (–)
– (+) {
+ (–)
– (+) {
CH4
CH5
CH2
CH3
CH6
CH7/COM
7 Single-Ended
to CH7/COM
+
+
+
+
+
+
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM (–)
8 Single-Ended
+
+
+
+
+
+
+
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (–)
Combinations of Differential
and Single-Ended
+
–{
CH0
CH1
–
+{
+
+
+
+
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (–)
OS
S1
S0
COM
Channel Configuration
“+”
“–”
0
0
0
0
0
CH0
CH1
0
0
0
1
0
CH2
CH3
0
0
1
0
0
CH4
CH5
0
0
1
1
0
CH6
CH7
0
1
0
0
0
CH1
CH0
0
1
0
1
0
CH3
CH2
0
1
1
0
0
CH5
CH4
0
1
1
1
0
CH7
CH6
1
0
0
0
0
CH0
GND
1
0
0
1
0
CH2
GND
1
0
1
0
0
CH4
GND
1
0
1
1
0
CH6
GND
1
1
0
0
0
CH1
GND
1
1
0
1
0
CH3
GND
1
1
1
0
0
CH5
GND
1
1
1
1
0
CH7
GND
Table 2. Channel Configuration (When COM = 1, CH7/COM Pin
Is Used as COMMON)
Channel Configuration
18637 AI01
SD
OS
S1
S0
COM
“+”
“–”
1
0
0
0
1
CH0
CH7/COM
1
0
0
1
1
CH2
CH7/COM
1
0
1
0
1
CH4
CH7/COM
1
0
1
1
1
CH6
CH7/COM
1
1
0
0
1
CH1
CH7/COM
1
1
0
1
1
CH3
CH7/COM
1
1
1
0
1
CH5
CH7/COM
Rev. E
10
For more information www.analog.com
LTC1863/LTC1867
APPLICATIONS INFORMATION
Driving the Analog Inputs
The analog inputs of the LTC1863/LTC1867 are easy to
drive. Each of the analog inputs can be used as a singleended input relative to the GND pin (CH0-GND, CH1-GND,
etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regardless of the MUX configuration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors during the acquire mode.
In conversion mode, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low then the LTC1863/LTC1867 inputs can be
driven directly. More acquisition time should be allowed
for a higher impedance source.
The following list is a summary of the op amps that are
suitable for driving the LTC1863/LTC1867.
LT1007 - Low noise precision amplifier. 2.7mA supply
current ± 5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ± 15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply
current. ±5V to ±15V supplies. Good AC/DC specs.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply
current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good
AC/DC specs.
LT1468 - 90MHz, 22V/µs 16-bit accurate amplifier
LT1469 - Dual LT1468
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1863/LTC1867 noise and distortion. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Rev. E
For more information www.analog.com
11
LTC1863/LTC1867
APPLICATIONS INFORMATION
50Ω
ANALOG
INPUT
Dynamic Performance
CH0
LTC1863/
LTC1867
2000pF
GND
REFCOMP
10µF
1867 F01a
Figure 1a. Optional RC Input Filtering for Single-Ended Input
1000pF
50Ω
DIFFERENTIAL
ANALOG
INPUTS
CH0
LTC1863/
LTC1867
1000pF
50Ω
CH1
1000pF
REFCOMP
10µF
1867 F01b
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3 shows a typical SINAD of 87.9dB
with a 200kHz sampling rate and a 1kHz input. When an
external 5V is applied to REFCOMP (tie VREF to GND), a
signal-to-noise ratio of 90dB can be achieved.
Figure 1b. Optional RC Input Filtering for Differential Inputs
0
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition noise is about 0.74LSB.
–40
AMPLITUDE (dB)
DC Performance
–20
SNR = 88.8dB
SINAD = 87.9dB
THD = 95dB
fSAMPLE = 200ksps
INTERNAL REFERENCE
–60
–80
–100
–120
–140
0
25
50
100
75
FREQUENCY (kHz)
2500
18637 G04
2152
Figure 3. LTC1867 Nonaveraged 4096 Point FFT Plot
COUNTS
2000
Total Harmonic Distortion
1500
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
935
1000
579
500
0
276
1
122
26
–4 –3
–2
–1
0
1
2
5
0
3
4
2
CODE
THD = 20 log
18637 GO3
Figure 2. LTC1867 Histogram for 4096 Conversions
2
2
V2 + V3 + V4 ... + VN
V1
2
Rev. E
12
For more information www.analog.com
LTC1863/LTC1867
APPLICATIONS INFORMATION
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
Internal Reference
The LTC1863/LTC1867 has an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.5V. It is internally connected
to a reference amplifier and is available at VREF (Pin 10).
A 6k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplifier gains the VREF voltage by 1.638V/V
to 4.096V at REFCOMP (Pin 9). This reference amplifier
compensation pin, REFCOMP, must be bypassed with a
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance.
2.5V
R1
6k
10 VREF
BANDGAP
REFERENCE
2.2µF
4.096V
9 REFCOMP
REFERENCE
AMP
10µF
R2
R3
15 GND
Digital Interface
The LTC1863/LTC1867 have a very simple digital interface
that is enabled by the control input, CS/CONV. A logic rising
edge applied to the CS/CONV input will initiate a conversion.
After the conversion, taking CS/CONV low will enable the
serial port and the ADC will present digital data in two’s
complement format in bipolar mode or straight binary
format in unipolar mode, through the SCK/SDO serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3µs and a maximum conversion time,
3.5µs, over the full operating temperature range. The typical acquisition time is 1.1µs, and a throughput sampling
rate of 200ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863/LTC1867 go into automatic nap mode when
CS/CONV is held high after the conversion is complete
(see Figure 6). With a typical operating current of 1.3mA
and automatic 150µA nap mode between conversions, the
power dissipation drops with reduced sample rate. The
ADC only keeps the VREF and REFCOMP voltages active
when the part is in the automatic nap mode. The slower the
sample rate allows the power dissipation to be lower (see
Figure 5).
LTC1863/LTC1867
1867 F04a
2.0
Figure 4a. LTC1867 Reference Circuit
SUPPLY CURRENT (mA)
5V
VIN
LT1019A-2.5
VOUT
+
10
2.2µF
VREF
LTC1863/
LTC1867
9
REFCOMP
10µF
0.1µF
15
1.5
1.0
0.5
0
GND
1867 F04b
Figure 4b. Using the LT1019-2.5 as an External Reference
VDD = 5V
1
10
100
fSAMPLE (ksps)
1000
18637 G10
Figure 5. Supply Current vs fSAMPLE
Rev. E
For more information www.analog.com
13
LTC1863/LTC1867
APPLICATIONS INFORMATION
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that
the CS/CONV returns low either within 100ns after the
conversion starts (i.e. before the first bit decision) or
after the conversion ends. If CS/CONV is low when the
conversion ends, the MSB bit will appear on SDO at the
end of the conversion and the ADC will remain powered
up (see Figure 7).
of the common return for these bypass capacitors is essential to the low noise operation of the ADC. The width
for these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital
input. The rising edge transition of the CS/CONV will start
a conversion. Once initiated, it cannot be restarted until
the conversion is complete. Figure 6 and Figure 7 show
the timing diagrams for two types of CS/CONV pulses.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC
will enter SLEEP mode and draw only leakage current
(provided that all the digital inputs stay at GND or VDD).
After release from the SLEEP mode, the ADC need 60ms
to wake up (2.2µF/10µF bypass capacitors on VREF/
REFCOMP pins).
Example 1 (Figure 6) shows the LTC1863/LTC1867 operating in automatic nap mode with CS/CONV signal staying
HIGH after the conversion. Automatic nap mode provides
power reduction at reduced sample rate. The ADCs can also
operate with the CS/CONV signal returning LOW before
the conversion ends. In this mode (Example 2, Figure 7),
the ADCs remain powered up.
Board Layout and Bypassing
For best performance, it is recommended to keep SCK, SDI,
and SDO at a constant logic high or low during acquisition
and conversion, even though these signals may be ignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
the conversion period (tCONV).
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
Figure 8 and Figure 9 are the transfer characteristics for
the bipolar and unipolar mode.
All analog inputs should be screened by GND. VREF,
REFCOMP and VDD should be bypassed to this ground
plane as close to the pin as possible; the low impedance
tACQ
1/fSCK
CS/CONV
tCONV
NAP MODE
NOT NEEDED FOR LTC1863
SCK
DON'T CARE
1
2
3
4
SDI
DON'T CARE
SD
0S
S1
S0
D9
D8
SDO
(LTC1863)
SDO
(LTC1867)
5
6
7
COM UNI
SLP
8
9
10
11
12
14
15
16
DON'T CARE
DON'T CARE
Hi-Z
MSB
D11 D10
D6
D5
D4
D3
D2
D1
D0
Hi-Z
MSB
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D7
13
D3
D2
D1
D0
1867 F06
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH After the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate.
Rev. E
14
For more information www.analog.com
LTC1863/LTC1867
APPLICATIONS INFORMATION
tACQ
CS/CONV
NOT NEEDED FOR LTC1863
SCK
SDI
DON'T CARE
1
2
3
4
5
6
7
COM UNI
SLP
8
9
10
11
12
SD
0S
S1
S0
MSB = D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
MSB = D15
D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
13
14
15
DON'T CARE
16
DON'T CARE
tCONV
SDO
(LTC1863)
Hi-Z
SDO
(LTC1867)
Hi-Z
D7
tCONV
D3
D2
D1
D0
1867 F07
111...111
011...111
111...110
BIPOLAR
ZERO
011...110
OUTPUT CODE
OUTPUT CODE (TWO’S COMPLEMENT)
Figure 7. Example 2, CS/CONV Starts a Conversion With Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up
000...001
000...000
111...111
111...110
FS = 4.096
1LSB = FS/2n
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5µV
100...001
100...000
–FS/2
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
FS = 4.096
1LSB = FS/2n
1LSB = (LTC1863) = 1mV
1LSB = (LTC1867) = 62.5µV
000...001
000...000
FS/2 – 1LSB
0V
FS – 1LSB
INPUT VOLTAGE (V)
1867 F08
Figure 8. LTC1863/LTC1867 Bipolar Transfer
Characteristics (Two’s Complement)
1867 F09
Figure 9. LTC1863/LTC1867 Unipolar Transfer
Characteristics (Straight Binary)
Rev. E
For more information www.analog.com
15
LTC1863/LTC1867
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic
(Narrow .150 Inch)
GNSSOP
Package
(Reference LTC DWG # 05-08-1641 Rev B)
16-Lead
Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.0250
(0.635)
BSC
GN16 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Rev. E
16
For more information www.analog.com
LTC1863/LTC1867
REVISION HISTORY
REV
DATE
DESCRIPTION
B
6/14
Fixed the Order Information.
PAGE NUMBER
2
C
5/15
Adjusted Notes 3 and 4 to specify input currents up to 100mA.
5
D
2/18
Added dummy conversion requirement on power up to VDD pin description
8
E
4/19
Added Automotive AEC-Q100 qualified products
2
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
17
LTC1863/LTC1867
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
14-Bit, 400ksps Serial ADC
20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package
LT1460
Micropower Precision Series Reference
Bandgap, 130µA Supply Current, 10ppm/°C, SOT-23 Package
LT1468/LT1469
Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amps
Low Input Offset: 75µV/125µV
LTC1609
16-Bit, 200ksps Serial ADC
65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply
LT1790
Micropower Low Dropout Reference
60µA Supply Current, 10ppm/°C, SOT-23 Package
LTC1850/LTC1851
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
Parallel Output, Programmable MUX and Sequencer, 5V Supply
LTC1852/LTC1853
10-Bit/12-Bit, 8-Channel, 400ksps ADC
Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply
LTC1860/LTC1861
12-Bit, 1-/2-Channel 250ksps ADC in MSOP
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L
3V, 12-Bit, 1-/2-Channel 150ksps ADC
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1864/LTC1865
16-Bit, 1-/2-Channel 250ksps ADC in MSOP
850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L
3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
Rev. E
18
04/19
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